ROM_CTRL/64KB Simulation Results

Thursday April 25 2024 19:02:55 UTC

GitHub Revision: b938dde05c

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 108701404146925295560026896903905201131509842528412483454495187515568509489952

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	1.316m	30.866ms	49	50	98.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	33.870s	13.295ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	28.910s	3.553ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	27.190s	10.896ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	27.030s	12.534ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	32.120s	4.126ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	28.910s	3.553ms	20	20	100.00
		rom_ctrl_csr_aliasing	27.030s	12.534ms	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	30.920s	18.370ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	28.290s	7.498ms	5	5	100.00
V1		TOTAL			114	115	99.13
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	35.810s	61.472ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	3.259m	114.446ms	50	50	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	1.188m	41.737ms	50	50	100.00
V2	alert_test	rom_ctrl_alert_test	33.550s	3.997ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	34.680s	4.122ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	34.680s	4.122ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	33.870s	13.295ms	5	5	100.00
		rom_ctrl_csr_rw	28.910s	3.553ms	20	20	100.00
		rom_ctrl_csr_aliasing	27.030s	12.534ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	35.280s	7.893ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	33.870s	13.295ms	5	5	100.00
		rom_ctrl_csr_rw	28.910s	3.553ms	20	20	100.00
		rom_ctrl_csr_aliasing	27.030s	12.534ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	35.280s	7.893ms	20	20	100.00
V2		TOTAL			240	240	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	17.904m	272.924ms	49	50	98.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	3.119m	23.231ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	2.234m	2.899ms	5	5	100.00
		rom_ctrl_tl_intg_err	2.869m	8.703ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	2.234m	2.899ms	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	17.904m	272.924ms	49	50	98.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	17.904m	272.924ms	49	50	98.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	17.904m	272.924ms	49	50	98.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	17.904m	272.924ms	49	50	98.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	17.904m	272.924ms	49	50	98.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	2.234m	2.899ms	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	2.234m	2.899ms	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	1.316m	30.866ms	49	50	98.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	1.316m	30.866ms	49	50	98.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	1.316m	30.866ms	49	50	98.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	2.869m	8.703ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	17.904m	272.924ms	49	50	98.00
		rom_ctrl_kmac_err_chk	1.188m	41.737ms	50	50	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	17.904m	272.924ms	49	50	98.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	17.904m	272.924ms	49	50	98.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	17.904m	272.924ms	49	50	98.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	3.119m	23.231ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	2.234m	2.899ms	5	5	100.00
V2S		TOTAL			94	95	98.95
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	2.805h	17.290ms	10	50	20.00
V3		TOTAL			10	50	20.00
		TOTAL			458	500	91.60

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	6	6	6	100.00
V2S	4	4	3	75.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.59	96.97	93.15	97.88	100.00	98.69	98.03	98.37

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:829) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 28 failures:

  • Test rom_ctrl_stress_all_with_rand_reset has 28 failures.

    • 0.rom_ctrl_stress_all_with_rand_reset.85590973126636444609252788883984303219113098964336831514063825239957730618358
      Line 278, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 10112921538 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 10112921538 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.rom_ctrl_stress_all_with_rand_reset.48427653004341103729343008908696307409598781814737242760381192458540354345468
      Line 468, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 29249724440 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 29249724440 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 26 more failures.

• UVM_FATAL (cip_base_vseq.sv:250) [rom_ctrl_common_vseq] Timeout waiting tl_access : addr=* has 7 failures:

  • Test rom_ctrl_stress_all_with_rand_reset has 7 failures.

    • 4.rom_ctrl_stress_all_with_rand_reset.110478474634973351967636598932095648848172627431710975929492578928657577601489
      Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 10010598015 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x9af8167b
        UVM_INFO @ 10010598015 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 12.rom_ctrl_stress_all_with_rand_reset.88069149084587456093543465512725864938070588473621264712799604415582968762714
      Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/12.rom_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 10003672298 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0xf413a966
        UVM_INFO @ 10003672298 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 5 more failures.

• Job rom_ctrl_64kB-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 5 failures:

  • Test rom_ctrl_stress_all_with_rand_reset has 5 failures.

    • 3.rom_ctrl_stress_all_with_rand_reset.18610446562839967348033153975031951971247726742581891401233072223575368275333
      Log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_stress_all_with_rand_reset/latest/run.log

        Job ID: smart:0a6a3925-1fb9-4430-b89f-6539c3f17ade
      

    • 10.rom_ctrl_stress_all_with_rand_reset.32943502982596729243617925696233083984164552492733649926314167641234371678960
      Log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/10.rom_ctrl_stress_all_with_rand_reset/latest/run.log

        Job ID: smart:1d6bfbbe-c3d9-4fe2-8ec1-690ecbe0b167
      

    • ... and 3 more failures.

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:

  • Test rom_ctrl_corrupt_sig_fatal_chk has 1 failures.

    • 38.rom_ctrl_corrupt_sig_fatal_chk.19082077311893691844492952496650477403846030501252028137033331782168597316261
      Line 289, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/38.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log

        UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (cip_base_vseq.sv:250) [rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=* has 1 failures:

  • Test rom_ctrl_smoke has 1 failures.

    • 42.rom_ctrl_smoke.70875634703420010121723726935420208286465384838088072651764433341737897618181
      Line 251, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/42.rom_ctrl_smoke/latest/run.log

        UVM_FATAL @ 40026017495 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0x61273213
        UVM_INFO @ 40026017495 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• 2024.04.24_08.08.04
• 2024.04.22_07.31.34