Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

576043

1

T3

26

T4

27

T5

37

full_word

357789

1

T3

4

T4

3

T5

4

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	933532	1			T3	30		T4	30		T5	41
auto[TlIntgErrCmd]	104	1			T79	3		T80	3		T81	1
auto[TlIntgErrData]	112	1			T79	3		T80	2		T81	4
auto[TlIntgErrBoth]	84	1			T79	4		T80	5		T81	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

165977

1

T3

30

T4

30

T5

41

auto[1]

767855

1

T14

4309

T15

4625

T16

589

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	79797	1			T3	26		T4	27		T5	37
auto[TlIntgErrNone]	partial	auto[1]	495970	1			T14	2689		T15	3051		T16	424
auto[TlIntgErrNone]	full_word	auto[0]	86035	1			T3	4		T4	3		T5	4
auto[TlIntgErrNone]	full_word	auto[1]	271730	1			T14	1620		T15	1574		T16	165
auto[TlIntgErrCmd]	partial	auto[0]	47	1			T79	2		T80	1		T81	1
auto[TlIntgErrCmd]	partial	auto[1]	47	1			T79	1		T80	2		T142	1
auto[TlIntgErrCmd]	full_word	auto[0]	6	1			T144	1		T145	1		T146	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T140	1		T144	1		T147	1
auto[TlIntgErrData]	partial	auto[0]	51	1			T79	1		T80	1		T142	1
auto[TlIntgErrData]	partial	auto[1]	50	1			T79	2		T80	1		T81	4
auto[TlIntgErrData]	full_word	auto[0]	7	1			T137	1		T141	1		T148	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T145	1		T149	1		T150	2
auto[TlIntgErrBoth]	partial	auto[0]	32	1			T81	1		T137	2		T139	1
auto[TlIntgErrBoth]	partial	auto[1]	49	1			T79	4		T80	5		T81	4
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T140	1		T151	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	1	1			T149	1		-	-		-	-