Unified Coverage Report :: Module :: prim_generic_rom

Module : prim_generic_rom

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.89	66.67				100.00	100.00

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/sim-vcs/../src/lowrisc_prim_generic_rom_0/rtl/prim_generic_rom.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_rom_scramble_enabled.u_rom.u_rom.u_prim_rom.gen_generic.u_impl_generic	88.89	66.67				100.00	100.00

---

Module Instance : tb.dut.gen_rom_scramble_enabled.u_rom.u_rom.u_prim_rom.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.89	66.67				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.89	66.67				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_prim_rom

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : prim_generic_rom

	Line No.	Total	Covered	Percent
TOTAL		3	2	66.67
CONT_ASSIGN	22	1	0	0.00
ALWAYS	27	2	2	100.00

21                        logic unused_cfg;
22         0/1     ==>    assign unused_cfg = ^cfg_i;
23                      
24                        logic [Width-1:0] mem [Depth];
25                      
26                        always_ff @(posedge clk_i) begin
27         1/1              if (req_i) begin
           Tests:       T1 T2 T3 
28         1/1                rdata_o <= mem[addr_i];
           Tests:       T1 T2 T3 
29                          end
                        MISSING_ELSE

---

Branch Coverage for Module : prim_generic_rom

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	27	2	2	100.00

27             if (req_i) begin
               -1-  
28               rdata_o <= mem[addr_i];
                 ==>
29             end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_generic_rom

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
noXOnCsI	50861356	50861356	0	0

noXOnCsI

Name	Attempts	Real Successes	Failures	Incomplete
Total	50861356	50861356	0	0
T1	24784	24784	0	0
T2	24978	24978	0	0
T3	17588	17588	0	0
T4	17521	17521	0	0
T5	17442	17442	0	0
T6	25824	25824	0	0
T7	18052	18052	0	0
T8	25686	25686	0	0
T9	25886	25886	0	0
T10	17562	17562	0	0