Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

491185

1

T3

147

T4

39

T5

222

full_word

307588

1

T3

14

T4

4

T5

26

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	798513	1			T3	161		T4	43		T5	248
auto[TlIntgErrCmd]	81	1			T81	5		T82	3		T83	4
auto[TlIntgErrData]	89	1			T81	1		T82	1		T83	4
auto[TlIntgErrBoth]	90	1			T81	4		T82	6		T83	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

144988

1

T3

161

T4

43

T5

248

auto[1]

653785

1

T19

1571

T20

4148

T21

6653

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	70787	1			T3	147		T4	39		T5	222
auto[TlIntgErrNone]	partial	auto[1]	420161	1			T19	837		T20	2574		T21	4515
auto[TlIntgErrNone]	full_word	auto[0]	74084	1			T3	14		T4	4		T5	26
auto[TlIntgErrNone]	full_word	auto[1]	233481	1			T19	734		T20	1574		T21	2138
auto[TlIntgErrCmd]	partial	auto[0]	34	1			T81	3		T82	1		T141	2
auto[TlIntgErrCmd]	partial	auto[1]	40	1			T81	2		T82	2		T83	1
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T83	2		T139	1		T147	1
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T83	1		T144	1		T146	1
auto[TlIntgErrData]	partial	auto[0]	32	1			T83	2		T138	2		T141	2
auto[TlIntgErrData]	partial	auto[1]	47	1			T81	1		T82	1		T83	2
auto[TlIntgErrData]	full_word	auto[0]	5	1			T139	1		T148	1		T145	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T138	1		T149	1		T146	1
auto[TlIntgErrBoth]	partial	auto[0]	38	1			T81	2		T82	3		T83	1
auto[TlIntgErrBoth]	partial	auto[1]	46	1			T81	2		T82	2		T83	1
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T82	1		T142	1		T140	1
auto[TlIntgErrBoth]	full_word	auto[1]	2	1			T138	1		T150	1		-	-