Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

460125

1

T1

25

T3

131

T5

110

full_word

294644

1

T1

5

T3

9

T5

12

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	754419	1			T1	30		T3	140		T5	122
auto[TlIntgErrCmd]	111	1			T70	3		T71	4		T72	6
auto[TlIntgErrData]	116	1			T70	4		T71	5		T72	8
auto[TlIntgErrBoth]	123	1			T70	3		T71	1		T72	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

138414

1

T1

30

T3

140

T5

122

auto[1]

616355

1

T12

2700

T13

6715

T14

202

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	66805	1			T1	25		T3	131		T5	110
auto[TlIntgErrNone]	partial	auto[1]	393006	1			T12	1739		T13	4278		T14	136
auto[TlIntgErrNone]	full_word	auto[0]	71449	1			T1	5		T3	9		T5	12
auto[TlIntgErrNone]	full_word	auto[1]	223159	1			T12	961		T13	2437		T14	66
auto[TlIntgErrCmd]	partial	auto[0]	49	1			T70	3		T71	1		T72	5
auto[TlIntgErrCmd]	partial	auto[1]	53	1			T71	2		T131	3		T137	7
auto[TlIntgErrCmd]	full_word	auto[0]	1	1			T138	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	8	1			T71	1		T72	1		T139	1
auto[TlIntgErrData]	partial	auto[0]	52	1			T70	2		T71	2		T72	3
auto[TlIntgErrData]	partial	auto[1]	53	1			T70	2		T71	3		T72	4
auto[TlIntgErrData]	full_word	auto[0]	1	1			T140	1		-	-		-	-
auto[TlIntgErrData]	full_word	auto[1]	10	1			T72	1		T131	1		T137	1
auto[TlIntgErrBoth]	partial	auto[0]	49	1			T70	2		T72	4		T131	5
auto[TlIntgErrBoth]	partial	auto[1]	58	1			T70	1		T71	1		T72	2
auto[TlIntgErrBoth]	full_word	auto[0]	8	1			T132	1		T139	1		T134	2
auto[TlIntgErrBoth]	full_word	auto[1]	8	1			T131	1		T134	1		T141	1