Unified Coverage Report :: Module :: rom_ctrl_compare

Module : rom_ctrl_compare

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.53	100.00	97.67		100.00	100.00	100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/default/sim-vcs/../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl_compare.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_fsm_scramble_enabled.u_checker_fsm.u_compare	99.53	100.00	97.67		100.00	100.00	100.00

---

Module Instance : tb.dut.gen_fsm_scramble_enabled.u_checker_fsm.u_compare

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.53	100.00	97.67		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.95	100.00	97.67	90.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.67	100.00	96.36		100.00	96.97	100.00	gen_fsm_scramble_enabled.u_checker_fsm

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_done_sender	100.00	100.00				100.00	100.00
u_prim_count_addr	90.00			90.00
u_state_regs	100.00	100.00				100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rom_ctrl_compare

	Line No.	Total	Covered	Percent
TOTAL		24	24	100.00
ALWAYS	85	3	3	100.00
ALWAYS	88	7	7	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	114	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
CONT_ASSIGN	125	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	152	1	1	100.00
ALWAYS	154	4	4	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	177	1	1	100.00

84                      
85         3/3            `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Waiting)
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Waiting):
85.1                    `ifdef SIMULATION                                   
85.2                        prim_sparse_fsm_flop #(                           
85.3                          .StateEnumT(state_e),                            
85.4                          .Width($bits(state_e)),                          
85.5                          .ResetValue($bits(state_e)'(Waiting)),          
85.6                          .EnableAlertTriggerSVA(1), 
85.7                          .CustomForceName("state_q")          
85.8                        ) u_state_regs (                                        
85.9                          .clk_i   ( clk_i   ),                           
85.10                         .rst_ni  ( rst_ni ),                           
85.11                         .state_i ( state_d     ),                           
85.12                         .state_o (         )                            
85.13                       );                                                
85.14                       always_ff @(posedge clk_i or negedge rst_ni) begin 
85.15      1/1              if (!rst_ni) begin                               
           Tests:       T1 T2 T3 
85.16      1/1                state_q <= Waiting;                                
           Tests:       T1 T2 T3 
85.17                       end else begin                                    
85.18      1/1                state_q <= state_d;                                     
           Tests:       T1 T2 T3 
85.19                       end                                               
85.20                     end  
85.21                       u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o))       
85.22                       else begin                                                                           
85.23                         `ifdef UVM                                                                               
85.24                     uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 
85.25                                               "../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl_compare.sv", 85, "", 1);                                
85.26                   `else                                                                                    
85.27                     $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,         
85.28                            `PRIM_STRINGIFY(u_state_regs_A));                                                       
85.29                   `endif                                                              
85.30                       end 
85.31                     `else                                               
85.32                       prim_sparse_fsm_flop #(                           
85.33                         .StateEnumT(state_e),                            
85.34                         .Width($bits(state_e)),                          
85.35                         .ResetValue($bits(state_e)'(Waiting)),          
85.36                         .EnableAlertTriggerSVA(1)  
85.37                       ) u_state_regs (                                        
85.38                         .clk_i   ( `PRIM_FLOP_CLK   ),                           
85.39                         .rst_ni  ( `PRIM_FLOP_RST ),                           
85.40                         .state_i ( state_d     ),                           
85.41                         .state_o ( state_q     )                            
85.42                       );                                                
85.43                     `endif86                      
87                        always_comb begin
88         1/1              state_d = state_q;
           Tests:       T1 T2 T3 
89         1/1              fsm_alert = 1'b0;
           Tests:       T1 T2 T3 
90         1/1              unique case (state_q)
           Tests:       T1 T2 T3 
91                            Waiting: begin
92         2/2                  if (start_i) state_d = Checking;
           Tests:       T1 T2 T3  | T1 T2 T3 
                        MISSING_ELSE
93                            end
94                            Checking: begin
95         2/2                  if (addr_q == LastAddr) state_d = Done;
           Tests:       T1 T2 T3  | T1 T2 T3 
                        MISSING_ELSE
96                            end
97                            Done: begin
98                              // Final state
99                            end
100                           default: fsm_alert = 1'b1;
101                         endcase
102                       end
103                     
104                       // start_i should only be signalled when we're in the Waiting state
105                       //
106                       // SEC_CM: COMPARE.CTRL_FLOW.CONSISTENCY
107                       logic start_alert;
108        1/1            assign start_alert = start_i && (state_q != Waiting);
           Tests:       T1 T2 T3 
109                     
110                       // addr_q should be zero when we're in the Waiting state
111                       //
112                       // SEC_CM: COMPARE.CTR.CONSISTENCY
113                       logic wait_addr_alert;
114        1/1            assign wait_addr_alert = (state_q == Waiting) && (addr_q != '0);
           Tests:       T1 T2 T3 
115                     
116                       // addr_q should be LastAddr when we're in the Done state
117                       //
118                       // SEC_CM: COMPARE.CTR.CONSISTENCY
119                       logic done_addr_alert;
120        1/1            assign done_addr_alert = (state_q == Done) && (addr_q != LastAddr);
           Tests:       T1 T2 T3 
121                     
122                       // Increment addr_q on each cycle except the last when in Checking. The prim_count primitive
123                       // doesn't overflow but in case NumWords is not a power of 2, we need to take care of this
124                       // ourselves.
125        1/1            assign addr_incr = (state_q == Checking) && (addr_q != LastAddr);
           Tests:       T1 T2 T3 
126                     
127                       // SEC_CM: COMPARE.CTR.REDUN
128                       logic addr_ctr_alert;
129                       prim_count #(
130                         .Width(AW)
131                       ) u_prim_count_addr (
132                         .clk_i,
133                         .rst_ni,
134                         .clr_i(1'b0),
135                         .set_i(1'b0),
136                         .set_cnt_i('0),
137                         .incr_en_i(addr_incr),
138                         .decr_en_i(1'b0),
139                         .step_i(AW'(1)),
140                         .commit_i(1'b1),
141                         .cnt_o(addr_q),
142                         .cnt_after_commit_o(),
143                         .err_o(addr_ctr_alert)
144                       );
145                     
146                       logic [AW+5-1:0] digest_idx;
147                       logic [31:0]     digest_word, exp_digest_word;
148        1/1            assign digest_idx = {addr_q, 5'd31};
           Tests:       T1 T2 T3 
149        1/1            assign digest_word = digest_i[digest_idx -: 32];
           Tests:       T1 T2 T3 
150        1/1            assign exp_digest_word = exp_digest_i[digest_idx -: 32];
           Tests:       T1 T2 T3 
151                     
152        1/1            assign matches_d = matches_q && (digest_word == exp_digest_word);
           Tests:       T1 T2 T3 
153                       always_ff @(posedge clk_i or negedge rst_ni) begin
154        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
155        1/1                matches_q <= 1'b1;
           Tests:       T1 T2 T3 
156                         end else begin
157        1/1                if (state_q == Checking) begin
           Tests:       T1 T2 T3 
158        1/1                  matches_q <= matches_d;
           Tests:       T1 T2 T3 
159                           end
                        MISSING_ELSE
160                         end
161                       end
162                     
163        1/1            assign done_o = (state_q == Done);
           Tests:       T1 T2 T3 
164                     
165                       // Instantiate an explicit prim_mubi4_sender for the good signal. The logic is that we don't want
166                       // to make the actual check multi-bit (doing so properly would mean replicating the 32-bit
167                       // comparator) but we *do* want to make sure a synthesis tool doesn't optimize away the 4-bit
168                       // signal. The barrier from the primitive ensures that won't happen.
169                       prim_mubi4_sender
170                       u_done_sender (
171                         .clk_i,
172                         .rst_ni,
173                         .mubi_i (mubi4_bool_to_mubi(matches_q)),
174                         .mubi_o (good_o)
175                       );
176                     
177        1/1            assign alert_o = fsm_alert | start_alert | wait_addr_alert | done_addr_alert | addr_ctr_alert;
           Tests:       T1 T2 T3 

---

Cond Coverage for Module : rom_ctrl_compare

	Total	Covered	Percent
Conditions	43	42	97.67
Logical	43	42	97.67
Non-Logical	0	0
Event	0	0

 LINE       95
 EXPRESSION (addr_q == LastAddr)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       108
 EXPRESSION (start_i && (state_q != Waiting))
             ---1---    ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T23,T24,T56

 LINE       108
 SUB-EXPRESSION (state_q != Waiting)
                ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       114
 EXPRESSION ((state_q == Waiting) && (addr_q != '0))
             ----------1---------    -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T23,T24,T25

 LINE       114
 SUB-EXPRESSION (state_q == Waiting)
                ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       114
 SUB-EXPRESSION (addr_q != '0)
                -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       120
 EXPRESSION ((state_q == Done) && (addr_q != LastAddr))
             --------1--------    ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T24,T25,T56

 LINE       120
 SUB-EXPRESSION (state_q == Done)
                --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       120
 SUB-EXPRESSION (addr_q != LastAddr)
                ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       125
 EXPRESSION ((state_q == Checking) && (addr_q != LastAddr))
             ----------1----------    ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       125
 SUB-EXPRESSION (state_q == Checking)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       125
 SUB-EXPRESSION (addr_q != LastAddr)
                ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       152
 EXPRESSION (matches_q && (digest_word == exp_digest_word))
             ----1----    ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T10,T12,T57
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       152
 SUB-EXPRESSION (digest_word == exp_digest_word)
                ----------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       157
 EXPRESSION (state_q == Checking)
            ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       163
 EXPRESSION (state_q == Done)
            --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       177
 EXPRESSION (fsm_alert | start_alert | wait_addr_alert | done_addr_alert | addr_ctr_alert)
             ----1----   -----2-----   -------3-------   -------4-------   -------5------

-1-	-2-	-3-	-4-	-5-	Status	Tests
0	0	0	0	0	Covered	T1,T2,T3
0	0	0	0	1	Not Covered
0	0	0	1	0	Covered	T24,T25,T56
0	0	1	0	0	Covered	T23,T24,T25
0	1	0	0	0	Covered	T23,T24,T56
1	0	0	0	0	Covered	T2,T26,T27

---

FSM Coverage for Module : rom_ctrl_compare

Summary for FSM :: state_q

	Total	Covered	Percent
States	3	3	100.00	(Not included in score)
Transitions	2	2	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
Checking	92	Covered	T1,T2,T3
Done	95	Covered	T1,T2,T3
Waiting	91	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
Checking->Done	95	Covered	T1,T2,T3
Waiting->Checking	92	Covered	T1,T2,T3

---

Branch Coverage for Module : rom_ctrl_compare

	Line No.	Total	Covered	Percent
Branches		11	11	100.00
IF	85	2	2	100.00
CASE	90	6	6	100.00
IF	154	3	3	100.00

85           `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Waiting)
             -1-                                                                       
             ==>                                                                       
             ==>                                                                       

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             unique case (state_q)
                      -1-  
91               Waiting: begin
92                 if (start_i) state_d = Checking;
                   -2-  
                   ==>
                   MISSING_ELSE
                   ==>
93               end
94               Checking: begin
95                 if (addr_q == LastAddr) state_d = Done;
                   -3-  
                   ==>
                   MISSING_ELSE
                   ==>
96               end
97               Done: begin
                 ==>
98                 // Final state
99               end
100              default: fsm_alert = 1'b1;
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
Waiting	1	-	Covered	T1,T2,T3
Waiting	0	-	Covered	T1,T2,T3
Checking	-	1	Covered	T1,T2,T3
Checking	-	0	Covered	T1,T2,T3
Done	-	-	Covered	T1,T2,T3
default	-	-	Covered	T2,T26,T27

154            if (!rst_ni) begin
               -1-  
155              matches_q <= 1'b1;
                 ==>
156            end else begin
157              if (state_q == Checking) begin
                 -2-  
158                matches_q <= matches_d;
                   ==>
159              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Module : rom_ctrl_compare

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumWordsPositive_A	313	313	0	0
u_state_regs_A	42542906	42375650	0	0

NumWordsPositive_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313	313	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	42542906	42375650	0	0
T1	26028	25952	0	0
T2	30001	27680	0	0
T3	25734	25642	0	0
T4	24819	24740	0	0
T5	17694	17629	0	0
T6	17204	17109	0	0
T7	24835	24745	0	0
T8	17703	17637	0	0
T9	25790	25711	0	0
T10	55601	55449	0	0