Unified Coverage Report :: Module :: rom_ctrl

Module : rom_ctrl

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.99	100.00	98.28	97.26		100.00	79.41

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/default/sim-vcs/../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	94.99	100.00	98.28	97.26		100.00	79.41

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.99	100.00	98.28	97.26		100.00	79.41

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.11	96.77	92.13	97.68	100.00	98.19	97.91

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_alert_tx[0].u_alert_sender	100.00			100.00
gen_fsm_scramble_enabled.u_checker_fsm	97.59	100.00	97.22	90.00	100.00	98.31	100.00
gen_rom_scramble_enabled.u_rom	97.06	88.24		100.00		100.00	100.00
regs_tlul_assert_device	100.00						100.00
rom_ctrl_regs_csr_assert	100.00						100.00
rom_tlul_assert_device	97.55						97.55
u_mux	95.24	100.00	85.71			100.00
u_reg_regs	99.72	99.41	99.21	100.00		100.00	100.00
u_tl_adapter_rom	93.10	90.70	82.93	97.66		94.20	100.00
u_tl_rom_h2d_buf	100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rom_ctrl

	Line No.	Total	Covered	Percent
TOTAL		65	65	100.00
CONT_ASSIGN	120	1	1	100.00
CONT_ASSIGN	125	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	127	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	258	1	1	100.00
CONT_ASSIGN	313	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	415	1	1	100.00
CONT_ASSIGN	415	1	1	100.00
CONT_ASSIGN	415	1	1	100.00
CONT_ASSIGN	415	1	1	100.00
CONT_ASSIGN	415	1	1	100.00
CONT_ASSIGN	415	1	1	100.00
CONT_ASSIGN	415	1	1	100.00
CONT_ASSIGN	415	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	421	1	1	100.00
CONT_ASSIGN	421	1	1	100.00
CONT_ASSIGN	421	1	1	100.00
CONT_ASSIGN	421	1	1	100.00
CONT_ASSIGN	421	1	1	100.00
CONT_ASSIGN	421	1	1	100.00
CONT_ASSIGN	421	1	1	100.00
CONT_ASSIGN	421	1	1	100.00
CONT_ASSIGN	425	1	1	100.00
CONT_ASSIGN	427	1	1	100.00
CONT_ASSIGN	430	1	1	100.00
CONT_ASSIGN	431	1	1	100.00
CONT_ASSIGN	432	1	1	100.00
CONT_ASSIGN	433	1	1	100.00
CONT_ASSIGN	438	1	1	100.00
CONT_ASSIGN	442	1	1	100.00

119                         // SEC_CM: MEM.DIGEST
120        1/1              assign kmac_data_o = '{valid: kmac_rom_vld,
           Tests:       T1 T2 T3 
121                                                data: kmac_rom_data,
122                                                strb: kmac_pkg::MsgStrbW'({NumBytes{1'b1}}),
123                                                last: kmac_rom_last};
124                     
125        1/1              assign kmac_rom_rdy = kmac_data_i.ready;
           Tests:       T1 T2 T3 
126        1/1              assign kmac_done = kmac_data_i.done;
           Tests:       T1 T2 T3 
127        1/1              assign kmac_digest = kmac_data_i.digest_share0[255:0] ^ kmac_data_i.digest_share1[255:0];
           Tests:       T1 T2 T3 
128        1/1              assign kmac_err = kmac_data_i.error;
           Tests:       T1 T2 T3 
129                     
130                         logic unused_kmac_digest;
131        1/1              assign unused_kmac_digest = ^{
           Tests:       T1 T2 T3 
132                           kmac_data_i.digest_share0[kmac_pkg::AppDigestW-1:256],
133                           kmac_data_i.digest_share1[kmac_pkg::AppDigestW-1:256]
134                         };
135                     
136                       end : gen_kmac_scramble_enabled
137                       else begin : gen_kmac_scramble_disabled
138                         // Scrambling is disabled. Stub out all KMAC connections and waive the ignored signals.
139                     
140                         assign kmac_data_o = '0;
141                         assign kmac_rom_rdy = 1'b0;
142                         assign kmac_done = 1'b0;
143                         assign kmac_digest = '0;
144                         assign kmac_err = 1'b0;
145                     
146                         logic unused_kmac_inputs;
147                         assign unused_kmac_inputs = ^{kmac_data_i};
148                     
149                         logic unused_kmac_outputs;
150                         assign unused_kmac_outputs = ^{kmac_rom_vld, kmac_rom_data, kmac_rom_last};
151                     
152                       end : gen_kmac_scramble_disabled
153                     
154                       // TL interface ==============================================================
155                       // This buffer ensures that when we calculate bus_rom_prince_index by snooping on
156                       // rom_tl_i, we get a value that's buffered from the thing that goes into both the ECC
157                       // check and the addr_o output of u_tl_adapter_rom. That way, an injected 1- or 2-bit fault that
158                       // affects bus_rom_prince_index must either affect the ECC check (causing it to fail) OR it cannot
159                       // affect bus_rom_rom_index (so the address-tweakable scrambling will mean the read probably gets
160                       // garbage).
161                       //
162                       // SEC_CM: CTRL.REDUN
163                       tlul_pkg::tl_h2d_t tl_rom_h2d_downstream;
164                       prim_buf #(
165                         .Width($bits(tlul_pkg::tl_h2d_t))
166                       ) u_tl_rom_h2d_buf (
167                         .in_i (rom_tl_i),
168                         .out_o (tl_rom_h2d_downstream)
169                       );
170                     
171                       // Bus -> ROM adapter ========================================================
172                     
173                       logic rom_integrity_error;
174                     
175                       tlul_adapter_sram #(
176                         .SramAw(RomIndexWidth),
177                         .SramDw(32),
178                         .Outstanding(2),
179                         .ByteAccess(0),
180                         .ErrOnWrite(1),
181                         .CmdIntgCheck(1),
182                         .EnableRspIntgGen(1),
183                         .EnableDataIntgGen(SecDisableScrambling),
184                         .EnableDataIntgPt(!SecDisableScrambling), // SEC_CM: BUS.INTEGRITY
185                         .SecFifoPtr      (1)                      // SEC_CM: TLUL_FIFO.CTR.REDUN
186                       ) u_tl_adapter_rom (
187                         .clk_i,
188                         .rst_ni,
189                     
190                         .tl_i                       (tl_rom_h2d_downstream),
191                         .tl_o                       (rom_tl_o),
192                         .en_ifetch_i                (prim_mubi_pkg::MuBi4True),
193                         .req_o                      (bus_rom_req),
194                         .req_type_o                 (),
195                         .gnt_i                      (bus_rom_gnt),
196                         .we_o                       (),
197                         .addr_o                     (bus_rom_rom_index),
198                         .wdata_o                    (),
199                         .wmask_o                    (),
200                         .intg_error_o               (rom_integrity_error),
201                         .rdata_i                    (bus_rom_rdata),
202                         .rvalid_i                   (bus_rom_rvalid),
203                         .rerror_i                   (2'b00),
204                         .compound_txn_in_progress_o (),
205                         .readback_en_i              (prim_mubi_pkg::MuBi4False),
206                         .readback_error_o           (),
207                         .wr_collision_i             (1'b0),
208                         .write_pending_i            (1'b0)
209                       );
210                     
211                       // Snoop on the "upstream" TL transaction to infer the address to pass to the PRINCE cipher.
212        1/1            assign bus_rom_prince_index = (rom_tl_i.a_valid ?
           Tests:       T4 T5 T6 
213                                                      rom_tl_i.a_address[2 +: RomIndexWidth] :
214                                                      '0);
215                     
216                       // Unless there has been an injected fault, bus_rom_prince_index and bus_rom_rom_index should have
217                       // the same value.
218                       `ASSERT(BusRomIndicesMatch_A, bus_rom_prince_index == bus_rom_rom_index)
219                     
220                       // The mux ===================================================================
221                     
222                       logic mux_alert;
223                     
224                       rom_ctrl_mux #(
225                         .AW (RomIndexWidth),
226                         .DW (DataWidth)
227                       ) u_mux (
228                         .clk_i,
229                         .rst_ni,
230                         .sel_bus_i         (rom_select_bus),
231                         .bus_rom_addr_i    (bus_rom_rom_index),
232                         .bus_prince_addr_i (bus_rom_prince_index),
233                         .bus_req_i         (bus_rom_req),
234                         .bus_gnt_o         (bus_rom_gnt),
235                         .bus_rdata_o       (bus_rom_rdata),
236                         .bus_rvalid_o      (bus_rom_rvalid_raw),
237                         .chk_addr_i        (checker_rom_index),
238                         .chk_req_i         (checker_rom_req),
239                         .chk_rdata_o       (checker_rom_rdata),
240                         .rom_rom_addr_o    (rom_rom_index),
241                         .rom_prince_addr_o (rom_prince_index),
242                         .rom_req_o         (rom_req),
243                         .rom_scr_rdata_i   (rom_scr_rdata),
244                         .rom_clr_rdata_i   (rom_clr_rdata),
245                         .rom_rvalid_i      (rom_rvalid),
246                         .alert_o           (mux_alert)
247                       );
248                     
249                       // Squash all responses from the ROM to the bus if there's an internal integrity error from the
250                       // checker FSM or the mux. This avoids having to handle awkward corner cases in the mux: if
251                       // something looks bad, we'll complain and hang the bus transaction.
252                       //
253                       // Note that the two signals that go into internal_alert are both sticky. The mux explicitly
254                       // latches its alert_o output and the checker FSM jumps to an invalid scrap state when it sees an
255                       // error which, in turn, sets checker_alert.
256                       //
257                       // SEC_CM: BUS.LOCAL_ESC
258        1/1            assign bus_rom_rvalid = bus_rom_rvalid_raw & !internal_alert;
           Tests:       T1 T2 T3 
259                     
260                       // The ROM itself ============================================================
261                     
262                       if (!SecDisableScrambling) begin : gen_rom_scramble_enabled
263                     
264                         // SEC_CM: MEM.SCRAMBLE
265                         rom_ctrl_scrambled_rom #(
266                           .MemInitFile (BootRomInitFile),
267                           .Width       (DataWidth),
268                           .Depth       (RomSizeWords),
269                           .ScrNonce    (RndCnstScrNonce),
270                           .ScrKey      (RndCnstScrKey)
271                         ) u_rom (
272                           .clk_i,
273                           .rst_ni,
274                           .req_i         (rom_req),
275                           .rom_addr_i    (rom_rom_index),
276                           .prince_addr_i (rom_prince_index),
277                           .rvalid_o      (rom_rvalid),
278                           .scr_rdata_o   (rom_scr_rdata),
279                           .clr_rdata_o   (rom_clr_rdata),
280                           .cfg_i         (rom_cfg_i)
281                         );
282                     
283                       end : gen_rom_scramble_enabled
284                       else begin : gen_rom_scramble_disabled
285                     
286                         // If scrambling is disabled then instantiate a normal ROM primitive (no PRINCE cipher etc.).
287                         // Note that this "raw memory" doesn't have ECC bits either.
288                     
289                         prim_rom_adv #(
290                           .Width       (DataWidth),
291                           .Depth       (RomSizeWords),
292                           .MemInitFile (BootRomInitFile)
293                         ) u_rom (
294                           .clk_i,
295                           .rst_ni,
296                           .req_i    (rom_req),
297                           .addr_i   (rom_rom_index),
298                           .rvalid_o (rom_rvalid),
299                           .rdata_o  (rom_scr_rdata),
300                           .cfg_i    (rom_cfg_i)
301                         );
302                     
303                         // There's no scrambling, so "scrambled" and "clear" rdata are equal.
304                         assign rom_clr_rdata = rom_scr_rdata;
305                     
306                         // Since we're not generating a keystream, we don't use the rom_prince_index at all
307                         logic unused_prince_index;
308                         assign unused_prince_index = ^rom_prince_index;
309                     
310                       end : gen_rom_scramble_disabled
311                     
312                       // Zero expand checker rdata to pass to KMAC
313        1/1            assign kmac_rom_data = {{64-DataWidth{1'b0}}, checker_rom_rdata};
           Tests:       T1 T2 T3 
314                     
315                       // Register block ============================================================
316                     
317                       rom_ctrl_regs_reg2hw_t reg2hw;
318                       rom_ctrl_regs_hw2reg_t hw2reg;
319                       logic                  reg_integrity_error;
320                     
321                       rom_ctrl_regs_reg_top u_reg_regs (
322                         .clk_i,
323                         .rst_ni,
324                         .tl_i       (regs_tl_i),
325                         .tl_o       (regs_tl_o),
326                         .reg2hw     (reg2hw),
327                         .hw2reg     (hw2reg),
328                         .intg_err_o (reg_integrity_error)    // SEC_CM: BUS.INTEGRITY
329                        );
330                     
331                       // The checker FSM ===========================================================
332                     
333                       logic [255:0] digest_q, exp_digest_q;
334                       logic [255:0] digest_d;
335                       logic         digest_de;
336                       logic [31:0]  exp_digest_word_d;
337                       logic         exp_digest_de;
338                       logic [2:0]   exp_digest_idx;
339                     
340                       logic         checker_alert;
341                     
342                       if (!SecDisableScrambling) begin : gen_fsm_scramble_enabled
343                     
344                         rom_ctrl_fsm #(
345                           .RomDepth (RomSizeWords),
346                           .TopCount (8)
347                         ) u_checker_fsm (
348                           .clk_i,
349                           .rst_ni,
350                           .digest_i             (digest_q),
351                           .exp_digest_i         (exp_digest_q),
352                           .digest_o             (digest_d),
353                           .digest_vld_o         (digest_de),
354                           .exp_digest_o         (exp_digest_word_d),
355                           .exp_digest_vld_o     (exp_digest_de),
356                           .exp_digest_idx_o     (exp_digest_idx),
357                           .pwrmgr_data_o        (pwrmgr_data_o),
358                           .keymgr_data_o        (keymgr_data_o),
359                           .kmac_rom_rdy_i       (kmac_rom_rdy),
360                           .kmac_rom_vld_o       (kmac_rom_vld),
361                           .kmac_rom_last_o      (kmac_rom_last),
362                           .kmac_done_i          (kmac_done),
363                           .kmac_digest_i        (kmac_digest),
364                           .kmac_err_i           (kmac_err),
365                           .rom_select_bus_o     (rom_select_bus),
366                           .rom_addr_o           (checker_rom_index),
367                           .rom_req_o            (checker_rom_req),
368                           .rom_data_i           (checker_rom_rdata[31:0]),
369                           .alert_o              (checker_alert)
370                         );
371                     
372                       end : gen_fsm_scramble_enabled
373                       else begin : gen_fsm_scramble_disabled
374                     
375                         // If scrambling is disabled, there's no checker FSM.
376                     
377                         assign digest_d = '0;
378                         assign digest_de = 1'b0;
379                         assign exp_digest_word_d = '0;
380                         assign exp_digest_de = 1'b0;
381                         assign exp_digest_idx = '0;
382                     
383                         assign pwrmgr_data_o = PWRMGR_DATA_DEFAULT;
384                         // Send something other than '1 or '0 because the key manager has an "all ones" and an "all
385                         // zeros" check.
386                         assign keymgr_data_o = '{data: {128{2'b10}}, valid: 1'b1};
387                     
388                         assign kmac_rom_vld = 1'b0;
389                         assign kmac_rom_last = 1'b0;
390                     
391                         // Always grant access to the bus. Setting this to a constant should mean the mux gets
392                         // synthesized away completely.
393                         assign rom_select_bus = MuBi4True;
394                     
395                         assign checker_rom_index = '0;
396                         assign checker_rom_req = 1'b0;
397                         assign checker_alert = 1'b0;
398                     
399                         logic unused_fsm_inputs;
400                         assign unused_fsm_inputs = ^{kmac_rom_rdy, kmac_done, kmac_digest, digest_q, exp_digest_q};
401                     
402                       end : gen_fsm_scramble_disabled
403                     
404                       // Register data =============================================================
405                     
406                       // DIGEST and EXP_DIGEST registers
407                     
408                       // Repack signals to convert between the view expected by rom_ctrl_reg_pkg for CSRs and the view
409                       // expected by rom_ctrl_fsm. Register 0 of a multi-reg appears as the low bits of the packed data.
410                       for (genvar i = 0; i < 8; i++) begin: gen_csr_digest
411                         localparam int unsigned TopBitInt = 32 * i + 31;
412                         localparam bit [7:0] TopBit = TopBitInt[7:0];
413                     
414        8/8              assign hw2reg.digest[i].d = digest_d[TopBit -: 32];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
415        8/8              assign hw2reg.digest[i].de = digest_de;
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
416                     
417        8/8              assign hw2reg.exp_digest[i].d = exp_digest_word_d;
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
418        8/8              assign hw2reg.exp_digest[i].de = exp_digest_de && (i == exp_digest_idx);
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
419                     
420        8/8              assign digest_q[TopBit -: 32] = reg2hw.digest[i].q;
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
421        8/8              assign exp_digest_q[TopBit -: 32] = reg2hw.exp_digest[i].q;
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
422                       end
423                     
424                       logic bus_integrity_error;
425        1/1            assign bus_integrity_error = rom_integrity_error | reg_integrity_error;
           Tests:       T1 T2 T3 
426                     
427        1/1            assign internal_alert = checker_alert | mux_alert;
           Tests:       T1 T2 T3 
428                     
429                       // FATAL_ALERT_CAUSE register
430        1/1            assign hw2reg.fatal_alert_cause.checker_error.d  = internal_alert;
           Tests:       T1 T2 T3 
431        1/1            assign hw2reg.fatal_alert_cause.checker_error.de = internal_alert;
           Tests:       T1 T2 T3 
432        1/1            assign hw2reg.fatal_alert_cause.integrity_error.d  = bus_integrity_error;
           Tests:       T1 T2 T3 
433        1/1            assign hw2reg.fatal_alert_cause.integrity_error.de = bus_integrity_error;
           Tests:       T1 T2 T3 
434                     
435                       // Alert generation ==========================================================
436                     
437                       logic [NumAlerts-1:0] alert_test;
438        1/1            assign alert_test[AlertFatal] = reg2hw.alert_test.q &
           Tests:       T1 T2 T3 
439                                                       reg2hw.alert_test.qe;
440                     
441                       logic [NumAlerts-1:0] alerts;
442        1/1            assign alerts[AlertFatal] = bus_integrity_error | checker_alert | mux_alert;
           Tests:       T1 T2 T3 

---

Cond Coverage for Module : rom_ctrl

	Total	Covered	Percent
Conditions	58	57	98.28
Logical	58	57	98.28
Non-Logical	0	0
Event	0	0

 LINE       212
 EXPRESSION (rom_tl_i.a_valid ? rom_tl_i.a_address[2+:RomIndexWidth] : '0)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T7

 LINE       258
 EXPRESSION (bus_rom_rvalid_raw & ((!internal_alert)))
             ---------1--------   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T24,T25,T26
1	1	Covered	T4,T5,T7

 LINE       418
 EXPRESSION (exp_digest_de && (0 == exp_digest_idx))
             ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       418
 SUB-EXPRESSION (0 == exp_digest_idx)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       418
 EXPRESSION (exp_digest_de && (1 == exp_digest_idx))
             ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       418
 SUB-EXPRESSION (1 == exp_digest_idx)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       418
 EXPRESSION (exp_digest_de && (2 == exp_digest_idx))
             ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       418
 SUB-EXPRESSION (2 == exp_digest_idx)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       418
 EXPRESSION (exp_digest_de && (3 == exp_digest_idx))
             ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       418
 SUB-EXPRESSION (3 == exp_digest_idx)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       418
 EXPRESSION (exp_digest_de && (4 == exp_digest_idx))
             ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       418
 SUB-EXPRESSION (4 == exp_digest_idx)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       418
 EXPRESSION (exp_digest_de && (5 == exp_digest_idx))
             ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       418
 SUB-EXPRESSION (5 == exp_digest_idx)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       418
 EXPRESSION (exp_digest_de && (6 == exp_digest_idx))
             ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       418
 SUB-EXPRESSION (6 == exp_digest_idx)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       418
 EXPRESSION (exp_digest_de && (7 == exp_digest_idx))
             ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       418
 SUB-EXPRESSION (7 == exp_digest_idx)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       425
 EXPRESSION (rom_integrity_error | reg_integrity_error)
             ---------1---------   ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T27,T28,T29
1	0	Not Covered

 LINE       427
 EXPRESSION (checker_alert | mux_alert)
             ------1------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T24,T25,T26
1	0	Covered	T12,T30,T31

 LINE       438
 EXPRESSION (reg2hw.alert_test.q & reg2hw.alert_test.qe)
             ---------1---------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       442
 EXPRESSION (bus_integrity_error | checker_alert | mux_alert)
             ---------1---------   ------2------   ----3----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T24,T25,T26
0	1	0	Covered	T12,T30,T31
1	0	0	Covered	T27,T28,T29

---

Toggle Coverage for Module : rom_ctrl

	Total	Covered	Percent
Totals	62	56	90.32
Total Bits	2884	2805	97.26
Total Bits 0->1	1442	1402	97.23
Total Bits 1->0	1442	1403	97.30

Ports	62	56	90.32
Port Bits	2884	2805	97.26
Port Bits 0->1	1442	1402	97.23
Port Bits 1->0	1442	1403	97.30

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T10,T11,T12	Yes	T1,T2,T3	INPUT
rom_cfg_i.cfg[3:0]	No	No		No		INPUT
rom_cfg_i.cfg_en	No	No		No		INPUT
rom_cfg_i.test	No	No		No		INPUT
rom_tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rom_tl_i.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T7	Yes	T4,T5,T7	INPUT
rom_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T7	Yes	T4,T5,T7	INPUT
rom_tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T7,T8	Yes	T4,T6,T7	INPUT
rom_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
rom_tl_i.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T7	INPUT
rom_tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T7	INPUT
rom_tl_i.a_address[31:0]	Yes	Yes	T4,T5,T7	Yes	T4,T7,T8	INPUT
rom_tl_i.a_source[7:0]	Yes	Yes	T4,T5,T7	Yes	T4,T5,T6	INPUT
rom_tl_i.a_size[1:0]	Yes	Yes	T4,T5,T7	Yes	T4,T5,T7	INPUT
rom_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
rom_tl_i.a_opcode[2:0]	Yes	Yes	T7,T8,T10	Yes	T7,T8,T10	INPUT
rom_tl_i.a_valid	Yes	Yes	T4,T5,T7	Yes	T4,T5,T7	INPUT
rom_tl_o.a_ready	Yes	Yes	T7,T11,T20	Yes	T1,T2,T3	OUTPUT
rom_tl_o.d_error	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
rom_tl_o.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T7	Yes	T4,T5,T7	OUTPUT
rom_tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T4,*T5,*T7	Yes	T4,T5,T7	OUTPUT
rom_tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
rom_tl_o.d_data[31:0]	Yes	Yes	T4,T5,T7	Yes	T4,T5,T7	OUTPUT
rom_tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
rom_tl_o.d_source[7:0]	Yes	Yes	T4,T5,T7	Yes	T4,T5,T7	OUTPUT
rom_tl_o.d_size[1:0]	Yes	Yes	T4,T5,T7	Yes	T4,T5,T7	OUTPUT
rom_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
rom_tl_o.d_opcode[0]	Yes	Yes	*T13,*T14,*T15	Yes	T13,T14,T15	OUTPUT
rom_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
rom_tl_o.d_valid	Yes	Yes	T4,T5,T7	Yes	T4,T5,T7	OUTPUT
regs_tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_i.a_address[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
regs_tl_o.d_error	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
regs_tl_o.d_user.data_intg[6:0]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	OUTPUT
regs_tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
regs_tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_data[31:0]	Yes	Yes	T5,T7,T8	Yes	T1,T2,T3	OUTPUT
regs_tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_source[7:0]	Yes	Yes	T1,T5,T6	Yes	T1,T3,T5	OUTPUT
regs_tl_o.d_size[1:0]	Yes	Yes	T2,T3,T5	Yes	T1,T2,T3	OUTPUT
regs_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_opcode[0]	Yes	Yes	*T11,*T12,*T30	Yes	T5,T7,T8	OUTPUT
regs_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
pwrmgr_data_o.good[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
pwrmgr_data_o.done[3:0]	Yes	Yes	T1,T2,T3	Yes	T11,T32,T13	OUTPUT
keymgr_data_o.valid	Yes	Yes	T11,T32,T13	Yes	T1,T2,T3	OUTPUT
keymgr_data_o.data[255:0]	Yes	Yes	T31,T33,T34	Yes	T3,T5,T7	OUTPUT
kmac_data_i.error	No	Yes	T12,T30,T31	No		INPUT
kmac_data_i.digest_share1[383:0]	Yes	Yes	T35,T36,T37	Yes	T33,T34,T38	INPUT
kmac_data_i.digest_share0[383:0]	Yes	Yes	T30,T39,T40	Yes	T31,T32,T41	INPUT
kmac_data_i.done	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
kmac_data_i.ready	Yes	Yes	T1,T3,T5	Yes	T1,T2,T3	INPUT
kmac_data_o.last	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
kmac_data_o.strb[7:0]	No	No		No		OUTPUT
kmac_data_o.data[38:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
kmac_data_o.data[63:39]	No	No		No		OUTPUT
kmac_data_o.valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT

*Tests covering at least one bit in the range

---

Branch Coverage for Module : rom_ctrl

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
TERNARY	212	2	2	100.00

212          assign bus_rom_prince_index = (rom_tl_i.a_valid ?
                                                             -1-  
                                                             ==>  
                                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Module : rom_ctrl

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	34	34	100.00	27	79.41
Cover properties	0	0		0
Cover sequences	0	0		0
Total	34	34	100.00	27	79.41

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxOKnown_A	40353022	40179537	0	0
BusRomIndicesMatch_A	40339927	40172508	0	0
FpvSecCmRegWeOnehotCheck_A	40353022	100	0	0
FpvSecCmReqFifoRptrCheck_A	40353022	0	0	0
FpvSecCmReqFifoWptrCheck_A	40353022	0	0	0
FpvSecCmRspFifoRptrCheck_A	40353022	0	0	0
FpvSecCmRspFifoWptrCheck_A	40353022	0	0	0
FpvSecCmSramReqFifoRptrCheck_A	40353022	0	0	0
FpvSecCmSramReqFifoWptrCheck_A	40353022	0	0	0
KeymgrDataODataKnown_A	40353022	7133360	0	0
KeymgrDataODataKnown_AKnownEnable	40353022	40179537	0	0
KeymgrDataOValidKnown_A	40353022	40179537	0	0
KeymgrValidChk_A	40353022	7125724	0	0
KmacDataODataKnown_A	40353022	32925128	0	0
KmacDataODataKnown_AKnownEnable	40353022	40179537	0	0
KmacDataOValidKnown_A	40353022	40179537	0	0
PwrmgrDataChk_A	40353022	7125724	0	0
PwrmgrDataOKnown_A	40353022	40179537	0	0
RegsTlOAReadyKnown_A	40353022	40179537	0	0
RegsTlODDataKnown_A	40353022	1293968	0	0
RegsTlODDataKnown_AKnownEnable	40353022	40179537	0	0
RegsTlODValidKnown_A	40353022	40179537	0	0
RomTlOAReadyKnown_A	40353022	40179537	0	0
RomTlODDataKnown_A	40353022	1324164	0	0
RomTlODDataKnown_AKnownEnable	40353022	40179537	0	0
RomTlODValidKnown_A	40353022	40179537	0	0
StabilityChkKmac_A	40353022	32922555	0	0
StabilityChkkeymgr_A	40353022	7132264	0	0
TlAccessChk_A	40353022	33046177	0	0
gen_asserts_with_scrambling.FpvSecCmCheckerFsmAlert_A	40353022	100	0	0
gen_asserts_with_scrambling.FpvSecCmCompareAddrCtrCheck_A	40353022	0	0	0
gen_asserts_with_scrambling.FpvSecCmCompareFsmAlert_A	40353022	524	0	0
gen_fsm_scramble_enabled_asserts.BusLocalEscChk_A	40353022	58512	0	0
gen_fsm_scramble_enabled_asserts.InvalidStateTerminal_A	40353022	57291	0	0

AlertTxOKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40353022	40179537	0	0
T1	25079	24988	0	0
T2	16563	16474	0	0
T3	24954	24855	0	0
T4	17210	17116	0	0
T5	25493	25402	0	0
T6	24853	24788	0	0
T7	26084	26013	0	0
T8	26159	26075	0	0
T9	17781	17714	0	0
T10	28941	28753	0	0

BusRomIndicesMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40339927	40172508	0	0
T1	25079	24988	0	0
T2	16563	16474	0	0
T3	24954	24855	0	0
T4	17210	17116	0	0
T5	25493	25402	0	0
T6	24853	24788	0	0
T7	26084	26013	0	0
T8	26159	26075	0	0
T9	17781	17714	0	0
T10	28941	28753	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40353022	100	0	0
T27	27071	20	0	0
T28	35051	20	0	0
T29	0	20	0	0
T42	0	20	0	0
T43	0	20	0	0
T44	32993	0	0	0
T45	365761	0	0	0
T46	248715	0	0	0
T47	24780	0	0	0
T48	26337	0	0	0
T49	224308	0	0	0
T50	16607	0	0	0
T51	230051	0	0	0

FpvSecCmReqFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40353022	0	0	0

FpvSecCmReqFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40353022	0	0	0

FpvSecCmRspFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40353022	0	0	0

FpvSecCmRspFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40353022	0	0	0

FpvSecCmSramReqFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40353022	0	0	0

FpvSecCmSramReqFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40353022	0	0	0

KeymgrDataODataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40353022	7133360	0	0
T1	25079	284	0	0
T2	16563	77	0	0
T3	24954	134	0	0
T4	17210	657	0	0
T5	25493	760	0	0
T6	24853	103	0	0
T7	26084	1369	0	0
T8	26159	1463	0	0
T9	17781	1317	0	0
T10	28941	3985	0	0

KeymgrDataODataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	40353022	40179537	0	0
T1	25079	24988	0	0
T2	16563	16474	0	0
T3	24954	24855	0	0
T4	17210	17116	0	0
T5	25493	25402	0	0
T6	24853	24788	0	0
T7	26084	26013	0	0
T8	26159	26075	0	0
T9	17781	17714	0	0
T10	28941	28753	0	0

KeymgrDataOValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40353022	40179537	0	0
T1	25079	24988	0	0
T2	16563	16474	0	0
T3	24954	24855	0	0
T4	17210	17116	0	0
T5	25493	25402	0	0
T6	24853	24788	0	0
T7	26084	26013	0	0
T8	26159	26075	0	0
T9	17781	17714	0	0
T10	28941	28753	0	0

KeymgrValidChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40353022	7125724	0	0
T1	25079	283	0	0
T2	16563	76	0	0
T3	24954	133	0	0
T4	17210	656	0	0
T5	25493	759	0	0
T6	24853	102	0	0
T7	26084	1368	0	0
T8	26159	1462	0	0
T9	17781	1316	0	0
T10	28941	3984	0	0

KmacDataODataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40353022	32925128	0	0
T1	25079	24610	0	0
T2	16563	16376	0	0
T3	24954	24643	0	0
T4	17210	16376	0	0
T5	25493	24582	0	0
T6	24853	24614	0	0
T7	26084	24623	0	0
T8	26159	24563	0	0
T9	17781	16376	0	0
T10	28941	24662	0	0

KmacDataODataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	40353022	40179537	0	0
T1	25079	24988	0	0
T2	16563	16474	0	0
T3	24954	24855	0	0
T4	17210	17116	0	0
T5	25493	25402	0	0
T6	24853	24788	0	0
T7	26084	26013	0	0
T8	26159	26075	0	0
T9	17781	17714	0	0
T10	28941	28753	0	0

KmacDataOValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40353022	40179537	0	0
T1	25079	24988	0	0
T2	16563	16474	0	0
T3	24954	24855	0	0
T4	17210	17116	0	0
T5	25493	25402	0	0
T6	24853	24788	0	0
T7	26084	26013	0	0
T8	26159	26075	0	0
T9	17781	17714	0	0
T10	28941	28753	0	0

PwrmgrDataChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40353022	7125724	0	0
T1	25079	283	0	0
T2	16563	76	0	0
T3	24954	133	0	0
T4	17210	656	0	0
T5	25493	759	0	0
T6	24853	102	0	0
T7	26084	1368	0	0
T8	26159	1462	0	0
T9	17781	1316	0	0
T10	28941	3984	0	0

PwrmgrDataOKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40353022	40179537	0	0
T1	25079	24988	0	0
T2	16563	16474	0	0
T3	24954	24855	0	0
T4	17210	17116	0	0
T5	25493	25402	0	0
T6	24853	24788	0	0
T7	26084	26013	0	0
T8	26159	26075	0	0
T9	17781	17714	0	0
T10	28941	28753	0	0

RegsTlOAReadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40353022	40179537	0	0
T1	25079	24988	0	0
T2	16563	16474	0	0
T3	24954	24855	0	0
T4	17210	17116	0	0
T5	25493	25402	0	0
T6	24853	24788	0	0
T7	26084	26013	0	0
T8	26159	26075	0	0
T9	17781	17714	0	0
T10	28941	28753	0	0

RegsTlODDataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40353022	1293968	0	0
T1	25079	6	0	0
T2	16563	32	0	0
T3	24954	19	0	0
T4	17210	0	0	0
T5	25493	16	0	0
T6	24853	27	0	0
T7	26084	74	0	0
T8	26159	48	0	0
T9	17781	0	0	0
T10	28941	48	0	0
T22	0	66	0	0
T23	0	16	0	0

RegsTlODDataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	40353022	40179537	0	0
T1	25079	24988	0	0
T2	16563	16474	0	0
T3	24954	24855	0	0
T4	17210	17116	0	0
T5	25493	25402	0	0
T6	24853	24788	0	0
T7	26084	26013	0	0
T8	26159	26075	0	0
T9	17781	17714	0	0
T10	28941	28753	0	0

RegsTlODValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40353022	40179537	0	0
T1	25079	24988	0	0
T2	16563	16474	0	0
T3	24954	24855	0	0
T4	17210	17116	0	0
T5	25493	25402	0	0
T6	24853	24788	0	0
T7	26084	26013	0	0
T8	26159	26075	0	0
T9	17781	17714	0	0
T10	28941	28753	0	0

RomTlOAReadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40353022	40179537	0	0
T1	25079	24988	0	0
T2	16563	16474	0	0
T3	24954	24855	0	0
T4	17210	17116	0	0
T5	25493	25402	0	0
T6	24853	24788	0	0
T7	26084	26013	0	0
T8	26159	26075	0	0
T9	17781	17714	0	0
T10	28941	28753	0	0

RomTlODDataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40353022	1324164	0	0
T4	17210	83	0	0
T5	25493	25	0	0
T6	24853	0	0	0
T7	26084	61	0	0
T8	26159	22	0	0
T9	17781	359	0	0
T10	28941	107	0	0
T16	17489	137	0	0
T17	0	247	0	0
T22	25816	33	0	0
T23	99362	48	0	0

RomTlODDataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	40353022	40179537	0	0
T1	25079	24988	0	0
T2	16563	16474	0	0
T3	24954	24855	0	0
T4	17210	17116	0	0
T5	25493	25402	0	0
T6	24853	24788	0	0
T7	26084	26013	0	0
T8	26159	26075	0	0
T9	17781	17714	0	0
T10	28941	28753	0	0

RomTlODValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40353022	40179537	0	0
T1	25079	24988	0	0
T2	16563	16474	0	0
T3	24954	24855	0	0
T4	17210	17116	0	0
T5	25493	25402	0	0
T6	24853	24788	0	0
T7	26084	26013	0	0
T8	26159	26075	0	0
T9	17781	17714	0	0
T10	28941	28753	0	0

StabilityChkKmac_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40353022	32922555	0	0
T1	25079	24609	0	0
T2	16563	16375	0	0
T3	24954	24642	0	0
T4	17210	16375	0	0
T5	25493	24581	0	0
T6	24853	24613	0	0
T7	26084	24622	0	0
T8	26159	24562	0	0
T9	17781	16375	0	0
T10	28941	24660	0	0

StabilityChkkeymgr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40353022	7132264	0	0
T1	25079	283	0	0
T2	16563	76	0	0
T3	24954	133	0	0
T4	17210	656	0	0
T5	25493	759	0	0
T6	24853	102	0	0
T7	26084	1368	0	0
T8	26159	1462	0	0
T9	17781	1316	0	0
T10	28941	3984	0	0

TlAccessChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40353022	33046177	0	0
T1	25079	24704	0	0
T2	16563	16397	0	0
T3	24954	24721	0	0
T4	17210	16459	0	0
T5	25493	24642	0	0
T6	24853	24685	0	0
T7	26084	24644	0	0
T8	26159	24612	0	0
T9	17781	16397	0	0
T10	28941	24768	0	0

gen_asserts_with_scrambling.FpvSecCmCheckerFsmAlert_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40353022	100	0	0
T27	27071	20	0	0
T28	35051	20	0	0
T29	0	20	0	0
T42	0	20	0	0
T43	0	20	0	0
T44	32993	0	0	0
T45	365761	0	0	0
T46	248715	0	0	0
T47	24780	0	0	0
T48	26337	0	0	0
T49	224308	0	0	0
T50	16607	0	0	0
T51	230051	0	0	0

gen_asserts_with_scrambling.FpvSecCmCompareAddrCtrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40353022	0	0	0

gen_asserts_with_scrambling.FpvSecCmCompareFsmAlert_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40353022	524	0	0
T27	0	20	0	0
T28	0	20	0	0
T29	0	20	0	0
T42	0	20	0	0
T43	0	20	0	0
T46	0	5	0	0
T52	260608	5	0	0
T53	0	5	0	0
T54	0	10	0	0
T55	0	10	0	0
T56	33090	0	0	0
T57	26096	0	0	0
T58	311924	0	0	0
T59	180457	0	0	0
T60	17779	0	0	0
T61	16792	0	0	0
T62	53605	0	0	0
T63	16539	0	0	0
T64	255502	0	0	0

gen_fsm_scramble_enabled_asserts.BusLocalEscChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40353022	58512	0	0
T12	49514	35	0	0
T20	25838	0	0	0
T21	25695	0	0	0
T30	49739	58	0	0
T31	49716	36	0	0
T32	50380	0	0	0
T33	0	34	0	0
T34	0	31	0	0
T36	0	51	0	0
T38	0	46	0	0
T39	0	32	0	0
T41	0	68	0	0
T65	0	37	0	0
T66	100328	0	0	0
T67	16754	0	0	0
T68	25989	0	0	0
T69	24723	0	0	0

gen_fsm_scramble_enabled_asserts.InvalidStateTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40353022	57291	0	0
T12	49514	34	0	0
T20	25838	0	0	0
T21	25695	0	0	0
T30	49739	57	0	0
T31	49716	35	0	0
T32	50380	0	0	0
T33	0	33	0	0
T34	0	30	0	0
T36	0	50	0	0
T38	0	45	0	0
T39	0	31	0	0
T41	0	67	0	0
T65	0	36	0	0
T66	100328	0	0	0
T67	16754	0	0	0
T68	25989	0	0	0
T69	24723	0	0	0