Unified Coverage Report :: Module :: rom_ctrl_regs_reg_top

Module : rom_ctrl_regs_reg_top

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/default/sim-vcs/../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl_regs_reg_top.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg_regs	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg_regs

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.72	99.41	99.21	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.99	100.00	98.28	97.26		100.00	79.41	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_alert_test	100.00	100.00
u_chk	100.00	100.00		100.00			100.00
u_digest_0	100.00	100.00	100.00			100.00
u_digest_1	100.00	100.00	100.00			100.00
u_digest_2	100.00	100.00	100.00			100.00
u_digest_3	100.00	100.00	100.00			100.00
u_digest_4	100.00	100.00	100.00			100.00
u_digest_5	100.00	100.00	100.00			100.00
u_digest_6	100.00	100.00	100.00			100.00
u_digest_7	100.00	100.00	100.00			100.00
u_exp_digest_0	100.00	100.00	100.00			100.00
u_exp_digest_1	100.00	100.00	100.00			100.00
u_exp_digest_2	100.00	100.00	100.00			100.00
u_exp_digest_3	100.00	100.00	100.00			100.00
u_exp_digest_4	100.00	100.00	100.00			100.00
u_exp_digest_5	100.00	100.00	100.00			100.00
u_exp_digest_6	100.00	100.00	100.00			100.00
u_exp_digest_7	100.00	100.00	100.00			100.00
u_fatal_alert_cause_checker_error	100.00	100.00	100.00			100.00
u_fatal_alert_cause_integrity_error	100.00	100.00	100.00			100.00
u_prim_reg_we_check	100.00	100.00		100.00
u_reg_if	98.67	97.14	97.53			100.00	100.00
u_rsp_intg_gen	100.00	100.00					100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rom_ctrl_regs_reg_top

	Line No.	Total	Covered	Percent
TOTAL		76	76	100.00
ALWAYS	68	4	4	100.00
CONT_ASSIGN	77	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	119	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
ALWAYS	689	19	19	100.00
CONT_ASSIGN	710	1	1	100.00
ALWAYS	714	1	1	100.00
CONT_ASSIGN	736	1	1	100.00
CONT_ASSIGN	738	1	1	100.00
ALWAYS	742	19	19	100.00
ALWAYS	765	21	21	100.00
CONT_ASSIGN	851	0	0
CONT_ASSIGN	859	1	1	100.00
CONT_ASSIGN	860	1	1	100.00

67                        always_ff @(posedge clk_i or negedge rst_ni) begin
68         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
69         1/1                err_q <= '0;
           Tests:       T1 T2 T3 
70         1/1              end else if (intg_err || reg_we_err) begin
           Tests:       T1 T2 T3 
71         1/1                err_q <= 1'b1;
           Tests:       T27 T28 T29 
72                          end
                        MISSING_ELSE
73                        end
74                      
75                        // integrity error output is permanent and should be used for alert generation
76                        // register errors are transactional
77         1/1            assign intg_err_o = err_q | intg_err | reg_we_err;
           Tests:       T1 T2 T3 
78                      
79                        // outgoing integrity generation
80                        tlul_pkg::tl_d2h_t tl_o_pre;
81                        tlul_rsp_intg_gen #(
82                          .EnableRspIntgGen(1),
83                          .EnableDataIntgGen(1)
84                        ) u_rsp_intg_gen (
85                          .tl_i(tl_o_pre),
86                          .tl_o(tl_o)
87                        );
88                      
89         1/1            assign tl_reg_h2d = tl_i;
           Tests:       T1 T2 T3 
90         1/1            assign tl_o_pre   = tl_reg_d2h;
           Tests:       T1 T2 T3 
91                      
92                        tlul_adapter_reg #(
93                          .RegAw(AW),
94                          .RegDw(DW),
95                          .EnableDataIntgGen(0)
96                        ) u_reg_if (
97                          .clk_i  (clk_i),
98                          .rst_ni (rst_ni),
99                      
100                         .tl_i (tl_reg_h2d),
101                         .tl_o (tl_reg_d2h),
102                     
103                         .en_ifetch_i(prim_mubi_pkg::MuBi4False),
104                         .intg_error_o(),
105                     
106                         .we_o    (reg_we),
107                         .re_o    (reg_re),
108                         .addr_o  (reg_addr),
109                         .wdata_o (reg_wdata),
110                         .be_o    (reg_be),
111                         .busy_i  (reg_busy),
112                         .rdata_i (reg_rdata),
113                         .error_i (reg_error)
114                       );
115                     
116                       // cdc oversampling signals
117                     
118        1/1            assign reg_rdata = reg_rdata_next ;
           Tests:       T1 T2 T3 
119        1/1            assign reg_error = addrmiss | wr_err | intg_err;
           Tests:       T13 T14 T15 
120                     
121                       // Define SW related signals
122                       // Format: <reg>_<field>_{wd|we|qs}
123                       //        or <reg>_{wd|we|qs} if field == 1 or 0
124                       logic alert_test_we;
125                       logic alert_test_wd;
126                       logic fatal_alert_cause_checker_error_qs;
127                       logic fatal_alert_cause_integrity_error_qs;
128                       logic [31:0] digest_0_qs;
129                       logic [31:0] digest_1_qs;
130                       logic [31:0] digest_2_qs;
131                       logic [31:0] digest_3_qs;
132                       logic [31:0] digest_4_qs;
133                       logic [31:0] digest_5_qs;
134                       logic [31:0] digest_6_qs;
135                       logic [31:0] digest_7_qs;
136                       logic [31:0] exp_digest_0_qs;
137                       logic [31:0] exp_digest_1_qs;
138                       logic [31:0] exp_digest_2_qs;
139                       logic [31:0] exp_digest_3_qs;
140                       logic [31:0] exp_digest_4_qs;
141                       logic [31:0] exp_digest_5_qs;
142                       logic [31:0] exp_digest_6_qs;
143                       logic [31:0] exp_digest_7_qs;
144                     
145                       // Register instances
146                       // R[alert_test]: V(True)
147                       logic alert_test_qe;
148                       logic [0:0] alert_test_flds_we;
149        1/1            assign alert_test_qe = &alert_test_flds_we;
           Tests:       T1 T2 T3 
150                       prim_subreg_ext #(
151                         .DW    (1)
152                       ) u_alert_test (
153                         .re     (1'b0),
154                         .we     (alert_test_we),
155                         .wd     (alert_test_wd),
156                         .d      ('0),
157                         .qre    (),
158                         .qe     (alert_test_flds_we[0]),
159                         .q      (reg2hw.alert_test.q),
160                         .ds     (),
161                         .qs     ()
162                       );
163        1/1            assign reg2hw.alert_test.qe = alert_test_qe;
           Tests:       T1 T2 T3 
164                     
165                     
166                       // R[fatal_alert_cause]: V(False)
167                       //   F[checker_error]: 0:0
168                       prim_subreg #(
169                         .DW      (1),
170                         .SwAccess(prim_subreg_pkg::SwAccessRO),
171                         .RESVAL  (1'h0),
172                         .Mubi    (1'b0)
173                       ) u_fatal_alert_cause_checker_error (
174                         .clk_i   (clk_i),
175                         .rst_ni  (rst_ni),
176                     
177                         // from register interface
178                         .we     (1'b0),
179                         .wd     ('0),
180                     
181                         // from internal hardware
182                         .de     (hw2reg.fatal_alert_cause.checker_error.de),
183                         .d      (hw2reg.fatal_alert_cause.checker_error.d),
184                     
185                         // to internal hardware
186                         .qe     (),
187                         .q      (),
188                         .ds     (),
189                     
190                         // to register interface (read)
191                         .qs     (fatal_alert_cause_checker_error_qs)
192                       );
193                     
194                       //   F[integrity_error]: 1:1
195                       prim_subreg #(
196                         .DW      (1),
197                         .SwAccess(prim_subreg_pkg::SwAccessRO),
198                         .RESVAL  (1'h0),
199                         .Mubi    (1'b0)
200                       ) u_fatal_alert_cause_integrity_error (
201                         .clk_i   (clk_i),
202                         .rst_ni  (rst_ni),
203                     
204                         // from register interface
205                         .we     (1'b0),
206                         .wd     ('0),
207                     
208                         // from internal hardware
209                         .de     (hw2reg.fatal_alert_cause.integrity_error.de),
210                         .d      (hw2reg.fatal_alert_cause.integrity_error.d),
211                     
212                         // to internal hardware
213                         .qe     (),
214                         .q      (),
215                         .ds     (),
216                     
217                         // to register interface (read)
218                         .qs     (fatal_alert_cause_integrity_error_qs)
219                       );
220                     
221                     
222                       // Subregister 0 of Multireg digest
223                       // R[digest_0]: V(False)
224                       prim_subreg #(
225                         .DW      (32),
226                         .SwAccess(prim_subreg_pkg::SwAccessRO),
227                         .RESVAL  (32'h0),
228                         .Mubi    (1'b0)
229                       ) u_digest_0 (
230                         .clk_i   (clk_i),
231                         .rst_ni  (rst_ni),
232                     
233                         // from register interface
234                         .we     (1'b0),
235                         .wd     ('0),
236                     
237                         // from internal hardware
238                         .de     (hw2reg.digest[0].de),
239                         .d      (hw2reg.digest[0].d),
240                     
241                         // to internal hardware
242                         .qe     (),
243                         .q      (reg2hw.digest[0].q),
244                         .ds     (),
245                     
246                         // to register interface (read)
247                         .qs     (digest_0_qs)
248                       );
249                     
250                     
251                       // Subregister 1 of Multireg digest
252                       // R[digest_1]: V(False)
253                       prim_subreg #(
254                         .DW      (32),
255                         .SwAccess(prim_subreg_pkg::SwAccessRO),
256                         .RESVAL  (32'h0),
257                         .Mubi    (1'b0)
258                       ) u_digest_1 (
259                         .clk_i   (clk_i),
260                         .rst_ni  (rst_ni),
261                     
262                         // from register interface
263                         .we     (1'b0),
264                         .wd     ('0),
265                     
266                         // from internal hardware
267                         .de     (hw2reg.digest[1].de),
268                         .d      (hw2reg.digest[1].d),
269                     
270                         // to internal hardware
271                         .qe     (),
272                         .q      (reg2hw.digest[1].q),
273                         .ds     (),
274                     
275                         // to register interface (read)
276                         .qs     (digest_1_qs)
277                       );
278                     
279                     
280                       // Subregister 2 of Multireg digest
281                       // R[digest_2]: V(False)
282                       prim_subreg #(
283                         .DW      (32),
284                         .SwAccess(prim_subreg_pkg::SwAccessRO),
285                         .RESVAL  (32'h0),
286                         .Mubi    (1'b0)
287                       ) u_digest_2 (
288                         .clk_i   (clk_i),
289                         .rst_ni  (rst_ni),
290                     
291                         // from register interface
292                         .we     (1'b0),
293                         .wd     ('0),
294                     
295                         // from internal hardware
296                         .de     (hw2reg.digest[2].de),
297                         .d      (hw2reg.digest[2].d),
298                     
299                         // to internal hardware
300                         .qe     (),
301                         .q      (reg2hw.digest[2].q),
302                         .ds     (),
303                     
304                         // to register interface (read)
305                         .qs     (digest_2_qs)
306                       );
307                     
308                     
309                       // Subregister 3 of Multireg digest
310                       // R[digest_3]: V(False)
311                       prim_subreg #(
312                         .DW      (32),
313                         .SwAccess(prim_subreg_pkg::SwAccessRO),
314                         .RESVAL  (32'h0),
315                         .Mubi    (1'b0)
316                       ) u_digest_3 (
317                         .clk_i   (clk_i),
318                         .rst_ni  (rst_ni),
319                     
320                         // from register interface
321                         .we     (1'b0),
322                         .wd     ('0),
323                     
324                         // from internal hardware
325                         .de     (hw2reg.digest[3].de),
326                         .d      (hw2reg.digest[3].d),
327                     
328                         // to internal hardware
329                         .qe     (),
330                         .q      (reg2hw.digest[3].q),
331                         .ds     (),
332                     
333                         // to register interface (read)
334                         .qs     (digest_3_qs)
335                       );
336                     
337                     
338                       // Subregister 4 of Multireg digest
339                       // R[digest_4]: V(False)
340                       prim_subreg #(
341                         .DW      (32),
342                         .SwAccess(prim_subreg_pkg::SwAccessRO),
343                         .RESVAL  (32'h0),
344                         .Mubi    (1'b0)
345                       ) u_digest_4 (
346                         .clk_i   (clk_i),
347                         .rst_ni  (rst_ni),
348                     
349                         // from register interface
350                         .we     (1'b0),
351                         .wd     ('0),
352                     
353                         // from internal hardware
354                         .de     (hw2reg.digest[4].de),
355                         .d      (hw2reg.digest[4].d),
356                     
357                         // to internal hardware
358                         .qe     (),
359                         .q      (reg2hw.digest[4].q),
360                         .ds     (),
361                     
362                         // to register interface (read)
363                         .qs     (digest_4_qs)
364                       );
365                     
366                     
367                       // Subregister 5 of Multireg digest
368                       // R[digest_5]: V(False)
369                       prim_subreg #(
370                         .DW      (32),
371                         .SwAccess(prim_subreg_pkg::SwAccessRO),
372                         .RESVAL  (32'h0),
373                         .Mubi    (1'b0)
374                       ) u_digest_5 (
375                         .clk_i   (clk_i),
376                         .rst_ni  (rst_ni),
377                     
378                         // from register interface
379                         .we     (1'b0),
380                         .wd     ('0),
381                     
382                         // from internal hardware
383                         .de     (hw2reg.digest[5].de),
384                         .d      (hw2reg.digest[5].d),
385                     
386                         // to internal hardware
387                         .qe     (),
388                         .q      (reg2hw.digest[5].q),
389                         .ds     (),
390                     
391                         // to register interface (read)
392                         .qs     (digest_5_qs)
393                       );
394                     
395                     
396                       // Subregister 6 of Multireg digest
397                       // R[digest_6]: V(False)
398                       prim_subreg #(
399                         .DW      (32),
400                         .SwAccess(prim_subreg_pkg::SwAccessRO),
401                         .RESVAL  (32'h0),
402                         .Mubi    (1'b0)
403                       ) u_digest_6 (
404                         .clk_i   (clk_i),
405                         .rst_ni  (rst_ni),
406                     
407                         // from register interface
408                         .we     (1'b0),
409                         .wd     ('0),
410                     
411                         // from internal hardware
412                         .de     (hw2reg.digest[6].de),
413                         .d      (hw2reg.digest[6].d),
414                     
415                         // to internal hardware
416                         .qe     (),
417                         .q      (reg2hw.digest[6].q),
418                         .ds     (),
419                     
420                         // to register interface (read)
421                         .qs     (digest_6_qs)
422                       );
423                     
424                     
425                       // Subregister 7 of Multireg digest
426                       // R[digest_7]: V(False)
427                       prim_subreg #(
428                         .DW      (32),
429                         .SwAccess(prim_subreg_pkg::SwAccessRO),
430                         .RESVAL  (32'h0),
431                         .Mubi    (1'b0)
432                       ) u_digest_7 (
433                         .clk_i   (clk_i),
434                         .rst_ni  (rst_ni),
435                     
436                         // from register interface
437                         .we     (1'b0),
438                         .wd     ('0),
439                     
440                         // from internal hardware
441                         .de     (hw2reg.digest[7].de),
442                         .d      (hw2reg.digest[7].d),
443                     
444                         // to internal hardware
445                         .qe     (),
446                         .q      (reg2hw.digest[7].q),
447                         .ds     (),
448                     
449                         // to register interface (read)
450                         .qs     (digest_7_qs)
451                       );
452                     
453                     
454                       // Subregister 0 of Multireg exp_digest
455                       // R[exp_digest_0]: V(False)
456                       prim_subreg #(
457                         .DW      (32),
458                         .SwAccess(prim_subreg_pkg::SwAccessRO),
459                         .RESVAL  (32'h0),
460                         .Mubi    (1'b0)
461                       ) u_exp_digest_0 (
462                         .clk_i   (clk_i),
463                         .rst_ni  (rst_ni),
464                     
465                         // from register interface
466                         .we     (1'b0),
467                         .wd     ('0),
468                     
469                         // from internal hardware
470                         .de     (hw2reg.exp_digest[0].de),
471                         .d      (hw2reg.exp_digest[0].d),
472                     
473                         // to internal hardware
474                         .qe     (),
475                         .q      (reg2hw.exp_digest[0].q),
476                         .ds     (),
477                     
478                         // to register interface (read)
479                         .qs     (exp_digest_0_qs)
480                       );
481                     
482                     
483                       // Subregister 1 of Multireg exp_digest
484                       // R[exp_digest_1]: V(False)
485                       prim_subreg #(
486                         .DW      (32),
487                         .SwAccess(prim_subreg_pkg::SwAccessRO),
488                         .RESVAL  (32'h0),
489                         .Mubi    (1'b0)
490                       ) u_exp_digest_1 (
491                         .clk_i   (clk_i),
492                         .rst_ni  (rst_ni),
493                     
494                         // from register interface
495                         .we     (1'b0),
496                         .wd     ('0),
497                     
498                         // from internal hardware
499                         .de     (hw2reg.exp_digest[1].de),
500                         .d      (hw2reg.exp_digest[1].d),
501                     
502                         // to internal hardware
503                         .qe     (),
504                         .q      (reg2hw.exp_digest[1].q),
505                         .ds     (),
506                     
507                         // to register interface (read)
508                         .qs     (exp_digest_1_qs)
509                       );
510                     
511                     
512                       // Subregister 2 of Multireg exp_digest
513                       // R[exp_digest_2]: V(False)
514                       prim_subreg #(
515                         .DW      (32),
516                         .SwAccess(prim_subreg_pkg::SwAccessRO),
517                         .RESVAL  (32'h0),
518                         .Mubi    (1'b0)
519                       ) u_exp_digest_2 (
520                         .clk_i   (clk_i),
521                         .rst_ni  (rst_ni),
522                     
523                         // from register interface
524                         .we     (1'b0),
525                         .wd     ('0),
526                     
527                         // from internal hardware
528                         .de     (hw2reg.exp_digest[2].de),
529                         .d      (hw2reg.exp_digest[2].d),
530                     
531                         // to internal hardware
532                         .qe     (),
533                         .q      (reg2hw.exp_digest[2].q),
534                         .ds     (),
535                     
536                         // to register interface (read)
537                         .qs     (exp_digest_2_qs)
538                       );
539                     
540                     
541                       // Subregister 3 of Multireg exp_digest
542                       // R[exp_digest_3]: V(False)
543                       prim_subreg #(
544                         .DW      (32),
545                         .SwAccess(prim_subreg_pkg::SwAccessRO),
546                         .RESVAL  (32'h0),
547                         .Mubi    (1'b0)
548                       ) u_exp_digest_3 (
549                         .clk_i   (clk_i),
550                         .rst_ni  (rst_ni),
551                     
552                         // from register interface
553                         .we     (1'b0),
554                         .wd     ('0),
555                     
556                         // from internal hardware
557                         .de     (hw2reg.exp_digest[3].de),
558                         .d      (hw2reg.exp_digest[3].d),
559                     
560                         // to internal hardware
561                         .qe     (),
562                         .q      (reg2hw.exp_digest[3].q),
563                         .ds     (),
564                     
565                         // to register interface (read)
566                         .qs     (exp_digest_3_qs)
567                       );
568                     
569                     
570                       // Subregister 4 of Multireg exp_digest
571                       // R[exp_digest_4]: V(False)
572                       prim_subreg #(
573                         .DW      (32),
574                         .SwAccess(prim_subreg_pkg::SwAccessRO),
575                         .RESVAL  (32'h0),
576                         .Mubi    (1'b0)
577                       ) u_exp_digest_4 (
578                         .clk_i   (clk_i),
579                         .rst_ni  (rst_ni),
580                     
581                         // from register interface
582                         .we     (1'b0),
583                         .wd     ('0),
584                     
585                         // from internal hardware
586                         .de     (hw2reg.exp_digest[4].de),
587                         .d      (hw2reg.exp_digest[4].d),
588                     
589                         // to internal hardware
590                         .qe     (),
591                         .q      (reg2hw.exp_digest[4].q),
592                         .ds     (),
593                     
594                         // to register interface (read)
595                         .qs     (exp_digest_4_qs)
596                       );
597                     
598                     
599                       // Subregister 5 of Multireg exp_digest
600                       // R[exp_digest_5]: V(False)
601                       prim_subreg #(
602                         .DW      (32),
603                         .SwAccess(prim_subreg_pkg::SwAccessRO),
604                         .RESVAL  (32'h0),
605                         .Mubi    (1'b0)
606                       ) u_exp_digest_5 (
607                         .clk_i   (clk_i),
608                         .rst_ni  (rst_ni),
609                     
610                         // from register interface
611                         .we     (1'b0),
612                         .wd     ('0),
613                     
614                         // from internal hardware
615                         .de     (hw2reg.exp_digest[5].de),
616                         .d      (hw2reg.exp_digest[5].d),
617                     
618                         // to internal hardware
619                         .qe     (),
620                         .q      (reg2hw.exp_digest[5].q),
621                         .ds     (),
622                     
623                         // to register interface (read)
624                         .qs     (exp_digest_5_qs)
625                       );
626                     
627                     
628                       // Subregister 6 of Multireg exp_digest
629                       // R[exp_digest_6]: V(False)
630                       prim_subreg #(
631                         .DW      (32),
632                         .SwAccess(prim_subreg_pkg::SwAccessRO),
633                         .RESVAL  (32'h0),
634                         .Mubi    (1'b0)
635                       ) u_exp_digest_6 (
636                         .clk_i   (clk_i),
637                         .rst_ni  (rst_ni),
638                     
639                         // from register interface
640                         .we     (1'b0),
641                         .wd     ('0),
642                     
643                         // from internal hardware
644                         .de     (hw2reg.exp_digest[6].de),
645                         .d      (hw2reg.exp_digest[6].d),
646                     
647                         // to internal hardware
648                         .qe     (),
649                         .q      (reg2hw.exp_digest[6].q),
650                         .ds     (),
651                     
652                         // to register interface (read)
653                         .qs     (exp_digest_6_qs)
654                       );
655                     
656                     
657                       // Subregister 7 of Multireg exp_digest
658                       // R[exp_digest_7]: V(False)
659                       prim_subreg #(
660                         .DW      (32),
661                         .SwAccess(prim_subreg_pkg::SwAccessRO),
662                         .RESVAL  (32'h0),
663                         .Mubi    (1'b0)
664                       ) u_exp_digest_7 (
665                         .clk_i   (clk_i),
666                         .rst_ni  (rst_ni),
667                     
668                         // from register interface
669                         .we     (1'b0),
670                         .wd     ('0),
671                     
672                         // from internal hardware
673                         .de     (hw2reg.exp_digest[7].de),
674                         .d      (hw2reg.exp_digest[7].d),
675                     
676                         // to internal hardware
677                         .qe     (),
678                         .q      (reg2hw.exp_digest[7].q),
679                         .ds     (),
680                     
681                         // to register interface (read)
682                         .qs     (exp_digest_7_qs)
683                       );
684                     
685                     
686                     
687                       logic [17:0] addr_hit;
688                       always_comb begin
689        1/1              addr_hit = '0;
           Tests:       T1 T2 T3 
690        1/1              addr_hit[ 0] = (reg_addr == ROM_CTRL_ALERT_TEST_OFFSET);
           Tests:       T1 T2 T3 
691        1/1              addr_hit[ 1] = (reg_addr == ROM_CTRL_FATAL_ALERT_CAUSE_OFFSET);
           Tests:       T1 T2 T3 
692        1/1              addr_hit[ 2] = (reg_addr == ROM_CTRL_DIGEST_0_OFFSET);
           Tests:       T1 T2 T3 
693        1/1              addr_hit[ 3] = (reg_addr == ROM_CTRL_DIGEST_1_OFFSET);
           Tests:       T1 T2 T3 
694        1/1              addr_hit[ 4] = (reg_addr == ROM_CTRL_DIGEST_2_OFFSET);
           Tests:       T1 T2 T3 
695        1/1              addr_hit[ 5] = (reg_addr == ROM_CTRL_DIGEST_3_OFFSET);
           Tests:       T1 T2 T3 
696        1/1              addr_hit[ 6] = (reg_addr == ROM_CTRL_DIGEST_4_OFFSET);
           Tests:       T1 T2 T3 
697        1/1              addr_hit[ 7] = (reg_addr == ROM_CTRL_DIGEST_5_OFFSET);
           Tests:       T1 T2 T3 
698        1/1              addr_hit[ 8] = (reg_addr == ROM_CTRL_DIGEST_6_OFFSET);
           Tests:       T1 T2 T3 
699        1/1              addr_hit[ 9] = (reg_addr == ROM_CTRL_DIGEST_7_OFFSET);
           Tests:       T1 T2 T3 
700        1/1              addr_hit[10] = (reg_addr == ROM_CTRL_EXP_DIGEST_0_OFFSET);
           Tests:       T1 T2 T3 
701        1/1              addr_hit[11] = (reg_addr == ROM_CTRL_EXP_DIGEST_1_OFFSET);
           Tests:       T1 T2 T3 
702        1/1              addr_hit[12] = (reg_addr == ROM_CTRL_EXP_DIGEST_2_OFFSET);
           Tests:       T1 T2 T3 
703        1/1              addr_hit[13] = (reg_addr == ROM_CTRL_EXP_DIGEST_3_OFFSET);
           Tests:       T1 T2 T3 
704        1/1              addr_hit[14] = (reg_addr == ROM_CTRL_EXP_DIGEST_4_OFFSET);
           Tests:       T1 T2 T3 
705        1/1              addr_hit[15] = (reg_addr == ROM_CTRL_EXP_DIGEST_5_OFFSET);
           Tests:       T1 T2 T3 
706        1/1              addr_hit[16] = (reg_addr == ROM_CTRL_EXP_DIGEST_6_OFFSET);
           Tests:       T1 T2 T3 
707        1/1              addr_hit[17] = (reg_addr == ROM_CTRL_EXP_DIGEST_7_OFFSET);
           Tests:       T1 T2 T3 
708                       end
709                     
710        1/1            assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
           Tests:       T1 T2 T3 
711                     
712                       // Check sub-word write is permitted
713                       always_comb begin
714        1/1              wr_err = (reg_we &
           Tests:       T1 T2 T3 
715                                   ((addr_hit[ 0] & (|(ROM_CTRL_REGS_PERMIT[ 0] & ~reg_be))) |
716                                    (addr_hit[ 1] & (|(ROM_CTRL_REGS_PERMIT[ 1] & ~reg_be))) |
717                                    (addr_hit[ 2] & (|(ROM_CTRL_REGS_PERMIT[ 2] & ~reg_be))) |
718                                    (addr_hit[ 3] & (|(ROM_CTRL_REGS_PERMIT[ 3] & ~reg_be))) |
719                                    (addr_hit[ 4] & (|(ROM_CTRL_REGS_PERMIT[ 4] & ~reg_be))) |
720                                    (addr_hit[ 5] & (|(ROM_CTRL_REGS_PERMIT[ 5] & ~reg_be))) |
721                                    (addr_hit[ 6] & (|(ROM_CTRL_REGS_PERMIT[ 6] & ~reg_be))) |
722                                    (addr_hit[ 7] & (|(ROM_CTRL_REGS_PERMIT[ 7] & ~reg_be))) |
723                                    (addr_hit[ 8] & (|(ROM_CTRL_REGS_PERMIT[ 8] & ~reg_be))) |
724                                    (addr_hit[ 9] & (|(ROM_CTRL_REGS_PERMIT[ 9] & ~reg_be))) |
725                                    (addr_hit[10] & (|(ROM_CTRL_REGS_PERMIT[10] & ~reg_be))) |
726                                    (addr_hit[11] & (|(ROM_CTRL_REGS_PERMIT[11] & ~reg_be))) |
727                                    (addr_hit[12] & (|(ROM_CTRL_REGS_PERMIT[12] & ~reg_be))) |
728                                    (addr_hit[13] & (|(ROM_CTRL_REGS_PERMIT[13] & ~reg_be))) |
729                                    (addr_hit[14] & (|(ROM_CTRL_REGS_PERMIT[14] & ~reg_be))) |
730                                    (addr_hit[15] & (|(ROM_CTRL_REGS_PERMIT[15] & ~reg_be))) |
731                                    (addr_hit[16] & (|(ROM_CTRL_REGS_PERMIT[16] & ~reg_be))) |
732                                    (addr_hit[17] & (|(ROM_CTRL_REGS_PERMIT[17] & ~reg_be)))));
733                       end
734                     
735                       // Generate write-enables
736        1/1            assign alert_test_we = addr_hit[0] & reg_we & !reg_error;
           Tests:       T1 T2 T3 
737                     
738        1/1            assign alert_test_wd = reg_wdata[0];
           Tests:       T1 T2 T3 
739                     
740                       // Assign write-enables to checker logic vector.
741                       always_comb begin
742        1/1              reg_we_check = '0;
           Tests:       T1 T2 T3 
743        1/1              reg_we_check[0] = alert_test_we;
           Tests:       T1 T2 T3 
744        1/1              reg_we_check[1] = 1'b0;
           Tests:       T1 T2 T3 
745        1/1              reg_we_check[2] = 1'b0;
           Tests:       T1 T2 T3 
746        1/1              reg_we_check[3] = 1'b0;
           Tests:       T1 T2 T3 
747        1/1              reg_we_check[4] = 1'b0;
           Tests:       T1 T2 T3 
748        1/1              reg_we_check[5] = 1'b0;
           Tests:       T1 T2 T3 
749        1/1              reg_we_check[6] = 1'b0;
           Tests:       T1 T2 T3 
750        1/1              reg_we_check[7] = 1'b0;
           Tests:       T1 T2 T3 
751        1/1              reg_we_check[8] = 1'b0;
           Tests:       T1 T2 T3 
752        1/1              reg_we_check[9] = 1'b0;
           Tests:       T1 T2 T3 
753        1/1              reg_we_check[10] = 1'b0;
           Tests:       T1 T2 T3 
754        1/1              reg_we_check[11] = 1'b0;
           Tests:       T1 T2 T3 
755        1/1              reg_we_check[12] = 1'b0;
           Tests:       T1 T2 T3 
756        1/1              reg_we_check[13] = 1'b0;
           Tests:       T1 T2 T3 
757        1/1              reg_we_check[14] = 1'b0;
           Tests:       T1 T2 T3 
758        1/1              reg_we_check[15] = 1'b0;
           Tests:       T1 T2 T3 
759        1/1              reg_we_check[16] = 1'b0;
           Tests:       T1 T2 T3 
760        1/1              reg_we_check[17] = 1'b0;
           Tests:       T1 T2 T3 
761                       end
762                     
763                       // Read data return
764                       always_comb begin
765        1/1              reg_rdata_next = '0;
           Tests:       T1 T2 T3 
766        1/1              unique case (1'b1)
           Tests:       T1 T2 T3 
767                           addr_hit[0]: begin
768        1/1                  reg_rdata_next[0] = '0;
           Tests:       T1 T2 T3 
769                           end
770                     
771                           addr_hit[1]: begin
772        1/1                  reg_rdata_next[0] = fatal_alert_cause_checker_error_qs;
           Tests:       T2 T3 T4 
773        1/1                  reg_rdata_next[1] = fatal_alert_cause_integrity_error_qs;
           Tests:       T2 T3 T4 
774                           end
775                     
776                           addr_hit[2]: begin
777        1/1                  reg_rdata_next[31:0] = digest_0_qs;
           Tests:       T3 T4 T5 
778                           end
779                     
780                           addr_hit[3]: begin
781        1/1                  reg_rdata_next[31:0] = digest_1_qs;
           Tests:       T1 T3 T4 
782                           end
783                     
784                           addr_hit[4]: begin
785        1/1                  reg_rdata_next[31:0] = digest_2_qs;
           Tests:       T1 T2 T3 
786                           end
787                     
788                           addr_hit[5]: begin
789        1/1                  reg_rdata_next[31:0] = digest_3_qs;
           Tests:       T4 T5 T6 
790                           end
791                     
792                           addr_hit[6]: begin
793        1/1                  reg_rdata_next[31:0] = digest_4_qs;
           Tests:       T1 T4 T5 
794                           end
795                     
796                           addr_hit[7]: begin
797        1/1                  reg_rdata_next[31:0] = digest_5_qs;
           Tests:       T2 T3 T4 
798                           end
799                     
800                           addr_hit[8]: begin
801        1/1                  reg_rdata_next[31:0] = digest_6_qs;
           Tests:       T4 T5 T6 
802                           end
803                     
804                           addr_hit[9]: begin
805        1/1                  reg_rdata_next[31:0] = digest_7_qs;
           Tests:       T1 T3 T4 
806                           end
807                     
808                           addr_hit[10]: begin
809        1/1                  reg_rdata_next[31:0] = exp_digest_0_qs;
           Tests:       T3 T4 T5 
810                           end
811                     
812                           addr_hit[11]: begin
813        1/1                  reg_rdata_next[31:0] = exp_digest_1_qs;
           Tests:       T4 T5 T6 
814                           end
815                     
816                           addr_hit[12]: begin
817        1/1                  reg_rdata_next[31:0] = exp_digest_2_qs;
           Tests:       T2 T4 T5 
818                           end
819                     
820                           addr_hit[13]: begin
821        1/1                  reg_rdata_next[31:0] = exp_digest_3_qs;
           Tests:       T2 T4 T5 
822                           end
823                     
824                           addr_hit[14]: begin
825        1/1                  reg_rdata_next[31:0] = exp_digest_4_qs;
           Tests:       T4 T5 T6 
826                           end
827                     
828                           addr_hit[15]: begin
829        1/1                  reg_rdata_next[31:0] = exp_digest_5_qs;
           Tests:       T3 T4 T5 
830                           end
831                     
832                           addr_hit[16]: begin
833        1/1                  reg_rdata_next[31:0] = exp_digest_6_qs;
           Tests:       T3 T4 T5 
834                           end
835                     
836                           addr_hit[17]: begin
837        1/1                  reg_rdata_next[31:0] = exp_digest_7_qs;
           Tests:       T4 T5 T6 
838                           end
839                     
840                           default: begin
841                             reg_rdata_next = '1;
842                           end
843                         endcase
844                       end
845                     
846                       // shadow busy
847                       logic shadow_busy;
848                       assign shadow_busy = 1'b0;
849                     
850                       // register busy
851        unreachable    assign reg_busy = shadow_busy;
852                     
853                       // Unused signal tieoff
854                     
855                       // wdata / byte enable are not always fully used
856                       // add a blanket unused statement to handle lint waivers
857                       logic unused_wdata;
858                       logic unused_be;
859        1/1            assign unused_wdata = ^reg_wdata;
           Tests:       T1 T2 T3 
860        1/1            assign unused_be = ^reg_be;
           Tests:       T1 T2 T3 

---

Cond Coverage for Module : rom_ctrl_regs_reg_top

	Total	Covered	Percent
Conditions	135	135	100.00
Logical	135	135	100.00
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (reg_we && ((!addrmiss)))
             ---1--    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T13,T14,T15
1	1	Covered	T1,T2,T3

 LINE       70
 EXPRESSION (intg_err || reg_we_err)
             ----1---    -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T27,T28,T29
1	0	Covered	T87,T88,T89

 LINE       77
 EXPRESSION (err_q | intg_err | reg_we_err)
             --1--   ----2---   -----3----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T27,T28,T29
0	1	0	Covered	T87,T88,T89
1	0	0	Covered	T27,T28,T29

 LINE       119
 EXPRESSION (addrmiss | wr_err | intg_err)
             ----1---   ---2--   ----3---

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T87,T88,T89
0	1	0	Covered	T13,T14,T15
1	0	0	Covered	T13,T14,T15

 LINE       690
 EXPRESSION (reg_addr == rom_ctrl_reg_pkg::ROM_CTRL_ALERT_TEST_OFFSET)
            -----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       691
 EXPRESSION (reg_addr == rom_ctrl_reg_pkg::ROM_CTRL_FATAL_ALERT_CAUSE_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T10

 LINE       692
 EXPRESSION (reg_addr == rom_ctrl_reg_pkg::ROM_CTRL_DIGEST_0_OFFSET)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T5,T7

 LINE       693
 EXPRESSION (reg_addr == rom_ctrl_reg_pkg::ROM_CTRL_DIGEST_1_OFFSET)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T5

 LINE       694
 EXPRESSION (reg_addr == rom_ctrl_reg_pkg::ROM_CTRL_DIGEST_2_OFFSET)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       695
 EXPRESSION (reg_addr == rom_ctrl_reg_pkg::ROM_CTRL_DIGEST_3_OFFSET)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T7,T8

 LINE       696
 EXPRESSION (reg_addr == rom_ctrl_reg_pkg::ROM_CTRL_DIGEST_4_OFFSET)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T5,T7

 LINE       697
 EXPRESSION (reg_addr == rom_ctrl_reg_pkg::ROM_CTRL_DIGEST_5_OFFSET)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T5

 LINE       698
 EXPRESSION (reg_addr == rom_ctrl_reg_pkg::ROM_CTRL_DIGEST_6_OFFSET)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T7,T8

 LINE       699
 EXPRESSION (reg_addr == rom_ctrl_reg_pkg::ROM_CTRL_DIGEST_7_OFFSET)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T5

 LINE       700
 EXPRESSION (reg_addr == rom_ctrl_reg_pkg::ROM_CTRL_EXP_DIGEST_0_OFFSET)
            ------------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T5,T7

 LINE       701
 EXPRESSION (reg_addr == rom_ctrl_reg_pkg::ROM_CTRL_EXP_DIGEST_1_OFFSET)
            ------------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T7,T8

 LINE       702
 EXPRESSION (reg_addr == rom_ctrl_reg_pkg::ROM_CTRL_EXP_DIGEST_2_OFFSET)
            ------------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T7,T8

 LINE       703
 EXPRESSION (reg_addr == rom_ctrl_reg_pkg::ROM_CTRL_EXP_DIGEST_3_OFFSET)
            ------------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T5,T7

 LINE       704
 EXPRESSION (reg_addr == rom_ctrl_reg_pkg::ROM_CTRL_EXP_DIGEST_4_OFFSET)
            ------------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T7,T8

 LINE       705
 EXPRESSION (reg_addr == rom_ctrl_reg_pkg::ROM_CTRL_EXP_DIGEST_5_OFFSET)
            ------------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T5,T7

 LINE       706
 EXPRESSION (reg_addr == rom_ctrl_reg_pkg::ROM_CTRL_EXP_DIGEST_6_OFFSET)
            ------------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T5,T7

 LINE       707
 EXPRESSION (reg_addr == rom_ctrl_reg_pkg::ROM_CTRL_EXP_DIGEST_7_OFFSET)
            ------------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T7,T8

 LINE       710
 EXPRESSION ((reg_re || reg_we) ? ((~|addr_hit)) : 1'b0)
             ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       710
 SUB-EXPRESSION (reg_re || reg_we)
                 ---1--    ---2--

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T7,T8

 LINE       714
 EXPRESSION 
 Number  Term
      1  reg_we & 
      2  ((addr_hit[0] & ((|(4'b1 & (~reg_be))))) | (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | (addr_hit[2] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[3] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[4] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[5] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[6] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[7] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[8] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[9] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[10] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[11] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[12] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[13] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[14] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[15] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[16] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[17] & ((|(4'b1111 & (~reg_be)))))))

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T13,T14,T15

 LINE       714
 SUB-EXPRESSION 
 Number  Term
      1  (addr_hit[0] & ((|(4'b1 & (~reg_be))))) | 
      2  (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | 
      3  (addr_hit[2] & ((|(4'b1111 & (~reg_be))))) | 
      4  (addr_hit[3] & ((|(4'b1111 & (~reg_be))))) | 
      5  (addr_hit[4] & ((|(4'b1111 & (~reg_be))))) | 
      6  (addr_hit[5] & ((|(4'b1111 & (~reg_be))))) | 
      7  (addr_hit[6] & ((|(4'b1111 & (~reg_be))))) | 
      8  (addr_hit[7] & ((|(4'b1111 & (~reg_be))))) | 
      9  (addr_hit[8] & ((|(4'b1111 & (~reg_be))))) | 
     10  (addr_hit[9] & ((|(4'b1111 & (~reg_be))))) | 
     11  (addr_hit[10] & ((|(4'b1111 & (~reg_be))))) | 
     12  (addr_hit[11] & ((|(4'b1111 & (~reg_be))))) | 
     13  (addr_hit[12] & ((|(4'b1111 & (~reg_be))))) | 
     14  (addr_hit[13] & ((|(4'b1111 & (~reg_be))))) | 
     15  (addr_hit[14] & ((|(4'b1111 & (~reg_be))))) | 
     16  (addr_hit[15] & ((|(4'b1111 & (~reg_be))))) | 
     17  (addr_hit[16] & ((|(4'b1111 & (~reg_be))))) | 
     18  (addr_hit[17] & ((|(4'b1111 & (~reg_be))))))

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	-17-	-18-	Status	Tests
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	Covered	T1,T2,T3
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	Covered	T5,T8,T10
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0	Covered	T3,T7,T10
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0	0	Covered	T3,T10,T22
0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0	0	0	Covered	T5,T7,T8
0	0	0	0	0	0	0	0	0	0	0	0	0	1	0	0	0	0	Covered	T2,T7,T8
0	0	0	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	Covered	T2,T7,T8
0	0	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	Covered	T5,T10,T23
0	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	Covered	T3,T5,T8
0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	Covered	T1,T3,T8
0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	Covered	T5,T7,T8
0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	Covered	T2,T3,T5
0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	0	Covered	T1,T7,T8
0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	Covered	T5,T8,T10
0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	Covered	T1,T2,T3
0	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	Covered	T1,T3,T8
0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	Covered	T3,T8,T10
0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	Covered	T2,T30,T13
1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	Covered	T8,T13,T14

 LINE       714
 SUB-EXPRESSION (addr_hit[0] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T8,T13,T14

 LINE       714
 SUB-EXPRESSION (addr_hit[1] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T10,T12
1	1	Covered	T2,T30,T13

 LINE       714
 SUB-EXPRESSION (addr_hit[2] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T7,T8
1	1	Covered	T3,T8,T10

 LINE       714
 SUB-EXPRESSION (addr_hit[3] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T7,T10
1	1	Covered	T1,T3,T8

 LINE       714
 SUB-EXPRESSION (addr_hit[4] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T7,T8
1	1	Covered	T1,T2,T3

 LINE       714
 SUB-EXPRESSION (addr_hit[5] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T10,T23
1	1	Covered	T5,T8,T10

 LINE       714
 SUB-EXPRESSION (addr_hit[6] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T8,T10
1	1	Covered	T1,T7,T8

 LINE       714
 SUB-EXPRESSION (addr_hit[7] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T8,T10
1	1	Covered	T2,T3,T5

 LINE       714
 SUB-EXPRESSION (addr_hit[8] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T10,T22,T23
1	1	Covered	T5,T7,T8

 LINE       714
 SUB-EXPRESSION (addr_hit[9] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T7,T10
1	1	Covered	T1,T3,T8

 LINE       714
 SUB-EXPRESSION (addr_hit[10] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T10,T13
1	1	Covered	T3,T5,T8

 LINE       714
 SUB-EXPRESSION (addr_hit[11] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T8,T10
1	1	Covered	T5,T10,T23

 LINE       714
 SUB-EXPRESSION (addr_hit[12] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T10,T22
1	1	Covered	T2,T7,T8

 LINE       714
 SUB-EXPRESSION (addr_hit[13] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T10,T11
1	1	Covered	T2,T7,T8

 LINE       714
 SUB-EXPRESSION (addr_hit[14] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T23,T20,T32
1	1	Covered	T5,T7,T8

 LINE       714
 SUB-EXPRESSION (addr_hit[15] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T7,T8
1	1	Covered	T3,T10,T22

 LINE       714
 SUB-EXPRESSION (addr_hit[16] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T8,T10
1	1	Covered	T3,T7,T10

 LINE       714
 SUB-EXPRESSION (addr_hit[17] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T8,T10
1	1	Covered	T5,T8,T10

 LINE       736
 EXPRESSION (addr_hit[0] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T90,T91,T92
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T13,T14,T15
1	1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : rom_ctrl_regs_reg_top

	Line No.	Total	Covered	Percent
Branches		24	24	100.00
TERNARY	710	2	2	100.00
IF	68	3	3	100.00
CASE	766	19	19	100.00

710          assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
                                                  -1-  
                                                  ==>  
                                                  ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

68             if (!rst_ni) begin
               -1-  
69               err_q <= '0;
                 ==>
70             end else if (intg_err || reg_we_err) begin
                        -2-  
71               err_q <= 1'b1;
                 ==>
72             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T27,T28,T29
0	0	Covered	T1,T2,T3

766            unique case (1'b1)
                      -1-  
767              addr_hit[0]: begin
768                reg_rdata_next[0] = '0;
                   ==>
769              end
770        
771              addr_hit[1]: begin
772                reg_rdata_next[0] = fatal_alert_cause_checker_error_qs;
                   ==>
773                reg_rdata_next[1] = fatal_alert_cause_integrity_error_qs;
774              end
775        
776              addr_hit[2]: begin
777                reg_rdata_next[31:0] = digest_0_qs;
                   ==>
778              end
779        
780              addr_hit[3]: begin
781                reg_rdata_next[31:0] = digest_1_qs;
                   ==>
782              end
783        
784              addr_hit[4]: begin
785                reg_rdata_next[31:0] = digest_2_qs;
                   ==>
786              end
787        
788              addr_hit[5]: begin
789                reg_rdata_next[31:0] = digest_3_qs;
                   ==>
790              end
791        
792              addr_hit[6]: begin
793                reg_rdata_next[31:0] = digest_4_qs;
                   ==>
794              end
795        
796              addr_hit[7]: begin
797                reg_rdata_next[31:0] = digest_5_qs;
                   ==>
798              end
799        
800              addr_hit[8]: begin
801                reg_rdata_next[31:0] = digest_6_qs;
                   ==>
802              end
803        
804              addr_hit[9]: begin
805                reg_rdata_next[31:0] = digest_7_qs;
                   ==>
806              end
807        
808              addr_hit[10]: begin
809                reg_rdata_next[31:0] = exp_digest_0_qs;
                   ==>
810              end
811        
812              addr_hit[11]: begin
813                reg_rdata_next[31:0] = exp_digest_1_qs;
                   ==>
814              end
815        
816              addr_hit[12]: begin
817                reg_rdata_next[31:0] = exp_digest_2_qs;
                   ==>
818              end
819        
820              addr_hit[13]: begin
821                reg_rdata_next[31:0] = exp_digest_3_qs;
                   ==>
822              end
823        
824              addr_hit[14]: begin
825                reg_rdata_next[31:0] = exp_digest_4_qs;
                   ==>
826              end
827        
828              addr_hit[15]: begin
829                reg_rdata_next[31:0] = exp_digest_5_qs;
                   ==>
830              end
831        
832              addr_hit[16]: begin
833                reg_rdata_next[31:0] = exp_digest_6_qs;
                   ==>
834              end
835        
836              addr_hit[17]: begin
837                reg_rdata_next[31:0] = exp_digest_7_qs;
                   ==>
838              end
839        
840              default: begin
841                reg_rdata_next = '1;
                   ==>

Branches:

-1-	Status	Tests
addr_hit[0]	Covered	T1,T2,T3
addr_hit[1]	Covered	T2,T3,T4
addr_hit[2]	Covered	T3,T4,T5
addr_hit[3]	Covered	T1,T3,T4
addr_hit[4]	Covered	T1,T2,T3
addr_hit[5]	Covered	T4,T5,T6
addr_hit[6]	Covered	T1,T4,T5
addr_hit[7]	Covered	T2,T3,T4
addr_hit[8]	Covered	T4,T5,T6
addr_hit[9]	Covered	T1,T3,T4
addr_hit[10]	Covered	T3,T4,T5
addr_hit[11]	Covered	T4,T5,T6
addr_hit[12]	Covered	T2,T4,T5
addr_hit[13]	Covered	T2,T4,T5
addr_hit[14]	Covered	T4,T5,T6
addr_hit[15]	Covered	T3,T4,T5
addr_hit[16]	Covered	T3,T4,T5
addr_hit[17]	Covered	T4,T5,T6
default	Covered	T1,T2,T3

---

Assert Coverage for Module : rom_ctrl_regs_reg_top

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
en2addrHit	45655785	43325	0	0
reAfterRv	45655785	43324	0	0
rePulse	45655785	16428	0	0
wePulse	45655785	26896	0	0

en2addrHit

Name	Attempts	Real Successes	Failures	Incomplete
Total	45655785	43325	0	0
T1	25079	6	0	0
T2	16563	6	0	0
T3	24954	19	0	0
T4	17210	0	0	0
T5	25493	16	0	0
T6	24853	6	0	0
T7	26084	16	0	0
T8	26159	16	0	0
T9	17781	0	0	0
T10	28941	48	0	0
T22	0	16	0	0
T23	0	16	0	0

reAfterRv

Name	Attempts	Real Successes	Failures	Incomplete
Total	45655785	43324	0	0
T1	25079	6	0	0
T2	16563	6	0	0
T3	24954	19	0	0
T4	17210	0	0	0
T5	25493	16	0	0
T6	24853	6	0	0
T7	26084	16	0	0
T8	26159	16	0	0
T9	17781	0	0	0
T10	28941	48	0	0
T22	0	16	0	0
T23	0	16	0	0

rePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	45655785	16428	0	0
T5	25493	16	0	0
T6	24853	0	0	0
T7	26084	16	0	0
T8	26159	16	0	0
T9	17781	0	0	0
T10	28941	48	0	0
T11	0	32	0	0
T12	0	1	0	0
T16	17489	0	0	0
T17	17456	0	0	0
T20	0	16	0	0
T22	25816	16	0	0
T23	99362	16	0	0
T30	0	1	0	0

wePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	45655785	26896	0	0
T1	25079	6	0	0
T2	16563	6	0	0
T3	24954	19	0	0
T4	17210	0	0	0
T5	25493	0	0	0
T6	24853	6	0	0
T7	26084	0	0	0
T8	26159	0	0	0
T9	17781	0	0	0
T10	28941	0	0	0
T13	0	64	0	0
T67	0	11	0	0
T69	0	15	0	0
T82	0	12	0	0
T86	0	2	0	0
T93	0	18	0	0