Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
dashboard | hierarchy | modlist | groups | tests | asserts


Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY   EXPECTED   UNCOVERED   COVERED   PERCENT   
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0



Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY   EXPECTED   UNCOVERED   COVERED   PERCENT   
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 55554 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 1633304 1 T1 3 T3 26 T4 19



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
values[0x4] 433178 1 T1 23 T3 310 T4 272
values[0x0] 616597 1 T12 16249 T13 17334 T14 20529
values[0x1] 639083 1 T12 16829 T13 17865 T14 21118



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 29639 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 1659219 1 T1 14 T3 162 T4 155



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
valid_sources[0x00] 6616 1 T3 3 T8 1 T10 13
valid_sources[0x01] 6613 1 T3 1 T11 1 T118 2
valid_sources[0x02] 6197 1 T3 1 T9 1 T32 2
valid_sources[0x03] 7142 1 T3 1 T8 1 T21 2
valid_sources[0x04] 7424 1 T3 1 T11 1 T32 13
valid_sources[0x05] 6424 1 T18 1 T120 2 T137 2
valid_sources[0x06] 6553 1 T3 2 T9 1 T21 1
valid_sources[0x07] 5977 1 T11 1 T120 3 T93 1
valid_sources[0x08] 5702 1 T3 3 T8 5 T11 1
valid_sources[0x09] 5981 1 T3 3 T8 2 T118 1
valid_sources[0x0a] 6472 1 T3 1 T118 1 T137 1
valid_sources[0x0b] 6464 1 T3 1 T118 2 T18 1
valid_sources[0x0c] 6796 1 T1 3 T3 2 T119 1
valid_sources[0x0d] 7132 1 T118 6 T137 4 T138 2
valid_sources[0x0e] 5395 1 T19 1 T137 2 T38 1
valid_sources[0x0f] 5895 1 T3 1 T32 3 T118 2
valid_sources[0x10] 5755 1 T3 2 T9 4 T32 2
valid_sources[0x11] 6912 1 T3 3 T118 1 T137 3
valid_sources[0x12] 6675 1 T118 1 T119 2 T120 4
valid_sources[0x13] 6689 1 T3 1 T8 2 T21 1
valid_sources[0x14] 7338 1 T10 2 T119 2 T139 1
valid_sources[0x15] 6336 1 T3 1 T11 1 T118 2
valid_sources[0x16] 5387 1 T3 1 T8 5 T120 5
valid_sources[0x17] 5168 1 T3 1 T9 1 T93 2
valid_sources[0x18] 6256 1 T3 1 T5 22 T118 1
valid_sources[0x19] 6555 1 T1 2 T3 3 T119 3
valid_sources[0x1a] 5272 1 T8 7 T11 3 T118 5
valid_sources[0x1b] 6506 1 T8 9 T11 1 T119 2
valid_sources[0x1c] 7505 1 T8 8 T118 2 T137 1
valid_sources[0x1d] 5908 1 T3 2 T9 1 T11 3
valid_sources[0x1e] 7256 1 T119 1 T120 5 T137 1
valid_sources[0x1f] 5858 1 T3 1 T9 1 T118 1
valid_sources[0x20] 7087 1 T8 1 T137 3 T38 1
valid_sources[0x21] 6379 1 T21 1 T118 1 T19 4
valid_sources[0x22] 5972 1 T4 17 T21 1 T118 2
valid_sources[0x23] 6276 1 T3 2 T11 2 T137 2
valid_sources[0x24] 6709 1 T3 3 T118 1 T137 3
valid_sources[0x25] 6762 1 T1 1 T3 2 T8 2
valid_sources[0x26] 5766 1 T3 1 T118 1 T18 2
valid_sources[0x27] 5153 1 T3 1 T137 2 T38 1
valid_sources[0x28] 6062 1 T3 5 T137 1 T138 1
valid_sources[0x29] 6907 1 T3 1 T10 24 T118 1
valid_sources[0x2a] 6341 1 T11 3 T118 7 T119 4
valid_sources[0x2b] 6122 1 T3 1 T118 1 T120 1
valid_sources[0x2c] 9129 1 T118 2 T137 2 T140 1
valid_sources[0x2d] 7383 1 T3 1 T120 3 T137 1
valid_sources[0x2e] 5625 1 T3 2 T10 1 T118 3
valid_sources[0x2f] 7510 1 T8 1 T118 1 T119 5
valid_sources[0x30] 6878 1 T4 14 T8 2 T119 2
valid_sources[0x31] 6109 1 T3 3 T8 4 T11 1
valid_sources[0x32] 5590 1 T3 1 T118 1 T119 1
valid_sources[0x33] 7125 1 T9 1 T118 3 T119 1
valid_sources[0x34] 5819 1 T3 3 T120 4 T137 4
valid_sources[0x35] 6075 1 T3 1 T8 1 T118 2
valid_sources[0x36] 6924 1 T3 1 T4 5 T120 3
valid_sources[0x37] 8316 1 T3 1 T8 2 T118 1
valid_sources[0x38] 6031 1 T11 1 T137 1 T38 2
valid_sources[0x39] 6416 1 T3 1 T11 1 T16 18
valid_sources[0x3a] 6281 1 T3 1 T11 3 T21 1
valid_sources[0x3b] 5840 1 T3 3 T11 1 T118 2
valid_sources[0x3c] 5276 1 T3 1 T8 3 T32 4
valid_sources[0x3d] 6199 1 T3 2 T21 1 T118 4
valid_sources[0x3e] 5749 1 T8 2 T120 4 T121 7
valid_sources[0x3f] 7326 1 T3 2 T118 1 T141 7
valid_sources[0x40] 5956 1 T8 3 T19 3 T120 3
valid_sources[0x41] 6450 1 T3 1 T119 3 T137 1
valid_sources[0x42] 6977 1 T8 4 T11 1 T119 15
valid_sources[0x43] 7281 1 T141 4 T38 2 T42 1
valid_sources[0x44] 7380 1 T1 2 T3 4 T11 1
valid_sources[0x45] 6941 1 T10 3 T32 5 T121 3
valid_sources[0x46] 6744 1 T3 4 T118 1 T137 1
valid_sources[0x47] 7334 1 T3 1 T118 2 T19 2
valid_sources[0x48] 7542 1 T3 2 T4 2 T119 1
valid_sources[0x49] 8327 1 T118 1 T137 4 T141 1
valid_sources[0x4a] 5714 1 T21 1 T118 5 T139 1
valid_sources[0x4b] 6144 1 T21 1 T120 2 T141 3
valid_sources[0x4c] 6815 1 T8 1 T138 1 T141 2
valid_sources[0x4d] 5829 1 T3 1 T32 22 T19 2
valid_sources[0x4e] 7619 1 T11 1 T118 2 T18 1
valid_sources[0x4f] 5792 1 T3 1 T119 2 T137 2
valid_sources[0x50] 6884 1 T3 1 T4 2 T11 1
valid_sources[0x51] 5274 1 T32 5 T118 3 T119 2
valid_sources[0x52] 7618 1 T137 1 T38 1 T142 1
valid_sources[0x53] 6002 1 T1 4 T21 1 T16 22
valid_sources[0x54] 7346 1 T3 4 T8 4 T11 1
valid_sources[0x55] 6705 1 T3 1 T10 3 T11 1
valid_sources[0x56] 7120 1 T4 3 T119 3 T137 3
valid_sources[0x57] 6067 1 T3 2 T4 10 T32 1
valid_sources[0x58] 5969 1 T4 26 T9 1 T118 2
valid_sources[0x59] 7710 1 T118 4 T119 5 T139 3
valid_sources[0x5a] 7059 1 T11 1 T118 3 T18 2
valid_sources[0x5b] 6477 1 T3 2 T118 1 T139 1
valid_sources[0x5c] 7833 1 T3 1 T4 10 T118 3
valid_sources[0x5d] 5752 1 T3 1 T19 1 T121 1
valid_sources[0x5e] 6824 1 T3 2 T121 6 T137 2
valid_sources[0x5f] 6634 1 T3 6 T8 1 T16 35
valid_sources[0x60] 6774 1 T8 2 T32 7 T90 18
valid_sources[0x61] 6872 1 T141 5 T38 3 T143 3
valid_sources[0x62] 6297 1 T3 1 T11 1 T137 3
valid_sources[0x63] 6988 1 T3 1 T118 1 T119 1
valid_sources[0x64] 6729 1 T1 4 T11 1 T118 1
valid_sources[0x65] 5941 1 T3 3 T8 1 T137 2
valid_sources[0x66] 6993 1 T118 7 T120 1 T137 2
valid_sources[0x67] 6030 1 T3 2 T118 1 T137 1
valid_sources[0x68] 7741 1 T1 2 T3 2 T10 9
valid_sources[0x69] 5150 1 T11 2 T137 1 T138 2
valid_sources[0x6a] 7618 1 T118 1 T119 4 T139 3
valid_sources[0x6b] 7210 1 T1 1 T3 1 T11 1
valid_sources[0x6c] 6369 1 T3 3 T10 12 T11 1
valid_sources[0x6d] 5223 1 T11 3 T137 3 T141 2
valid_sources[0x6e] 6591 1 T3 1 T71 13 T137 2
valid_sources[0x6f] 7786 1 T3 2 T118 1 T120 2
valid_sources[0x70] 6620 1 T3 1 T21 1 T118 1
valid_sources[0x71] 6446 1 T3 3 T4 44 T15 22
valid_sources[0x72] 6491 1 T3 4 T9 1 T11 2
valid_sources[0x73] 6838 1 T8 3 T118 3 T139 1
valid_sources[0x74] 6468 1 T8 6 T119 2 T137 1
valid_sources[0x75] 5783 1 T3 2 T121 1 T38 2
valid_sources[0x76] 6119 1 T19 6 T120 9 T140 1
valid_sources[0x77] 6324 1 T9 1 T11 1 T118 2
valid_sources[0x78] 6649 1 T3 3 T137 3 T141 1
valid_sources[0x79] 6928 1 T3 3 T11 1 T118 1
valid_sources[0x7a] 6489 1 T3 6 T137 3 T138 1
valid_sources[0x7b] 5609 1 T16 58 T137 2 T141 4
valid_sources[0x7c] 6979 1 T3 2 T118 2 T119 1
valid_sources[0x7d] 6778 1 T3 3 T118 2 T121 3
valid_sources[0x7e] 5873 1 T10 26 T11 1 T121 2
valid_sources[0x7f] 7583 1 T3 2 T4 17 T137 2
valid_sources[0x80] 5554 1 T11 1 T137 1 T141 1



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcode   cp_mask   cp_size   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
values[0x4] all_enables biggest_size 411039 1 T1 3 T3 26 T4 19
values[0x0] all_enables biggest_size 611165 1 T12 16117 T13 17184 T14 20333
values[0x1] all_enables biggest_size 611100 1 T12 16098 T13 17197 T14 20150


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 120246 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 1240886 1 T1 7 T2 4 T5 8



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
values[0x4] 336270 1 T1 16 T5 16 T6 1
values[0x0] 474899 1 T2 5 T7 5 T30 5
values[0x1] 549963 1 T2 5 T7 4 T30 5



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 52987 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 1308145 1 T1 11 T2 5 T5 9



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
valid_sources[0x00] 5154 1 T11 1 T12 18 T144 1
valid_sources[0x01] 4795 1 T145 2 T12 103 T49 12
valid_sources[0x02] 5382 1 T53 1 T146 1 T147 1
valid_sources[0x03] 5834 1 T10 2 T139 1 T20 1
valid_sources[0x04] 4765 1 T11 1 T20 2 T145 2
valid_sources[0x05] 5723 1 T43 1 T148 2 T51 1
valid_sources[0x06] 5312 1 T19 2 T37 1 T149 1
valid_sources[0x07] 5683 1 T71 1 T25 1 T39 3
valid_sources[0x08] 5452 1 T43 1 T46 1 T35 1
valid_sources[0x09] 5481 1 T150 1 T12 426 T151 1
valid_sources[0x0a] 5351 1 T152 3 T39 1 T153 1
valid_sources[0x0b] 5396 1 T43 1 T20 1 T45 3
valid_sources[0x0c] 5199 1 T21 1 T32 23 T152 1
valid_sources[0x0d] 4933 1 T21 1 T154 1 T12 4
valid_sources[0x0e] 4908 1 T2 1 T19 1 T152 1
valid_sources[0x0f] 6611 1 T152 1 T20 1 T24 1
valid_sources[0x10] 5232 1 T152 1 T36 5 T149 1
valid_sources[0x11] 6240 1 T155 2 T12 332 T49 3
valid_sources[0x12] 5364 1 T148 1 T145 1 T156 1
valid_sources[0x13] 5176 1 T39 1 T148 3 T157 1
valid_sources[0x14] 5481 1 T43 1 T20 1 T150 1
valid_sources[0x15] 6038 1 T1 3 T11 1 T21 1
valid_sources[0x16] 5450 1 T158 1 T43 1 T159 1
valid_sources[0x17] 5297 1 T40 3 T160 2 T12 10
valid_sources[0x18] 5076 1 T20 3 T53 1 T149 1
valid_sources[0x19] 4969 1 T21 1 T19 1 T91 16
valid_sources[0x1a] 6109 1 T150 1 T149 1 T12 386
valid_sources[0x1b] 5102 1 T11 1 T21 1 T45 1
valid_sources[0x1c] 4889 1 T23 2 T12 3 T144 1
valid_sources[0x1d] 5669 1 T160 2 T150 2 T145 1
valid_sources[0x1e] 5138 1 T21 1 T149 2 T12 10
valid_sources[0x1f] 5657 1 T92 1 T146 3 T12 111
valid_sources[0x20] 4915 1 T10 1 T18 2 T90 1
valid_sources[0x21] 5373 1 T146 1 T161 2 T136 1
valid_sources[0x22] 5436 1 T19 1 T39 1 T20 1
valid_sources[0x23] 4587 1 T152 1 T162 1 T12 29
valid_sources[0x24] 5018 1 T35 1 T150 1 T12 57
valid_sources[0x25] 5836 1 T31 1 T163 2 T43 1
valid_sources[0x26] 5165 1 T11 1 T138 32 T24 2
valid_sources[0x27] 5345 1 T2 1 T10 1 T19 1
valid_sources[0x28] 5676 1 T23 1 T46 1 T12 22
valid_sources[0x29] 5758 1 T80 6 T149 1 T12 375
valid_sources[0x2a] 5087 1 T19 3 T145 2 T149 1
valid_sources[0x2b] 5756 1 T10 4 T34 1 T157 1
valid_sources[0x2c] 5068 1 T1 1 T29 1 T32 1
valid_sources[0x2d] 5723 1 T15 1 T24 1 T35 1
valid_sources[0x2e] 5497 1 T2 1 T152 2 T44 32
valid_sources[0x2f] 4923 1 T152 1 T20 1 T164 1
valid_sources[0x30] 5933 1 T71 2 T39 1 T150 2
valid_sources[0x31] 5046 1 T163 2 T159 1 T46 1
valid_sources[0x32] 5440 1 T93 16 T158 5 T39 1
valid_sources[0x33] 5379 1 T80 2 T165 2 T35 1
valid_sources[0x34] 4707 1 T21 1 T39 3 T20 1
valid_sources[0x35] 5105 1 T152 1 T148 1 T149 2
valid_sources[0x36] 5355 1 T150 2 T156 1 T12 235
valid_sources[0x37] 5059 1 T25 3 T45 1 T150 1
valid_sources[0x38] 5485 1 T25 2 T166 1 T145 3
valid_sources[0x39] 5585 1 T19 1 T47 1 T159 1
valid_sources[0x3a] 5466 1 T39 1 T20 1 T46 1
valid_sources[0x3b] 5031 1 T11 1 T23 1 T148 1
valid_sources[0x3c] 5977 1 T39 1 T160 3 T150 1
valid_sources[0x3d] 5744 1 T53 2 T145 3 T51 1
valid_sources[0x3e] 5205 1 T1 2 T167 7 T157 1
valid_sources[0x3f] 5519 1 T15 1 T21 1 T19 2
valid_sources[0x40] 5322 1 T139 4 T152 1 T39 2
valid_sources[0x41] 4946 1 T15 1 T12 143 T49 1
valid_sources[0x42] 5390 1 T10 1 T71 1 T39 2
valid_sources[0x43] 5413 1 T168 2 T12 60 T169 1
valid_sources[0x44] 5009 1 T2 3 T10 1 T19 2
valid_sources[0x45] 5965 1 T10 1 T12 397 T65 1
valid_sources[0x46] 5526 1 T15 1 T75 1 T90 1
valid_sources[0x47] 5255 1 T1 1 T136 1 T12 30
valid_sources[0x48] 5288 1 T71 1 T148 1 T51 1
valid_sources[0x49] 5822 1 T152 1 T163 2 T20 1
valid_sources[0x4a] 5274 1 T19 3 T12 12 T170 3
valid_sources[0x4b] 5675 1 T75 1 T152 1 T41 1
valid_sources[0x4c] 4939 1 T90 1 T39 1 T165 12
valid_sources[0x4d] 5598 1 T19 1 T152 1 T43 1
valid_sources[0x4e] 5075 1 T32 8 T158 1 T149 1
valid_sources[0x4f] 5436 1 T148 1 T171 2 T12 108
valid_sources[0x50] 4924 1 T19 1 T45 2 T51 1
valid_sources[0x51] 5638 1 T19 1 T146 2 T12 193
valid_sources[0x52] 5103 1 T163 1 T39 1 T35 1
valid_sources[0x53] 5861 1 T146 3 T12 488 T172 5
valid_sources[0x54] 5842 1 T11 2 T75 1 T39 1
valid_sources[0x55] 4761 1 T152 1 T148 3 T12 208
valid_sources[0x56] 5000 1 T19 1 T20 1 T27 1
valid_sources[0x57] 5578 1 T1 1 T159 1 T23 1
valid_sources[0x58] 4991 1 T75 1 T39 1 T20 1
valid_sources[0x59] 5076 1 T19 1 T52 31 T12 20
valid_sources[0x5a] 5331 1 T90 2 T92 1 T40 1
valid_sources[0x5b] 5665 1 T18 1 T19 1 T39 3
valid_sources[0x5c] 6086 1 T19 1 T159 1 T149 1
valid_sources[0x5d] 5972 1 T92 1 T160 5 T173 1
valid_sources[0x5e] 5003 1 T39 1 T160 1 T165 2
valid_sources[0x5f] 5302 1 T148 1 T150 1 T145 2
valid_sources[0x60] 5556 1 T6 1 T75 1 T19 2
valid_sources[0x61] 4818 1 T152 2 T39 2 T43 1
valid_sources[0x62] 5058 1 T71 1 T158 1 T45 2
valid_sources[0x63] 5031 1 T152 1 T39 1 T43 1
valid_sources[0x64] 4669 1 T19 4 T154 1 T12 9
valid_sources[0x65] 5120 1 T18 2 T36 1 T12 262
valid_sources[0x66] 5605 1 T15 2 T152 1 T46 1
valid_sources[0x67] 5000 1 T78 1 T46 1 T12 335
valid_sources[0x68] 5020 1 T1 1 T21 1 T20 1
valid_sources[0x69] 5126 1 T152 1 T39 1 T149 1
valid_sources[0x6a] 5878 1 T158 1 T20 1 T46 1
valid_sources[0x6b] 5029 1 T2 1 T79 3 T43 1
valid_sources[0x6c] 5555 1 T92 2 T152 1 T150 3
valid_sources[0x6d] 4926 1 T12 44 T174 1 T50 1
valid_sources[0x6e] 4818 1 T11 1 T39 1 T35 1
valid_sources[0x6f] 4984 1 T163 1 T175 1 T158 1
valid_sources[0x70] 5564 1 T163 1 T39 2 T159 1
valid_sources[0x71] 5443 1 T150 1 T12 7 T176 1
valid_sources[0x72] 5850 1 T11 1 T75 1 T152 1
valid_sources[0x73] 5441 1 T19 2 T150 1 T171 1
valid_sources[0x74] 5370 1 T18 2 T152 1 T20 2
valid_sources[0x75] 5070 1 T43 1 T51 3 T12 501
valid_sources[0x76] 5288 1 T19 1 T152 1 T53 1
valid_sources[0x77] 4981 1 T11 1 T21 1 T166 1
valid_sources[0x78] 5426 1 T75 1 T163 1 T39 1
valid_sources[0x79] 5429 1 T11 1 T71 1 T39 1
valid_sources[0x7a] 5136 1 T165 4 T177 1 T136 1
valid_sources[0x7b] 5792 1 T19 1 T51 4 T149 1
valid_sources[0x7c] 5025 1 T40 1 T43 1 T12 69
valid_sources[0x7d] 5487 1 T39 1 T40 3 T53 1
valid_sources[0x7e] 4944 1 T10 1 T20 1 T45 2
valid_sources[0x7f] 5122 1 T12 67 T178 1 T179 2
valid_sources[0x80] 5152 1 T10 2 T71 4 T180 1



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcode   cp_mask   cp_size   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
values[0x4] all_enables biggest_size 311734 1 T1 7 T5 8 T9 10
values[0x0] all_enables biggest_size 464960 1 T2 3 T7 2 T30 2
values[0x1] all_enables biggest_size 464192 1 T2 1 T75 1 T80 3