Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

2976964

1

T1

20

T3

284

T4

253

full_word

1906162

1

T1

3

T3

26

T4

19

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	4882816	1			T1	23		T3	310		T4	272
auto[TlIntgErrCmd]	108	1			T68	2		T69	6		T70	8
auto[TlIntgErrData]	101	1			T68	5		T69	3		T70	8
auto[TlIntgErrBoth]	101	1			T68	3		T69	1		T70	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

766233

1

T1

23

T3

310

T4

272

auto[1]

4116893

1

T12

110197

T13

110566

T14

141282

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	315340	1			T1	20		T3	284		T4	253
auto[TlIntgErrNone]	partial	auto[1]	2661349	1			T12	71765		T13	69993		T14	92675
auto[TlIntgErrNone]	full_word	auto[0]	450752	1			T1	3		T3	26		T4	19
auto[TlIntgErrNone]	full_word	auto[1]	1455375	1			T12	38432		T13	40573		T14	48607
auto[TlIntgErrCmd]	partial	auto[0]	44	1			T69	3		T70	3		T122	2
auto[TlIntgErrCmd]	partial	auto[1]	55	1			T68	1		T69	3		T70	5
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T130	2		T131	1		T132	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T68	1		T122	1		T127	1
auto[TlIntgErrData]	partial	auto[0]	39	1			T68	2		T70	1		T123	1
auto[TlIntgErrData]	partial	auto[1]	45	1			T68	2		T69	2		T70	5
auto[TlIntgErrData]	full_word	auto[0]	9	1			T68	1		T70	1		T122	1
auto[TlIntgErrData]	full_word	auto[1]	8	1			T69	1		T70	1		T123	1
auto[TlIntgErrBoth]	partial	auto[0]	42	1			T68	3		T70	2		T122	2
auto[TlIntgErrBoth]	partial	auto[1]	50	1			T69	1		T70	2		T122	1
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T133	1		T124	1		T132	1
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T130	1		T133	1		T134	1