Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

485858

1

T2

36

T3

35

T4

59

full_word

301454

1

T2

2

T3

2

T5

6

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	787032	1			T2	38		T3	37		T4	59
auto[TlIntgErrCmd]	100	1			T74	5		T75	5		T76	3
auto[TlIntgErrData]	83	1			T74	1		T75	3		T76	2
auto[TlIntgErrBoth]	97	1			T74	4		T75	2		T76	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

144281

1

T2

38

T3

37

T4

59

auto[1]

643031

1

T13

5593

T14

5737

T15

11212

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	71422	1			T2	36		T3	35		T4	59
auto[TlIntgErrNone]	partial	auto[1]	414182	1			T13	3362		T14	3309		T15	7382
auto[TlIntgErrNone]	full_word	auto[0]	72741	1			T2	2		T3	2		T5	6
auto[TlIntgErrNone]	full_word	auto[1]	228687	1			T13	2231		T14	2428		T15	3830
auto[TlIntgErrCmd]	partial	auto[0]	36	1			T74	3		T75	2		T76	2
auto[TlIntgErrCmd]	partial	auto[1]	58	1			T74	1		T75	3		T76	1
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T74	1		T128	2		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T131	1		T134	1		T135	1
auto[TlIntgErrData]	partial	auto[0]	34	1			T74	1		T76	1		T125	1
auto[TlIntgErrData]	partial	auto[1]	39	1			T75	3		T76	1		T125	2
auto[TlIntgErrData]	full_word	auto[0]	5	1			T128	1		T134	4		-	-
auto[TlIntgErrData]	full_word	auto[1]	5	1			T129	1		T133	1		T136	1
auto[TlIntgErrBoth]	partial	auto[0]	33	1			T74	2		T75	1		T76	1
auto[TlIntgErrBoth]	partial	auto[1]	54	1			T74	2		T75	1		T76	2
auto[TlIntgErrBoth]	full_word	auto[0]	7	1			T76	2		T131	1		T137	1
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T128	1		T134	1		T138	1