Unified Coverage Report :: Module :: prim_prince

Module : prim_prince

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/sim-vcs/../src/lowrisc_prim_cipher_0/rtl/prim_prince.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_rom_scramble_enabled.u_rom.u_prince	100.00			100.00

---

Module Instance : tb.dut.gen_rom_scramble_enabled.u_rom.u_prince

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
87.50	75.00					100.00	gen_rom_scramble_enabled.u_rom

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : prim_prince

	Total	Covered	Percent
Totals	6	6	100.00
Total Bits	164	164	100.00
Total Bits 0->1	82	82	100.00
Total Bits 1->0	82	82	100.00

Ports	6	6	100.00
Port Bits	164	164	100.00
Port Bits 0->1	82	82	100.00
Port Bits 1->0	82	82	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T6,T10,T11	Yes	T1,T2,T3	INPUT
valid_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
data_i[13:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
data_i[63:14]	Unreachable	Unreachable		Unreachable		INPUT
key_i[127:0]	Unreachable	Unreachable		Unreachable		INPUT
dec_i	Unreachable	Unreachable		Unreachable		INPUT
valid_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
data_o[63:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT