Unified Coverage Report :: Module :: prim_rom_adv

Module : prim_rom_adv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/default/sim-vcs/../src/lowrisc_prim_rom_adv_0.1/rtl/prim_rom_adv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_rom_scramble_enabled.u_rom.u_rom	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_rom_scramble_enabled.u_rom.u_rom

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44	83.33				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	gen_rom_scramble_enabled.u_rom

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_rom	88.89	66.67				100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : prim_rom_adv

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	40	3	3	100.00

39                        always_ff @(posedge clk_i or negedge rst_ni) begin
40         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
41         1/1                rvalid_o <= 1'b0;
           Tests:       T1 T2 T3 
42                          end else begin
43         1/1                rvalid_o <= req_i;
           Tests:       T1 T2 T3 

---

Branch Coverage for Module : prim_rom_adv

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	40	2	2	100.00

40             if (!rst_ni) begin
               -1-  
41               rvalid_o <= 1'b0;
                 ==>
42             end else begin
43               rvalid_o <= req_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_rom_adv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
noXOnCsI	37739680	37739680	0	0

noXOnCsI

Name	Attempts	Real Successes	Failures	Incomplete
Total	37739680	37739680	0	0
T1	16972	16972	0	0
T2	18530	18530	0	0
T3	21485	21485	0	0
T4	100766	100766	0	0
T5	29220	29220	0	0
T6	26605	26605	0	0
T7	29736	29736	0	0
T8	27445	27445	0	0
T9	26699	26699	0	0
T10	33979	33979	0	0