RSTMGR Simulation Results

Friday May 19 2023 07:05:15 UTC

GitHub Revision: 30db5a999

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 2235272161

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rstmgr_smoke	1.530s	250.742us	50	50	100.00
V1	csr_hw_reset	rstmgr_csr_hw_reset	0.910s	136.736us	5	5	100.00
V1	csr_rw	rstmgr_csr_rw	0.870s	94.666us	20	20	100.00
V1	csr_bit_bash	rstmgr_csr_bit_bash	9.710s	2.284ms	5	5	100.00
V1	csr_aliasing	rstmgr_csr_aliasing	2.350s	436.294us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rstmgr_csr_mem_rw_with_rand_reset	1.710s	168.869us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rstmgr_csr_rw	0.870s	94.666us	20	20	100.00
		rstmgr_csr_aliasing	2.350s	436.294us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	reset_stretcher	rstmgr_por_stretcher	0.960s	259.402us	50	50	100.00
V2	sw_rst	rstmgr_sw_rst	2.650s	538.618us	50	50	100.00
V2	sw_rst_reset_race	rstmgr_sw_rst_reset_race	1.470s	274.114us	50	50	100.00
V2	reset_info	rstmgr_reset	7.070s	2.315ms	50	50	100.00
V2	cpu_info	rstmgr_reset	7.070s	2.315ms	50	50	100.00
V2	alert_info	rstmgr_reset	7.070s	2.315ms	50	50	100.00
V2	reset_info_capture	rstmgr_reset	7.070s	2.315ms	50	50	100.00
V2	stress_all	rstmgr_stress_all	47.370s	16.426ms	50	50	100.00
V2	alert_test	rstmgr_alert_test	0.810s	82.441us	50	50	100.00
V2	tl_d_oob_addr_access	rstmgr_tl_errors	3.400s	563.538us	20	20	100.00
V2	tl_d_illegal_access	rstmgr_tl_errors	3.400s	563.538us	20	20	100.00
V2	tl_d_outstanding_access	rstmgr_csr_hw_reset	0.910s	136.736us	5	5	100.00
		rstmgr_csr_rw	0.870s	94.666us	20	20	100.00
		rstmgr_csr_aliasing	2.350s	436.294us	5	5	100.00
		rstmgr_same_csr_outstanding	1.530s	231.069us	20	20	100.00
V2	tl_d_partial_access	rstmgr_csr_hw_reset	0.910s	136.736us	5	5	100.00
		rstmgr_csr_rw	0.870s	94.666us	20	20	100.00
		rstmgr_csr_aliasing	2.350s	436.294us	5	5	100.00
		rstmgr_same_csr_outstanding	1.530s	231.069us	20	20	100.00
V2		TOTAL			340	340	100.00
V2S	tl_intg_err	rstmgr_sec_cm	21.250s	17.410ms	5	5	100.00
		rstmgr_tl_intg_err	3.350s	935.337us	20	20	100.00
V2S	prim_count_check	rstmgr_sec_cm	21.250s	17.410ms	5	5	100.00
V2S	prim_fsm_check	rstmgr_sec_cm	21.250s	17.410ms	5	5	100.00
V2S	sec_cm_bus_integrity	rstmgr_tl_intg_err	3.350s	935.337us	20	20	100.00
V2S	sec_cm_scan_intersig_mubi	rstmgr_sec_cm_scan_intersig_mubi	1.200s	178.867us	50	50	100.00
V2S	sec_cm_leaf_rst_bkgn_chk	rstmgr_leaf_rst_cnsty	8.040s	2.163ms	49	50	98.00
V2S	sec_cm_leaf_rst_shadow	rstmgr_leaf_rst_shadow_attack	1.160s	243.871us	50	50	100.00
V2S	sec_cm_leaf_fsm_sparse	rstmgr_sec_cm	21.250s	17.410ms	5	5	100.00
V2S	sec_cm_sw_rst_config_regwen	rstmgr_csr_rw	0.870s	94.666us	20	20	100.00
V2S	sec_cm_dump_ctrl_config_regwen	rstmgr_csr_rw	0.870s	94.666us	20	20	100.00
V2S		TOTAL			174	175	99.43
V3	stress_all_with_rand_reset	rstmgr_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			619	620	99.84

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	8	8	8	100.00
V2S	5	5	4	80.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.52	99.41	99.24	99.88	--	99.83	100.00	98.77

Failure Buckets

• UVM_ERROR (cip_base_scoreboard.sv:281) scoreboard [scoreboard] alert fatal_cnsty_fault did not trigger max_delay:* has 1 failures:
  • Test rstmgr_leaf_rst_cnsty has 1 failures.

    • 2.rstmgr_leaf_rst_cnsty.1514682248
      Line 239, in log /container/opentitan-public/scratch/os_regression/rstmgr-sim-vcs/2.rstmgr_leaf_rst_cnsty/latest/run.log

        UVM_ERROR @ 179752494 ps: (cip_base_scoreboard.sv:281) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_cnsty_fault did not trigger max_delay:20
        UVM_INFO @ 179752494 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
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• 2023.05.15_18.46.51
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