Summary for Variable enable
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1600 |
1 |
|
|
T8 |
32 |
|
T9 |
32 |
|
T10 |
32 |
auto[1] |
7000 |
1 |
|
|
T1 |
3 |
|
T3 |
3 |
|
T7 |
85 |
Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1600 |
1 |
|
|
T8 |
32 |
|
T9 |
32 |
|
T10 |
32 |
auto[1] |
7000 |
1 |
|
|
T1 |
3 |
|
T3 |
3 |
|
T7 |
85 |
Summary for Variable rst_n
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for rst_n
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
2500 |
1 |
|
|
T7 |
31 |
|
T8 |
16 |
|
T9 |
16 |
auto[1] |
6100 |
1 |
|
|
T1 |
3 |
|
T3 |
3 |
|
T7 |
54 |
Summary for Variable rst_n_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for rst_n_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
2500 |
1 |
|
|
T7 |
31 |
|
T8 |
16 |
|
T9 |
16 |
auto[1] |
6100 |
1 |
|
|
T1 |
3 |
|
T3 |
3 |
|
T7 |
54 |
Summary for Cross sw_rst_cross
Samples crossed: enable rst_n
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for sw_rst_cross
Bins
enable | rst_n | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
400 |
1 |
|
|
T8 |
8 |
|
T9 |
8 |
|
T10 |
8 |
auto[0] |
auto[1] |
1200 |
1 |
|
|
T8 |
24 |
|
T9 |
24 |
|
T10 |
24 |
auto[1] |
auto[0] |
2100 |
1 |
|
|
T7 |
31 |
|
T8 |
8 |
|
T9 |
8 |
auto[1] |
auto[1] |
4900 |
1 |
|
|
T1 |
3 |
|
T3 |
3 |
|
T7 |
54 |
Summary for Variable enable
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1550 |
1 |
|
|
T1 |
3 |
|
T3 |
3 |
|
T8 |
28 |
auto[1] |
6750 |
1 |
|
|
T7 |
85 |
|
T8 |
32 |
|
T9 |
32 |
Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1550 |
1 |
|
|
T1 |
3 |
|
T3 |
3 |
|
T8 |
28 |
auto[1] |
6750 |
1 |
|
|
T7 |
85 |
|
T8 |
32 |
|
T9 |
32 |
Summary for Variable rst_n
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for rst_n
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
2350 |
1 |
|
|
T1 |
2 |
|
T3 |
2 |
|
T7 |
28 |
auto[1] |
5950 |
1 |
|
|
T1 |
1 |
|
T3 |
1 |
|
T7 |
57 |
Summary for Variable rst_n_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for rst_n_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
2350 |
1 |
|
|
T1 |
2 |
|
T3 |
2 |
|
T7 |
28 |
auto[1] |
5950 |
1 |
|
|
T1 |
1 |
|
T3 |
1 |
|
T7 |
57 |
Summary for Cross sw_rst_cross
Samples crossed: enable rst_n
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for sw_rst_cross
Bins
enable | rst_n | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
450 |
1 |
|
|
T1 |
2 |
|
T3 |
2 |
|
T8 |
7 |
auto[0] |
auto[1] |
1100 |
1 |
|
|
T1 |
1 |
|
T3 |
1 |
|
T8 |
21 |
auto[1] |
auto[0] |
1900 |
1 |
|
|
T7 |
28 |
|
T8 |
10 |
|
T9 |
10 |
auto[1] |
auto[1] |
4850 |
1 |
|
|
T7 |
57 |
|
T8 |
22 |
|
T9 |
22 |
Summary for Variable enable
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1350 |
1 |
|
|
T1 |
3 |
|
T3 |
3 |
|
T8 |
24 |
auto[1] |
6950 |
1 |
|
|
T7 |
85 |
|
T8 |
36 |
|
T9 |
36 |
Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1350 |
1 |
|
|
T1 |
3 |
|
T3 |
3 |
|
T8 |
24 |
auto[1] |
6950 |
1 |
|
|
T7 |
85 |
|
T8 |
36 |
|
T9 |
36 |
Summary for Variable rst_n
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for rst_n
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
2500 |
1 |
|
|
T1 |
1 |
|
T3 |
1 |
|
T7 |
32 |
auto[1] |
5800 |
1 |
|
|
T1 |
2 |
|
T3 |
2 |
|
T7 |
53 |
Summary for Variable rst_n_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for rst_n_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
2500 |
1 |
|
|
T1 |
1 |
|
T3 |
1 |
|
T7 |
32 |
auto[1] |
5800 |
1 |
|
|
T1 |
2 |
|
T3 |
2 |
|
T7 |
53 |
Summary for Cross sw_rst_cross
Samples crossed: enable rst_n
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for sw_rst_cross
Bins
enable | rst_n | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
350 |
1 |
|
|
T1 |
1 |
|
T3 |
1 |
|
T8 |
6 |
auto[0] |
auto[1] |
1000 |
1 |
|
|
T1 |
2 |
|
T3 |
2 |
|
T8 |
18 |
auto[1] |
auto[0] |
2150 |
1 |
|
|
T7 |
32 |
|
T8 |
11 |
|
T9 |
11 |
auto[1] |
auto[1] |
4800 |
1 |
|
|
T7 |
53 |
|
T8 |
25 |
|
T9 |
25 |
Summary for Variable enable
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1150 |
1 |
|
|
T1 |
3 |
|
T3 |
3 |
|
T8 |
20 |
auto[1] |
7150 |
1 |
|
|
T7 |
85 |
|
T8 |
40 |
|
T9 |
40 |
Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1150 |
1 |
|
|
T1 |
3 |
|
T3 |
3 |
|
T8 |
20 |
auto[1] |
7150 |
1 |
|
|
T7 |
85 |
|
T8 |
40 |
|
T9 |
40 |
Summary for Variable rst_n
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for rst_n
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
2150 |
1 |
|
|
T1 |
1 |
|
T3 |
1 |
|
T7 |
27 |
auto[1] |
6150 |
1 |
|
|
T1 |
2 |
|
T3 |
2 |
|
T7 |
58 |
Summary for Variable rst_n_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for rst_n_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
2150 |
1 |
|
|
T1 |
1 |
|
T3 |
1 |
|
T7 |
27 |
auto[1] |
6150 |
1 |
|
|
T1 |
2 |
|
T3 |
2 |
|
T7 |
58 |
Summary for Cross sw_rst_cross
Samples crossed: enable rst_n
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for sw_rst_cross
Bins
enable | rst_n | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
300 |
1 |
|
|
T1 |
1 |
|
T3 |
1 |
|
T8 |
5 |
auto[0] |
auto[1] |
850 |
1 |
|
|
T1 |
2 |
|
T3 |
2 |
|
T8 |
15 |
auto[1] |
auto[0] |
1850 |
1 |
|
|
T7 |
27 |
|
T8 |
10 |
|
T9 |
10 |
auto[1] |
auto[1] |
5300 |
1 |
|
|
T7 |
58 |
|
T8 |
30 |
|
T9 |
30 |
Summary for Variable enable
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
800 |
1 |
|
|
T8 |
16 |
|
T9 |
16 |
|
T10 |
16 |
auto[1] |
7500 |
1 |
|
|
T1 |
3 |
|
T3 |
3 |
|
T7 |
85 |
Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
800 |
1 |
|
|
T8 |
16 |
|
T9 |
16 |
|
T10 |
16 |
auto[1] |
7500 |
1 |
|
|
T1 |
3 |
|
T3 |
3 |
|
T7 |
85 |
Summary for Variable rst_n
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for rst_n
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
2650 |
1 |
|
|
T1 |
1 |
|
T3 |
1 |
|
T7 |
33 |
auto[1] |
5650 |
1 |
|
|
T1 |
2 |
|
T3 |
2 |
|
T7 |
52 |
Summary for Variable rst_n_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for rst_n_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
2650 |
1 |
|
|
T1 |
1 |
|
T3 |
1 |
|
T7 |
33 |
auto[1] |
5650 |
1 |
|
|
T1 |
2 |
|
T3 |
2 |
|
T7 |
52 |
Summary for Cross sw_rst_cross
Samples crossed: enable rst_n
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for sw_rst_cross
Bins
enable | rst_n | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
200 |
1 |
|
|
T8 |
4 |
|
T9 |
4 |
|
T10 |
4 |
auto[0] |
auto[1] |
600 |
1 |
|
|
T8 |
12 |
|
T9 |
12 |
|
T10 |
12 |
auto[1] |
auto[0] |
2450 |
1 |
|
|
T1 |
1 |
|
T3 |
1 |
|
T7 |
33 |
auto[1] |
auto[1] |
5050 |
1 |
|
|
T1 |
2 |
|
T3 |
2 |
|
T7 |
52 |
Summary for Variable enable
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
750 |
1 |
|
|
T1 |
3 |
|
T3 |
3 |
|
T8 |
12 |
auto[1] |
7550 |
1 |
|
|
T7 |
85 |
|
T8 |
48 |
|
T9 |
48 |
Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
750 |
1 |
|
|
T1 |
3 |
|
T3 |
3 |
|
T8 |
12 |
auto[1] |
7550 |
1 |
|
|
T7 |
85 |
|
T8 |
48 |
|
T9 |
48 |
Summary for Variable rst_n
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for rst_n
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
2550 |
1 |
|
|
T1 |
2 |
|
T3 |
2 |
|
T7 |
33 |
auto[1] |
5750 |
1 |
|
|
T1 |
1 |
|
T3 |
1 |
|
T7 |
52 |
Summary for Variable rst_n_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for rst_n_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
2550 |
1 |
|
|
T1 |
2 |
|
T3 |
2 |
|
T7 |
33 |
auto[1] |
5750 |
1 |
|
|
T1 |
1 |
|
T3 |
1 |
|
T7 |
52 |
Summary for Cross sw_rst_cross
Samples crossed: enable rst_n
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for sw_rst_cross
Bins
enable | rst_n | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
250 |
1 |
|
|
T1 |
2 |
|
T3 |
2 |
|
T8 |
3 |
auto[0] |
auto[1] |
500 |
1 |
|
|
T1 |
1 |
|
T3 |
1 |
|
T8 |
9 |
auto[1] |
auto[0] |
2300 |
1 |
|
|
T7 |
33 |
|
T8 |
13 |
|
T9 |
13 |
auto[1] |
auto[1] |
5250 |
1 |
|
|
T7 |
52 |
|
T8 |
35 |
|
T9 |
35 |
Summary for Variable enable
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
550 |
1 |
|
|
T1 |
3 |
|
T3 |
3 |
|
T8 |
8 |
auto[1] |
7750 |
1 |
|
|
T7 |
85 |
|
T8 |
52 |
|
T9 |
52 |
Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
550 |
1 |
|
|
T1 |
3 |
|
T3 |
3 |
|
T8 |
8 |
auto[1] |
7750 |
1 |
|
|
T7 |
85 |
|
T8 |
52 |
|
T9 |
52 |
Summary for Variable rst_n
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for rst_n
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
2100 |
1 |
|
|
T1 |
2 |
|
T3 |
2 |
|
T7 |
24 |
auto[1] |
6200 |
1 |
|
|
T1 |
1 |
|
T3 |
1 |
|
T7 |
61 |
Summary for Variable rst_n_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for rst_n_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
2100 |
1 |
|
|
T1 |
2 |
|
T3 |
2 |
|
T7 |
24 |
auto[1] |
6200 |
1 |
|
|
T1 |
1 |
|
T3 |
1 |
|
T7 |
61 |
Summary for Cross sw_rst_cross
Samples crossed: enable rst_n
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for sw_rst_cross
Bins
enable | rst_n | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
200 |
1 |
|
|
T1 |
2 |
|
T3 |
2 |
|
T8 |
2 |
auto[0] |
auto[1] |
350 |
1 |
|
|
T1 |
1 |
|
T3 |
1 |
|
T8 |
6 |
auto[1] |
auto[0] |
1900 |
1 |
|
|
T7 |
24 |
|
T8 |
14 |
|
T9 |
14 |
auto[1] |
auto[1] |
5850 |
1 |
|
|
T7 |
61 |
|
T8 |
38 |
|
T9 |
38 |
Summary for Variable enable
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
350 |
1 |
|
|
T1 |
3 |
|
T3 |
3 |
|
T8 |
4 |
auto[1] |
7950 |
1 |
|
|
T7 |
85 |
|
T8 |
56 |
|
T9 |
56 |
Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
350 |
1 |
|
|
T1 |
3 |
|
T3 |
3 |
|
T8 |
4 |
auto[1] |
7950 |
1 |
|
|
T7 |
85 |
|
T8 |
56 |
|
T9 |
56 |
Summary for Variable rst_n
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for rst_n
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
2600 |
1 |
|
|
T1 |
2 |
|
T3 |
2 |
|
T7 |
33 |
auto[1] |
5700 |
1 |
|
|
T1 |
1 |
|
T3 |
1 |
|
T7 |
52 |
Summary for Variable rst_n_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for rst_n_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
2600 |
1 |
|
|
T1 |
2 |
|
T3 |
2 |
|
T7 |
33 |
auto[1] |
5700 |
1 |
|
|
T1 |
1 |
|
T3 |
1 |
|
T7 |
52 |
Summary for Cross sw_rst_cross
Samples crossed: enable rst_n
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for sw_rst_cross
Bins
enable | rst_n | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
150 |
1 |
|
|
T1 |
2 |
|
T3 |
2 |
|
T8 |
1 |
auto[0] |
auto[1] |
200 |
1 |
|
|
T1 |
1 |
|
T3 |
1 |
|
T8 |
3 |
auto[1] |
auto[0] |
2450 |
1 |
|
|
T7 |
33 |
|
T8 |
16 |
|
T9 |
16 |
auto[1] |
auto[1] |
5500 |
1 |
|
|
T7 |
52 |
|
T8 |
40 |
|
T9 |
40 |