Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64




Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 825675 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 504665 1 T1 131 T3 131 T4 1020



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 721900 1 T1 186 T2 1 T3 186
values[0x0] 304060 1 T1 96 T3 96 T4 621
values[0x1] 304380 1 T1 97 T3 97 T4 607



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 692260 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 638080 1 T1 175 T2 1 T3 175



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 3875 1 T4 21 T5 21 T6 21
valid_sources[0x01] 4930 1 T1 12 T3 12 T4 5
valid_sources[0x02] 4445 1 T1 2 T3 2 T7 76
valid_sources[0x03] 5965 1 T4 16 T5 16 T6 16
valid_sources[0x04] 6925 1 T1 6 T3 6 T4 6
valid_sources[0x05] 2665 1 T7 41 T8 4 T9 4
valid_sources[0x06] 3015 1 T4 6 T5 6 T6 6
valid_sources[0x07] 4090 1 T4 5 T5 5 T6 5
valid_sources[0x08] 4570 1 T4 7 T5 7 T6 7
valid_sources[0x09] 6095 1 T4 1 T5 1 T6 1
valid_sources[0x0a] 8265 1 T1 2 T3 2 T4 7
valid_sources[0x0b] 3580 1 T4 9 T5 9 T6 9
valid_sources[0x0c] 6580 1 T4 30 T5 30 T6 30
valid_sources[0x0d] 5025 1 T4 15 T5 15 T6 15
valid_sources[0x0e] 5985 1 T1 1 T3 1 T4 12
valid_sources[0x0f] 7295 1 T4 17 T5 17 T6 17
valid_sources[0x10] 4510 1 T4 4 T5 4 T6 4
valid_sources[0x11] 5145 1 T4 14 T5 14 T6 14
valid_sources[0x12] 4560 1 T4 1 T5 1 T6 1
valid_sources[0x13] 7040 1 T1 5 T3 5 T4 16
valid_sources[0x14] 7070 1 T7 123 T8 4 T9 4
valid_sources[0x15] 3900 1 T4 8 T5 8 T6 8
valid_sources[0x16] 3855 1 T1 3 T3 3 T4 13
valid_sources[0x17] 7425 1 T4 31 T5 31 T6 31
valid_sources[0x18] 4715 1 T4 6 T5 6 T6 6
valid_sources[0x19] 5395 1 T1 8 T3 8 T4 14
valid_sources[0x1a] 6505 1 T1 15 T3 15 T4 1
valid_sources[0x1b] 7240 1 T1 8 T3 8 T4 19
valid_sources[0x1c] 6360 1 T4 7 T5 7 T6 7
valid_sources[0x1d] 4230 1 T1 10 T3 10 T4 6
valid_sources[0x1e] 3180 1 T4 2 T5 2 T6 2
valid_sources[0x1f] 6315 1 T4 2 T5 2 T6 2
valid_sources[0x20] 4650 1 T4 7 T5 7 T6 7
valid_sources[0x21] 3735 1 T4 10 T5 10 T6 10
valid_sources[0x22] 6275 1 T1 4 T3 4 T4 6
valid_sources[0x23] 3940 1 T1 1 T3 1 T7 46
valid_sources[0x24] 5120 1 T4 22 T5 22 T6 22
valid_sources[0x25] 6340 1 T4 20 T5 20 T6 20
valid_sources[0x26] 7305 1 T4 23 T5 23 T6 23
valid_sources[0x27] 5150 1 T4 25 T5 25 T6 25
valid_sources[0x28] 8745 1 T1 9 T3 9 T4 22
valid_sources[0x29] 4430 1 T4 9 T5 9 T6 9
valid_sources[0x2a] 6845 1 T4 23 T5 23 T6 23
valid_sources[0x2b] 4765 1 T4 1 T5 1 T6 1
valid_sources[0x2c] 3235 1 T4 3 T5 3 T6 3
valid_sources[0x2d] 5720 1 T4 5 T5 5 T6 5
valid_sources[0x2e] 4810 1 T4 15 T5 15 T6 15
valid_sources[0x2f] 3830 1 T4 3 T5 3 T6 3
valid_sources[0x30] 4710 1 T4 14 T5 14 T6 14
valid_sources[0x31] 5025 1 T4 9 T5 9 T6 9
valid_sources[0x32] 6990 1 T1 1 T3 1 T4 13
valid_sources[0x33] 4805 1 T1 10 T3 10 T4 4
valid_sources[0x34] 6115 1 T1 16 T3 16 T4 12
valid_sources[0x35] 4795 1 T1 1 T3 1 T4 6
valid_sources[0x36] 5155 1 T1 3 T3 3 T4 11
valid_sources[0x37] 5415 1 T4 22 T5 22 T6 22
valid_sources[0x38] 6160 1 T4 17 T5 17 T6 17
valid_sources[0x39] 4210 1 T4 14 T5 14 T6 14
valid_sources[0x3a] 4860 1 T4 22 T5 22 T6 22
valid_sources[0x3b] 6155 1 T1 4 T3 4 T4 27
valid_sources[0x3c] 4135 1 T4 2 T5 2 T6 2
valid_sources[0x3d] 4835 1 T1 1 T3 1 T4 12
valid_sources[0x3e] 4030 1 T1 4 T3 4 T4 11
valid_sources[0x3f] 4995 1 T4 6 T5 6 T6 6
valid_sources[0x40] 6560 1 T4 8 T5 8 T6 8
valid_sources[0x41] 6920 1 T1 4 T3 4 T4 14
valid_sources[0x42] 3890 1 T1 1 T3 1 T4 11
valid_sources[0x43] 7185 1 T4 34 T5 34 T6 34
valid_sources[0x44] 6010 1 T1 5 T3 5 T4 20
valid_sources[0x45] 6185 1 T1 2 T3 2 T4 30
valid_sources[0x46] 5805 1 T7 96 T11 96 T12 96
valid_sources[0x47] 4955 1 T1 1 T3 1 T4 4
valid_sources[0x48] 6585 1 T1 7 T3 7 T4 20
valid_sources[0x49] 4020 1 T4 6 T5 6 T6 6
valid_sources[0x4a] 5610 1 T4 27 T5 27 T6 27
valid_sources[0x4b] 6615 1 T1 4 T3 4 T4 11
valid_sources[0x4c] 5025 1 T4 27 T5 27 T6 27
valid_sources[0x4d] 4675 1 T1 4 T3 4 T4 8
valid_sources[0x4e] 3495 1 T4 21 T5 21 T6 21
valid_sources[0x4f] 4490 1 T4 27 T5 27 T6 27
valid_sources[0x50] 6525 1 T4 32 T5 32 T6 32
valid_sources[0x51] 3665 1 T4 8 T5 8 T6 8
valid_sources[0x52] 3905 1 T4 6 T5 6 T6 6
valid_sources[0x53] 7455 1 T4 4 T5 4 T6 4
valid_sources[0x54] 5985 1 T4 9 T5 9 T6 9
valid_sources[0x55] 7985 1 T1 12 T3 12 T4 27
valid_sources[0x56] 5420 1 T7 66 T11 66 T12 66
valid_sources[0x57] 4275 1 T4 24 T5 24 T6 24
valid_sources[0x58] 3010 1 T4 11 T5 11 T6 11
valid_sources[0x59] 6165 1 T4 16 T5 16 T6 16
valid_sources[0x5a] 5195 1 T4 8 T5 8 T6 8
valid_sources[0x5b] 5220 1 T7 94 T11 94 T12 94
valid_sources[0x5c] 3940 1 T1 1 T3 1 T4 10
valid_sources[0x5d] 4820 1 T4 2 T5 2 T6 2
valid_sources[0x5e] 5540 1 T4 15 T5 15 T6 15
valid_sources[0x5f] 2820 1 T4 2 T5 2 T6 2
valid_sources[0x60] 5995 1 T4 13 T5 13 T6 13
valid_sources[0x61] 5045 1 T1 2 T3 2 T4 9
valid_sources[0x62] 7970 1 T4 37 T5 37 T6 37
valid_sources[0x63] 7615 1 T4 14 T5 14 T6 14
valid_sources[0x64] 4470 1 T4 5 T5 5 T6 5
valid_sources[0x65] 5955 1 T1 12 T3 12 T4 12
valid_sources[0x66] 3980 1 T4 1 T5 1 T6 1
valid_sources[0x67] 5715 1 T1 5 T3 5 T4 13
valid_sources[0x68] 6640 1 T4 13 T5 13 T6 13
valid_sources[0x69] 4585 1 T4 5 T5 5 T6 5
valid_sources[0x6a] 4430 1 T7 84 T11 84 T12 84
valid_sources[0x6b] 6115 1 T1 4 T3 4 T4 9
valid_sources[0x6c] 5105 1 T4 7 T5 7 T6 7
valid_sources[0x6d] 5275 1 T4 8 T5 8 T6 8
valid_sources[0x6e] 6235 1 T4 23 T5 23 T6 23
valid_sources[0x6f] 4110 1 T7 63 T11 63 T12 63
valid_sources[0x70] 4500 1 T7 76 T8 5 T9 5
valid_sources[0x71] 6995 1 T4 2 T5 2 T6 2
valid_sources[0x72] 3170 1 T4 7 T5 7 T6 7
valid_sources[0x73] 6055 1 T4 15 T5 15 T6 15
valid_sources[0x74] 6500 1 T4 10 T5 10 T6 10
valid_sources[0x75] 4100 1 T4 17 T5 17 T6 17
valid_sources[0x76] 3175 1 T4 9 T5 9 T6 9
valid_sources[0x77] 4875 1 T7 72 T11 72 T12 72
valid_sources[0x78] 4400 1 T4 4 T5 4 T6 4
valid_sources[0x79] 7020 1 T1 5 T3 5 T4 5
valid_sources[0x7a] 3450 1 T4 1 T5 1 T6 1
valid_sources[0x7b] 3270 1 T4 14 T5 14 T6 14
valid_sources[0x7c] 3655 1 T1 2 T3 2 T4 11
valid_sources[0x7d] 5265 1 T4 10 T5 10 T6 10
valid_sources[0x7e] 5015 1 T1 1 T3 1 T4 7
valid_sources[0x7f] 9060 1 T4 3 T5 3 T6 3
valid_sources[0x80] 4990 1 T4 12 T5 12 T6 12



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 346325 1 T1 90 T3 90 T4 747
values[0x0] all_enables biggest_size 104235 1 T1 31 T3 31 T4 182
values[0x1] all_enables biggest_size 54105 1 T1 10 T3 10 T4 91

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%