Group : dv_base_reg_pkg::mubi_cov#(4,32'sh00000006,32'sh00000009)::mubi_cg
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Group : dv_base_reg_pkg::mubi_cov#(4,32'sh00000006,32'sh00000009)::mubi_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 58.33 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_dv_base_reg_0/dv_base_mubi_cov.sv

2 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
mubi4_cov_of_mubi4_cov_of_rstmgr_reg_block.reset_req.val 16.67 1 100 1 64 64
mubi4_cov_of_mubi4_cov_of_tb.dut.u_scanmode_mubi_cov_if 100.00 1 100 1 64 64




Group Instance : mubi4_cov_of_mubi4_cov_of_rstmgr_reg_block.reset_req.val
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
16.67 1 100 1 64 64




Summary for Group Instance mubi4_cov_of_mubi4_cov_of_rstmgr_reg_block.reset_req.val

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 5 1 16.67


Variables for Group Instance mubi4_cov_of_mubi4_cov_of_rstmgr_reg_block.reset_req.val
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_value 6 5 1 16.67 100 1 1 0



Group Instance : mubi4_cov_of_mubi4_cov_of_tb.dut.u_scanmode_mubi_cov_if
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance mubi4_cov_of_mubi4_cov_of_tb.dut.u_scanmode_mubi_cov_if

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00


Variables for Group Instance mubi4_cov_of_mubi4_cov_of_tb.dut.u_scanmode_mubi_cov_if
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_value 6 0 6 100.00 100 1 1 0


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 6 5 1 16.67


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
others[0] 0 1 1
others[1] 0 1 1
others[2] 0 1 1
others[3] 0 1 1
false 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
true 7500 1 T1 1 T3 1 T4 21


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 6 0 6 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 1000 1 T24 20 T70 20 T35 20
others[1] 700 1 T24 14 T70 14 T35 14
others[2] 850 1 T24 17 T70 17 T35 17
others[3] 1450 1 T24 29 T70 29 T35 29
false 29295 1 T1 6 T2 2 T3 6
true 3450 1 T1 1 T3 1 T4 9

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%