Line Coverage for Module :
prim_generic_clock_mux2
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Module :
prim_generic_clock_mux2
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Module :
prim_generic_clock_mux2
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
1642020 |
1609700 |
0 |
0 |
selKnown1 |
253120 |
220800 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1642020 |
1609700 |
0 |
0 |
T1 |
347 |
284 |
0 |
0 |
T2 |
160 |
96 |
0 |
0 |
T3 |
348 |
284 |
0 |
0 |
T4 |
3196 |
3132 |
0 |
0 |
T5 |
3196 |
3132 |
0 |
0 |
T6 |
3196 |
3132 |
0 |
0 |
T7 |
19406 |
19342 |
0 |
0 |
T8 |
144 |
80 |
0 |
0 |
T9 |
144 |
80 |
0 |
0 |
T10 |
144 |
80 |
0 |
0 |
T11 |
0 |
16546 |
0 |
0 |
T12 |
0 |
16546 |
0 |
0 |
T13 |
0 |
846 |
0 |
0 |
T14 |
0 |
17 |
0 |
0 |
T23 |
1 |
0 |
0 |
0 |
T24 |
0 |
8 |
0 |
0 |
T25 |
0 |
26 |
0 |
0 |
T43 |
0 |
10 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
253120 |
220800 |
0 |
0 |
T1 |
128 |
64 |
0 |
0 |
T2 |
64 |
0 |
0 |
0 |
T3 |
128 |
64 |
0 |
0 |
T4 |
640 |
576 |
0 |
0 |
T5 |
640 |
576 |
0 |
0 |
T6 |
640 |
576 |
0 |
0 |
T7 |
3776 |
3712 |
0 |
0 |
T8 |
64 |
0 |
0 |
0 |
T9 |
64 |
0 |
0 |
0 |
T10 |
64 |
0 |
0 |
0 |
T11 |
0 |
3712 |
0 |
0 |
T12 |
0 |
3712 |
0 |
0 |
T24 |
0 |
64 |
0 |
0 |
T70 |
0 |
64 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_lc_src.u_rst_aon_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_lc_src.u_rst_aon_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_lc_src.u_rst_aon_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
27855 |
27350 |
0 |
0 |
selKnown1 |
3955 |
3450 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
27855 |
27350 |
0 |
0 |
T1 |
6 |
5 |
0 |
0 |
T2 |
2 |
1 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
55 |
54 |
0 |
0 |
T5 |
55 |
54 |
0 |
0 |
T6 |
55 |
54 |
0 |
0 |
T7 |
330 |
329 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
329 |
0 |
0 |
T12 |
0 |
329 |
0 |
0 |
T13 |
0 |
18 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
3955 |
3450 |
0 |
0 |
T1 |
2 |
1 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
10 |
9 |
0 |
0 |
T5 |
10 |
9 |
0 |
0 |
T6 |
10 |
9 |
0 |
0 |
T7 |
59 |
58 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
58 |
0 |
0 |
T12 |
0 |
58 |
0 |
0 |
T24 |
0 |
1 |
0 |
0 |
T70 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_lc_src.gen_rst_pd_n[0].u_rst_pd_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_lc_src.gen_rst_pd_n[0].u_rst_pd_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_lc_src.gen_rst_pd_n[0].u_rst_pd_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
27855 |
27350 |
0 |
0 |
selKnown1 |
3955 |
3450 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
27855 |
27350 |
0 |
0 |
T1 |
6 |
5 |
0 |
0 |
T2 |
2 |
1 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
55 |
54 |
0 |
0 |
T5 |
55 |
54 |
0 |
0 |
T6 |
55 |
54 |
0 |
0 |
T7 |
330 |
329 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
329 |
0 |
0 |
T12 |
0 |
329 |
0 |
0 |
T13 |
0 |
18 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
3955 |
3450 |
0 |
0 |
T1 |
2 |
1 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
10 |
9 |
0 |
0 |
T5 |
10 |
9 |
0 |
0 |
T6 |
10 |
9 |
0 |
0 |
T7 |
59 |
58 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
58 |
0 |
0 |
T12 |
0 |
58 |
0 |
0 |
T24 |
0 |
1 |
0 |
0 |
T70 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sys_src.u_rst_aon_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_sys_src.u_rst_aon_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_sys_src.u_rst_aon_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
27855 |
27350 |
0 |
0 |
selKnown1 |
3955 |
3450 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
27855 |
27350 |
0 |
0 |
T1 |
6 |
5 |
0 |
0 |
T2 |
2 |
1 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
55 |
54 |
0 |
0 |
T5 |
55 |
54 |
0 |
0 |
T6 |
55 |
54 |
0 |
0 |
T7 |
330 |
329 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
329 |
0 |
0 |
T12 |
0 |
329 |
0 |
0 |
T13 |
0 |
18 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
3955 |
3450 |
0 |
0 |
T1 |
2 |
1 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
10 |
9 |
0 |
0 |
T5 |
10 |
9 |
0 |
0 |
T6 |
10 |
9 |
0 |
0 |
T7 |
59 |
58 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
58 |
0 |
0 |
T12 |
0 |
58 |
0 |
0 |
T24 |
0 |
1 |
0 |
0 |
T70 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sys_src.gen_rst_pd_n[0].u_rst_pd_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_sys_src.gen_rst_pd_n[0].u_rst_pd_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_sys_src.gen_rst_pd_n[0].u_rst_pd_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
27855 |
27350 |
0 |
0 |
selKnown1 |
3955 |
3450 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
27855 |
27350 |
0 |
0 |
T1 |
6 |
5 |
0 |
0 |
T2 |
2 |
1 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
55 |
54 |
0 |
0 |
T5 |
55 |
54 |
0 |
0 |
T6 |
55 |
54 |
0 |
0 |
T7 |
330 |
329 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
329 |
0 |
0 |
T12 |
0 |
329 |
0 |
0 |
T13 |
0 |
18 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
3955 |
3450 |
0 |
0 |
T1 |
2 |
1 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
10 |
9 |
0 |
0 |
T5 |
10 |
9 |
0 |
0 |
T6 |
10 |
9 |
0 |
0 |
T7 |
59 |
58 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
58 |
0 |
0 |
T12 |
0 |
58 |
0 |
0 |
T24 |
0 |
1 |
0 |
0 |
T70 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_daon_por.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_daon_por.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_daon_por.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
10955 |
10450 |
0 |
0 |
selKnown1 |
3955 |
3450 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
10955 |
10450 |
0 |
0 |
T1 |
2 |
1 |
0 |
0 |
T2 |
2 |
1 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
20 |
19 |
0 |
0 |
T5 |
20 |
19 |
0 |
0 |
T6 |
20 |
19 |
0 |
0 |
T7 |
128 |
127 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
127 |
0 |
0 |
T12 |
0 |
127 |
0 |
0 |
T24 |
0 |
1 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
3955 |
3450 |
0 |
0 |
T1 |
2 |
1 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
10 |
9 |
0 |
0 |
T5 |
10 |
9 |
0 |
0 |
T6 |
10 |
9 |
0 |
0 |
T7 |
59 |
58 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
58 |
0 |
0 |
T12 |
0 |
58 |
0 |
0 |
T24 |
0 |
1 |
0 |
0 |
T70 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_daon_por.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_daon_por.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_daon_por.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
27905 |
27400 |
0 |
0 |
selKnown1 |
3955 |
3450 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
27905 |
27400 |
0 |
0 |
T1 |
6 |
5 |
0 |
0 |
T2 |
2 |
1 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
55 |
54 |
0 |
0 |
T5 |
55 |
54 |
0 |
0 |
T6 |
55 |
54 |
0 |
0 |
T7 |
330 |
329 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
329 |
0 |
0 |
T12 |
0 |
329 |
0 |
0 |
T13 |
0 |
18 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
3955 |
3450 |
0 |
0 |
T1 |
2 |
1 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
10 |
9 |
0 |
0 |
T5 |
10 |
9 |
0 |
0 |
T6 |
10 |
9 |
0 |
0 |
T7 |
59 |
58 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
58 |
0 |
0 |
T12 |
0 |
58 |
0 |
0 |
T24 |
0 |
1 |
0 |
0 |
T70 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_daon_por_io.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_daon_por_io.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_daon_por_io.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
10955 |
10450 |
0 |
0 |
selKnown1 |
3955 |
3450 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
10955 |
10450 |
0 |
0 |
T1 |
2 |
1 |
0 |
0 |
T2 |
2 |
1 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
20 |
19 |
0 |
0 |
T5 |
20 |
19 |
0 |
0 |
T6 |
20 |
19 |
0 |
0 |
T7 |
128 |
127 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
127 |
0 |
0 |
T12 |
0 |
127 |
0 |
0 |
T24 |
0 |
1 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
3955 |
3450 |
0 |
0 |
T1 |
2 |
1 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
10 |
9 |
0 |
0 |
T5 |
10 |
9 |
0 |
0 |
T6 |
10 |
9 |
0 |
0 |
T7 |
59 |
58 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
58 |
0 |
0 |
T12 |
0 |
58 |
0 |
0 |
T24 |
0 |
1 |
0 |
0 |
T70 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_daon_por_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_daon_por_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_daon_por_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
27905 |
27400 |
0 |
0 |
selKnown1 |
3955 |
3450 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
27905 |
27400 |
0 |
0 |
T1 |
6 |
5 |
0 |
0 |
T2 |
2 |
1 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
55 |
54 |
0 |
0 |
T5 |
55 |
54 |
0 |
0 |
T6 |
55 |
54 |
0 |
0 |
T7 |
330 |
329 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
329 |
0 |
0 |
T12 |
0 |
329 |
0 |
0 |
T13 |
0 |
18 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
3955 |
3450 |
0 |
0 |
T1 |
2 |
1 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
10 |
9 |
0 |
0 |
T5 |
10 |
9 |
0 |
0 |
T6 |
10 |
9 |
0 |
0 |
T7 |
59 |
58 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
58 |
0 |
0 |
T12 |
0 |
58 |
0 |
0 |
T24 |
0 |
1 |
0 |
0 |
T70 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_daon_por_io_div2.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_daon_por_io_div2.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_daon_por_io_div2.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
10955 |
10450 |
0 |
0 |
selKnown1 |
3955 |
3450 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
10955 |
10450 |
0 |
0 |
T1 |
2 |
1 |
0 |
0 |
T2 |
2 |
1 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
20 |
19 |
0 |
0 |
T5 |
20 |
19 |
0 |
0 |
T6 |
20 |
19 |
0 |
0 |
T7 |
128 |
127 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
127 |
0 |
0 |
T12 |
0 |
127 |
0 |
0 |
T24 |
0 |
1 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
3955 |
3450 |
0 |
0 |
T1 |
2 |
1 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
10 |
9 |
0 |
0 |
T5 |
10 |
9 |
0 |
0 |
T6 |
10 |
9 |
0 |
0 |
T7 |
59 |
58 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
58 |
0 |
0 |
T12 |
0 |
58 |
0 |
0 |
T24 |
0 |
1 |
0 |
0 |
T70 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_daon_por_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_daon_por_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_daon_por_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
27905 |
27400 |
0 |
0 |
selKnown1 |
3955 |
3450 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
27905 |
27400 |
0 |
0 |
T1 |
6 |
5 |
0 |
0 |
T2 |
2 |
1 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
55 |
54 |
0 |
0 |
T5 |
55 |
54 |
0 |
0 |
T6 |
55 |
54 |
0 |
0 |
T7 |
330 |
329 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
329 |
0 |
0 |
T12 |
0 |
329 |
0 |
0 |
T13 |
0 |
18 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
3955 |
3450 |
0 |
0 |
T1 |
2 |
1 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
10 |
9 |
0 |
0 |
T5 |
10 |
9 |
0 |
0 |
T6 |
10 |
9 |
0 |
0 |
T7 |
59 |
58 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
58 |
0 |
0 |
T12 |
0 |
58 |
0 |
0 |
T24 |
0 |
1 |
0 |
0 |
T70 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_daon_por_io_div4.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_daon_por_io_div4.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_daon_por_io_div4.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
10955 |
10450 |
0 |
0 |
selKnown1 |
3955 |
3450 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
10955 |
10450 |
0 |
0 |
T1 |
2 |
1 |
0 |
0 |
T2 |
2 |
1 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
20 |
19 |
0 |
0 |
T5 |
20 |
19 |
0 |
0 |
T6 |
20 |
19 |
0 |
0 |
T7 |
128 |
127 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
127 |
0 |
0 |
T12 |
0 |
127 |
0 |
0 |
T24 |
0 |
1 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
3955 |
3450 |
0 |
0 |
T1 |
2 |
1 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
10 |
9 |
0 |
0 |
T5 |
10 |
9 |
0 |
0 |
T6 |
10 |
9 |
0 |
0 |
T7 |
59 |
58 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
58 |
0 |
0 |
T12 |
0 |
58 |
0 |
0 |
T24 |
0 |
1 |
0 |
0 |
T70 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_daon_por_io_div4.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_daon_por_io_div4.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_daon_por_io_div4.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
27905 |
27400 |
0 |
0 |
selKnown1 |
3955 |
3450 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
27905 |
27400 |
0 |
0 |
T1 |
6 |
5 |
0 |
0 |
T2 |
2 |
1 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
55 |
54 |
0 |
0 |
T5 |
55 |
54 |
0 |
0 |
T6 |
55 |
54 |
0 |
0 |
T7 |
330 |
329 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
329 |
0 |
0 |
T12 |
0 |
329 |
0 |
0 |
T13 |
0 |
18 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
3955 |
3450 |
0 |
0 |
T1 |
2 |
1 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
10 |
9 |
0 |
0 |
T5 |
10 |
9 |
0 |
0 |
T6 |
10 |
9 |
0 |
0 |
T7 |
59 |
58 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
58 |
0 |
0 |
T12 |
0 |
58 |
0 |
0 |
T24 |
0 |
1 |
0 |
0 |
T70 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_daon_por_usb.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_daon_por_usb.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_daon_por_usb.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
10955 |
10450 |
0 |
0 |
selKnown1 |
3955 |
3450 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
10955 |
10450 |
0 |
0 |
T1 |
2 |
1 |
0 |
0 |
T2 |
2 |
1 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
20 |
19 |
0 |
0 |
T5 |
20 |
19 |
0 |
0 |
T6 |
20 |
19 |
0 |
0 |
T7 |
128 |
127 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
127 |
0 |
0 |
T12 |
0 |
127 |
0 |
0 |
T24 |
0 |
1 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
3955 |
3450 |
0 |
0 |
T1 |
2 |
1 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
10 |
9 |
0 |
0 |
T5 |
10 |
9 |
0 |
0 |
T6 |
10 |
9 |
0 |
0 |
T7 |
59 |
58 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
58 |
0 |
0 |
T12 |
0 |
58 |
0 |
0 |
T24 |
0 |
1 |
0 |
0 |
T70 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_daon_por_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_daon_por_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_daon_por_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
27905 |
27400 |
0 |
0 |
selKnown1 |
3955 |
3450 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
27905 |
27400 |
0 |
0 |
T1 |
6 |
5 |
0 |
0 |
T2 |
2 |
1 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
55 |
54 |
0 |
0 |
T5 |
55 |
54 |
0 |
0 |
T6 |
55 |
54 |
0 |
0 |
T7 |
330 |
329 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
329 |
0 |
0 |
T12 |
0 |
329 |
0 |
0 |
T13 |
0 |
18 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
3955 |
3450 |
0 |
0 |
T1 |
2 |
1 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
10 |
9 |
0 |
0 |
T5 |
10 |
9 |
0 |
0 |
T6 |
10 |
9 |
0 |
0 |
T7 |
59 |
58 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
58 |
0 |
0 |
T12 |
0 |
58 |
0 |
0 |
T24 |
0 |
1 |
0 |
0 |
T70 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_daon_lc.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_daon_lc.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_daon_lc.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
27855 |
27350 |
0 |
0 |
selKnown1 |
3955 |
3450 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
27855 |
27350 |
0 |
0 |
T1 |
6 |
5 |
0 |
0 |
T2 |
2 |
1 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
55 |
54 |
0 |
0 |
T5 |
55 |
54 |
0 |
0 |
T6 |
55 |
54 |
0 |
0 |
T7 |
330 |
329 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
329 |
0 |
0 |
T12 |
0 |
329 |
0 |
0 |
T13 |
0 |
18 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
3955 |
3450 |
0 |
0 |
T1 |
2 |
1 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
10 |
9 |
0 |
0 |
T5 |
10 |
9 |
0 |
0 |
T6 |
10 |
9 |
0 |
0 |
T7 |
59 |
58 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
58 |
0 |
0 |
T12 |
0 |
58 |
0 |
0 |
T24 |
0 |
1 |
0 |
0 |
T70 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_daon_lc.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_daon_lc.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_daon_lc.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
27905 |
27400 |
0 |
0 |
selKnown1 |
3955 |
3450 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
27905 |
27400 |
0 |
0 |
T1 |
6 |
5 |
0 |
0 |
T2 |
2 |
1 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
55 |
54 |
0 |
0 |
T5 |
55 |
54 |
0 |
0 |
T6 |
55 |
54 |
0 |
0 |
T7 |
330 |
329 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
329 |
0 |
0 |
T12 |
0 |
329 |
0 |
0 |
T13 |
0 |
18 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
3955 |
3450 |
0 |
0 |
T1 |
2 |
1 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
10 |
9 |
0 |
0 |
T5 |
10 |
9 |
0 |
0 |
T6 |
10 |
9 |
0 |
0 |
T7 |
59 |
58 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
58 |
0 |
0 |
T12 |
0 |
58 |
0 |
0 |
T24 |
0 |
1 |
0 |
0 |
T70 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_d0_lc.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_d0_lc.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_d0_lc.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
27855 |
27350 |
0 |
0 |
selKnown1 |
3955 |
3450 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
27855 |
27350 |
0 |
0 |
T1 |
6 |
5 |
0 |
0 |
T2 |
2 |
1 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
55 |
54 |
0 |
0 |
T5 |
55 |
54 |
0 |
0 |
T6 |
55 |
54 |
0 |
0 |
T7 |
330 |
329 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
329 |
0 |
0 |
T12 |
0 |
329 |
0 |
0 |
T13 |
0 |
18 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
3955 |
3450 |
0 |
0 |
T1 |
2 |
1 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
10 |
9 |
0 |
0 |
T5 |
10 |
9 |
0 |
0 |
T6 |
10 |
9 |
0 |
0 |
T7 |
59 |
58 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
58 |
0 |
0 |
T12 |
0 |
58 |
0 |
0 |
T24 |
0 |
1 |
0 |
0 |
T70 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_d0_lc.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_d0_lc.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_d0_lc.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
27905 |
27400 |
0 |
0 |
selKnown1 |
3955 |
3450 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
27905 |
27400 |
0 |
0 |
T1 |
6 |
5 |
0 |
0 |
T2 |
2 |
1 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
55 |
54 |
0 |
0 |
T5 |
55 |
54 |
0 |
0 |
T6 |
55 |
54 |
0 |
0 |
T7 |
330 |
329 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
329 |
0 |
0 |
T12 |
0 |
329 |
0 |
0 |
T13 |
0 |
18 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
3955 |
3450 |
0 |
0 |
T1 |
2 |
1 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
10 |
9 |
0 |
0 |
T5 |
10 |
9 |
0 |
0 |
T6 |
10 |
9 |
0 |
0 |
T7 |
59 |
58 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
58 |
0 |
0 |
T12 |
0 |
58 |
0 |
0 |
T24 |
0 |
1 |
0 |
0 |
T70 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_daon_lc_shadowed.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_daon_lc_shadowed.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_daon_lc_shadowed.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
27855 |
27350 |
0 |
0 |
selKnown1 |
3955 |
3450 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
27855 |
27350 |
0 |
0 |
T1 |
6 |
5 |
0 |
0 |
T2 |
2 |
1 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
55 |
54 |
0 |
0 |
T5 |
55 |
54 |
0 |
0 |
T6 |
55 |
54 |
0 |
0 |
T7 |
330 |
329 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
329 |
0 |
0 |
T12 |
0 |
329 |
0 |
0 |
T13 |
0 |
18 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
3955 |
3450 |
0 |
0 |
T1 |
2 |
1 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
10 |
9 |
0 |
0 |
T5 |
10 |
9 |
0 |
0 |
T6 |
10 |
9 |
0 |
0 |
T7 |
59 |
58 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
58 |
0 |
0 |
T12 |
0 |
58 |
0 |
0 |
T24 |
0 |
1 |
0 |
0 |
T70 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_daon_lc_shadowed.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_daon_lc_shadowed.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_daon_lc_shadowed.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
27905 |
27400 |
0 |
0 |
selKnown1 |
3955 |
3450 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
27905 |
27400 |
0 |
0 |
T1 |
6 |
5 |
0 |
0 |
T2 |
2 |
1 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
55 |
54 |
0 |
0 |
T5 |
55 |
54 |
0 |
0 |
T6 |
55 |
54 |
0 |
0 |
T7 |
330 |
329 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
329 |
0 |
0 |
T12 |
0 |
329 |
0 |
0 |
T13 |
0 |
18 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
3955 |
3450 |
0 |
0 |
T1 |
2 |
1 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
10 |
9 |
0 |
0 |
T5 |
10 |
9 |
0 |
0 |
T6 |
10 |
9 |
0 |
0 |
T7 |
59 |
58 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
58 |
0 |
0 |
T12 |
0 |
58 |
0 |
0 |
T24 |
0 |
1 |
0 |
0 |
T70 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_d0_lc_shadowed.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_d0_lc_shadowed.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_d0_lc_shadowed.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
27855 |
27350 |
0 |
0 |
selKnown1 |
3955 |
3450 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
27855 |
27350 |
0 |
0 |
T1 |
6 |
5 |
0 |
0 |
T2 |
2 |
1 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
55 |
54 |
0 |
0 |
T5 |
55 |
54 |
0 |
0 |
T6 |
55 |
54 |
0 |
0 |
T7 |
330 |
329 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
329 |
0 |
0 |
T12 |
0 |
329 |
0 |
0 |
T13 |
0 |
18 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
3955 |
3450 |
0 |
0 |
T1 |
2 |
1 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
10 |
9 |
0 |
0 |
T5 |
10 |
9 |
0 |
0 |
T6 |
10 |
9 |
0 |
0 |
T7 |
59 |
58 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
58 |
0 |
0 |
T12 |
0 |
58 |
0 |
0 |
T24 |
0 |
1 |
0 |
0 |
T70 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_d0_lc_shadowed.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_d0_lc_shadowed.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_d0_lc_shadowed.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
27905 |
27400 |
0 |
0 |
selKnown1 |
3955 |
3450 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
27905 |
27400 |
0 |
0 |
T1 |
6 |
5 |
0 |
0 |
T2 |
2 |
1 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
55 |
54 |
0 |
0 |
T5 |
55 |
54 |
0 |
0 |
T6 |
55 |
54 |
0 |
0 |
T7 |
330 |
329 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
329 |
0 |
0 |
T12 |
0 |
329 |
0 |
0 |
T13 |
0 |
18 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
3955 |
3450 |
0 |
0 |
T1 |
2 |
1 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
10 |
9 |
0 |
0 |
T5 |
10 |
9 |
0 |
0 |
T6 |
10 |
9 |
0 |
0 |
T7 |
59 |
58 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
58 |
0 |
0 |
T12 |
0 |
58 |
0 |
0 |
T24 |
0 |
1 |
0 |
0 |
T70 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_daon_lc_aon.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_daon_lc_aon.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_daon_lc_aon.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
27855 |
27350 |
0 |
0 |
selKnown1 |
3955 |
3450 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
27855 |
27350 |
0 |
0 |
T1 |
6 |
5 |
0 |
0 |
T2 |
2 |
1 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
55 |
54 |
0 |
0 |
T5 |
55 |
54 |
0 |
0 |
T6 |
55 |
54 |
0 |
0 |
T7 |
330 |
329 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
329 |
0 |
0 |
T12 |
0 |
329 |
0 |
0 |
T13 |
0 |
18 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
3955 |
3450 |
0 |
0 |
T1 |
2 |
1 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
10 |
9 |
0 |
0 |
T5 |
10 |
9 |
0 |
0 |
T6 |
10 |
9 |
0 |
0 |
T7 |
59 |
58 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
58 |
0 |
0 |
T12 |
0 |
58 |
0 |
0 |
T24 |
0 |
1 |
0 |
0 |
T70 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_daon_lc_aon.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_daon_lc_aon.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_daon_lc_aon.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
27755 |
27250 |
0 |
0 |
selKnown1 |
3955 |
3450 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
27755 |
27250 |
0 |
0 |
T1 |
6 |
5 |
0 |
0 |
T2 |
2 |
1 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
55 |
54 |
0 |
0 |
T5 |
55 |
54 |
0 |
0 |
T6 |
55 |
54 |
0 |
0 |
T7 |
329 |
328 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
328 |
0 |
0 |
T12 |
0 |
328 |
0 |
0 |
T13 |
0 |
18 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
3955 |
3450 |
0 |
0 |
T1 |
2 |
1 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
10 |
9 |
0 |
0 |
T5 |
10 |
9 |
0 |
0 |
T6 |
10 |
9 |
0 |
0 |
T7 |
59 |
58 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
58 |
0 |
0 |
T12 |
0 |
58 |
0 |
0 |
T24 |
0 |
1 |
0 |
0 |
T70 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_daon_lc_io.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_daon_lc_io.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_daon_lc_io.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
27855 |
27350 |
0 |
0 |
selKnown1 |
3955 |
3450 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
27855 |
27350 |
0 |
0 |
T1 |
6 |
5 |
0 |
0 |
T2 |
2 |
1 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
55 |
54 |
0 |
0 |
T5 |
55 |
54 |
0 |
0 |
T6 |
55 |
54 |
0 |
0 |
T7 |
330 |
329 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
329 |
0 |
0 |
T12 |
0 |
329 |
0 |
0 |
T13 |
0 |
18 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
3955 |
3450 |
0 |
0 |
T1 |
2 |
1 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
10 |
9 |
0 |
0 |
T5 |
10 |
9 |
0 |
0 |
T6 |
10 |
9 |
0 |
0 |
T7 |
59 |
58 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
58 |
0 |
0 |
T12 |
0 |
58 |
0 |
0 |
T24 |
0 |
1 |
0 |
0 |
T70 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_daon_lc_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_daon_lc_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_daon_lc_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
27905 |
27400 |
0 |
0 |
selKnown1 |
3955 |
3450 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
27905 |
27400 |
0 |
0 |
T1 |
6 |
5 |
0 |
0 |
T2 |
2 |
1 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
55 |
54 |
0 |
0 |
T5 |
55 |
54 |
0 |
0 |
T6 |
55 |
54 |
0 |
0 |
T7 |
330 |
329 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
329 |
0 |
0 |
T12 |
0 |
329 |
0 |
0 |
T13 |
0 |
18 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
3955 |
3450 |
0 |
0 |
T1 |
2 |
1 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
10 |
9 |
0 |
0 |
T5 |
10 |
9 |
0 |
0 |
T6 |
10 |
9 |
0 |
0 |
T7 |
59 |
58 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
58 |
0 |
0 |
T12 |
0 |
58 |
0 |
0 |
T24 |
0 |
1 |
0 |
0 |
T70 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_d0_lc_io.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_d0_lc_io.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_d0_lc_io.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
27855 |
27350 |
0 |
0 |
selKnown1 |
3955 |
3450 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
27855 |
27350 |
0 |
0 |
T1 |
6 |
5 |
0 |
0 |
T2 |
2 |
1 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
55 |
54 |
0 |
0 |
T5 |
55 |
54 |
0 |
0 |
T6 |
55 |
54 |
0 |
0 |
T7 |
330 |
329 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
329 |
0 |
0 |
T12 |
0 |
329 |
0 |
0 |
T13 |
0 |
18 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
3955 |
3450 |
0 |
0 |
T1 |
2 |
1 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
10 |
9 |
0 |
0 |
T5 |
10 |
9 |
0 |
0 |
T6 |
10 |
9 |
0 |
0 |
T7 |
59 |
58 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
58 |
0 |
0 |
T12 |
0 |
58 |
0 |
0 |
T24 |
0 |
1 |
0 |
0 |
T70 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_d0_lc_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_d0_lc_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_d0_lc_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
27905 |
27400 |
0 |
0 |
selKnown1 |
3955 |
3450 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
27905 |
27400 |
0 |
0 |
T1 |
6 |
5 |
0 |
0 |
T2 |
2 |
1 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
55 |
54 |
0 |
0 |
T5 |
55 |
54 |
0 |
0 |
T6 |
55 |
54 |
0 |
0 |
T7 |
330 |
329 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
329 |
0 |
0 |
T12 |
0 |
329 |
0 |
0 |
T13 |
0 |
18 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
3955 |
3450 |
0 |
0 |
T1 |
2 |
1 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
10 |
9 |
0 |
0 |
T5 |
10 |
9 |
0 |
0 |
T6 |
10 |
9 |
0 |
0 |
T7 |
59 |
58 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
58 |
0 |
0 |
T12 |
0 |
58 |
0 |
0 |
T24 |
0 |
1 |
0 |
0 |
T70 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_daon_lc_io_div2.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_daon_lc_io_div2.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_daon_lc_io_div2.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
27855 |
27350 |
0 |
0 |
selKnown1 |
3955 |
3450 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
27855 |
27350 |
0 |
0 |
T1 |
6 |
5 |
0 |
0 |
T2 |
2 |
1 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
55 |
54 |
0 |
0 |
T5 |
55 |
54 |
0 |
0 |
T6 |
55 |
54 |
0 |
0 |
T7 |
330 |
329 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
329 |
0 |
0 |
T12 |
0 |
329 |
0 |
0 |
T13 |
0 |
18 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
3955 |
3450 |
0 |
0 |
T1 |
2 |
1 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
10 |
9 |
0 |
0 |
T5 |
10 |
9 |
0 |
0 |
T6 |
10 |
9 |
0 |
0 |
T7 |
59 |
58 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
58 |
0 |
0 |
T12 |
0 |
58 |
0 |
0 |
T24 |
0 |
1 |
0 |
0 |
T70 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_daon_lc_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_daon_lc_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_daon_lc_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
27905 |
27400 |
0 |
0 |
selKnown1 |
3955 |
3450 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
27905 |
27400 |
0 |
0 |
T1 |
6 |
5 |
0 |
0 |
T2 |
2 |
1 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
55 |
54 |
0 |
0 |
T5 |
55 |
54 |
0 |
0 |
T6 |
55 |
54 |
0 |
0 |
T7 |
330 |
329 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
329 |
0 |
0 |
T12 |
0 |
329 |
0 |
0 |
T13 |
0 |
18 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
3955 |
3450 |
0 |
0 |
T1 |
2 |
1 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
10 |
9 |
0 |
0 |
T5 |
10 |
9 |
0 |
0 |
T6 |
10 |
9 |
0 |
0 |
T7 |
59 |
58 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
58 |
0 |
0 |
T12 |
0 |
58 |
0 |
0 |
T24 |
0 |
1 |
0 |
0 |
T70 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_d0_lc_io_div2.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_d0_lc_io_div2.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_d0_lc_io_div2.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
27855 |
27350 |
0 |
0 |
selKnown1 |
3955 |
3450 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
27855 |
27350 |
0 |
0 |
T1 |
6 |
5 |
0 |
0 |
T2 |
2 |
1 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
55 |
54 |
0 |
0 |
T5 |
55 |
54 |
0 |
0 |
T6 |
55 |
54 |
0 |
0 |
T7 |
330 |
329 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
329 |
0 |
0 |
T12 |
0 |
329 |
0 |
0 |
T13 |
0 |
18 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
3955 |
3450 |
0 |
0 |
T1 |
2 |
1 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
10 |
9 |
0 |
0 |
T5 |
10 |
9 |
0 |
0 |
T6 |
10 |
9 |
0 |
0 |
T7 |
59 |
58 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
58 |
0 |
0 |
T12 |
0 |
58 |
0 |
0 |
T24 |
0 |
1 |
0 |
0 |
T70 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_d0_lc_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_d0_lc_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_d0_lc_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
27905 |
27400 |
0 |
0 |
selKnown1 |
3955 |
3450 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
27905 |
27400 |
0 |
0 |
T1 |
6 |
5 |
0 |
0 |
T2 |
2 |
1 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
55 |
54 |
0 |
0 |
T5 |
55 |
54 |
0 |
0 |
T6 |
55 |
54 |
0 |
0 |
T7 |
330 |
329 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
329 |
0 |
0 |
T12 |
0 |
329 |
0 |
0 |
T13 |
0 |
18 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
3955 |
3450 |
0 |
0 |
T1 |
2 |
1 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
10 |
9 |
0 |
0 |
T5 |
10 |
9 |
0 |
0 |
T6 |
10 |
9 |
0 |
0 |
T7 |
59 |
58 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
58 |
0 |
0 |
T12 |
0 |
58 |
0 |
0 |
T24 |
0 |
1 |
0 |
0 |
T70 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_daon_lc_io_div4.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_daon_lc_io_div4.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_daon_lc_io_div4.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
27855 |
27350 |
0 |
0 |
selKnown1 |
3955 |
3450 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
27855 |
27350 |
0 |
0 |
T1 |
6 |
5 |
0 |
0 |
T2 |
2 |
1 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
55 |
54 |
0 |
0 |
T5 |
55 |
54 |
0 |
0 |
T6 |
55 |
54 |
0 |
0 |
T7 |
330 |
329 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
329 |
0 |
0 |
T12 |
0 |
329 |
0 |
0 |
T13 |
0 |
18 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
3955 |
3450 |
0 |
0 |
T1 |
2 |
1 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
10 |
9 |
0 |
0 |
T5 |
10 |
9 |
0 |
0 |
T6 |
10 |
9 |
0 |
0 |
T7 |
59 |
58 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
58 |
0 |
0 |
T12 |
0 |
58 |
0 |
0 |
T24 |
0 |
1 |
0 |
0 |
T70 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_d0_lc_io_div4.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_d0_lc_io_div4.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_d0_lc_io_div4.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
27855 |
27350 |
0 |
0 |
selKnown1 |
3955 |
3450 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
27855 |
27350 |
0 |
0 |
T1 |
6 |
5 |
0 |
0 |
T2 |
2 |
1 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
55 |
54 |
0 |
0 |
T5 |
55 |
54 |
0 |
0 |
T6 |
55 |
54 |
0 |
0 |
T7 |
330 |
329 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
329 |
0 |
0 |
T12 |
0 |
329 |
0 |
0 |
T13 |
0 |
18 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
3955 |
3450 |
0 |
0 |
T1 |
2 |
1 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
10 |
9 |
0 |
0 |
T5 |
10 |
9 |
0 |
0 |
T6 |
10 |
9 |
0 |
0 |
T7 |
59 |
58 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
58 |
0 |
0 |
T12 |
0 |
58 |
0 |
0 |
T24 |
0 |
1 |
0 |
0 |
T70 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_daon_lc_io_div4_shadowed.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_daon_lc_io_div4_shadowed.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_daon_lc_io_div4_shadowed.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
27855 |
27350 |
0 |
0 |
selKnown1 |
3955 |
3450 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
27855 |
27350 |
0 |
0 |
T1 |
6 |
5 |
0 |
0 |
T2 |
2 |
1 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
55 |
54 |
0 |
0 |
T5 |
55 |
54 |
0 |
0 |
T6 |
55 |
54 |
0 |
0 |
T7 |
330 |
329 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
329 |
0 |
0 |
T12 |
0 |
329 |
0 |
0 |
T13 |
0 |
18 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
3955 |
3450 |
0 |
0 |
T1 |
2 |
1 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
10 |
9 |
0 |
0 |
T5 |
10 |
9 |
0 |
0 |
T6 |
10 |
9 |
0 |
0 |
T7 |
59 |
58 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
58 |
0 |
0 |
T12 |
0 |
58 |
0 |
0 |
T24 |
0 |
1 |
0 |
0 |
T70 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_d0_lc_io_div4_shadowed.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_d0_lc_io_div4_shadowed.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_d0_lc_io_div4_shadowed.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
27855 |
27350 |
0 |
0 |
selKnown1 |
3955 |
3450 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
27855 |
27350 |
0 |
0 |
T1 |
6 |
5 |
0 |
0 |
T2 |
2 |
1 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
55 |
54 |
0 |
0 |
T5 |
55 |
54 |
0 |
0 |
T6 |
55 |
54 |
0 |
0 |
T7 |
330 |
329 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
329 |
0 |
0 |
T12 |
0 |
329 |
0 |
0 |
T13 |
0 |
18 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
3955 |
3450 |
0 |
0 |
T1 |
2 |
1 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
10 |
9 |
0 |
0 |
T5 |
10 |
9 |
0 |
0 |
T6 |
10 |
9 |
0 |
0 |
T7 |
59 |
58 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
58 |
0 |
0 |
T12 |
0 |
58 |
0 |
0 |
T24 |
0 |
1 |
0 |
0 |
T70 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_daon_lc_usb.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_daon_lc_usb.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_daon_lc_usb.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
27855 |
27350 |
0 |
0 |
selKnown1 |
3955 |
3450 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
27855 |
27350 |
0 |
0 |
T1 |
6 |
5 |
0 |
0 |
T2 |
2 |
1 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
55 |
54 |
0 |
0 |
T5 |
55 |
54 |
0 |
0 |
T6 |
55 |
54 |
0 |
0 |
T7 |
330 |
329 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
329 |
0 |
0 |
T12 |
0 |
329 |
0 |
0 |
T13 |
0 |
18 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
3955 |
3450 |
0 |
0 |
T1 |
2 |
1 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
10 |
9 |
0 |
0 |
T5 |
10 |
9 |
0 |
0 |
T6 |
10 |
9 |
0 |
0 |
T7 |
59 |
58 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
58 |
0 |
0 |
T12 |
0 |
58 |
0 |
0 |
T24 |
0 |
1 |
0 |
0 |
T70 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_daon_lc_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_daon_lc_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_daon_lc_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
27905 |
27400 |
0 |
0 |
selKnown1 |
3955 |
3450 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
27905 |
27400 |
0 |
0 |
T1 |
6 |
5 |
0 |
0 |
T2 |
2 |
1 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
55 |
54 |
0 |
0 |
T5 |
55 |
54 |
0 |
0 |
T6 |
55 |
54 |
0 |
0 |
T7 |
330 |
329 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
329 |
0 |
0 |
T12 |
0 |
329 |
0 |
0 |
T13 |
0 |
18 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
3955 |
3450 |
0 |
0 |
T1 |
2 |
1 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
10 |
9 |
0 |
0 |
T5 |
10 |
9 |
0 |
0 |
T6 |
10 |
9 |
0 |
0 |
T7 |
59 |
58 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
58 |
0 |
0 |
T12 |
0 |
58 |
0 |
0 |
T24 |
0 |
1 |
0 |
0 |
T70 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_d0_lc_usb.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_d0_lc_usb.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_d0_lc_usb.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
27855 |
27350 |
0 |
0 |
selKnown1 |
3955 |
3450 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
27855 |
27350 |
0 |
0 |
T1 |
6 |
5 |
0 |
0 |
T2 |
2 |
1 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
55 |
54 |
0 |
0 |
T5 |
55 |
54 |
0 |
0 |
T6 |
55 |
54 |
0 |
0 |
T7 |
330 |
329 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
329 |
0 |
0 |
T12 |
0 |
329 |
0 |
0 |
T13 |
0 |
18 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
3955 |
3450 |
0 |
0 |
T1 |
2 |
1 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
10 |
9 |
0 |
0 |
T5 |
10 |
9 |
0 |
0 |
T6 |
10 |
9 |
0 |
0 |
T7 |
59 |
58 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
58 |
0 |
0 |
T12 |
0 |
58 |
0 |
0 |
T24 |
0 |
1 |
0 |
0 |
T70 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_d0_lc_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_d0_lc_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_d0_lc_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
27905 |
27400 |
0 |
0 |
selKnown1 |
3955 |
3450 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
27905 |
27400 |
0 |
0 |
T1 |
6 |
5 |
0 |
0 |
T2 |
2 |
1 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
55 |
54 |
0 |
0 |
T5 |
55 |
54 |
0 |
0 |
T6 |
55 |
54 |
0 |
0 |
T7 |
330 |
329 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
329 |
0 |
0 |
T12 |
0 |
329 |
0 |
0 |
T13 |
0 |
18 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
3955 |
3450 |
0 |
0 |
T1 |
2 |
1 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
10 |
9 |
0 |
0 |
T5 |
10 |
9 |
0 |
0 |
T6 |
10 |
9 |
0 |
0 |
T7 |
59 |
58 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
58 |
0 |
0 |
T12 |
0 |
58 |
0 |
0 |
T24 |
0 |
1 |
0 |
0 |
T70 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_d0_sys.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_d0_sys.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_d0_sys.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
27855 |
27350 |
0 |
0 |
selKnown1 |
3955 |
3450 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
27855 |
27350 |
0 |
0 |
T1 |
6 |
5 |
0 |
0 |
T2 |
2 |
1 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
55 |
54 |
0 |
0 |
T5 |
55 |
54 |
0 |
0 |
T6 |
55 |
54 |
0 |
0 |
T7 |
330 |
329 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
329 |
0 |
0 |
T12 |
0 |
329 |
0 |
0 |
T13 |
0 |
18 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
3955 |
3450 |
0 |
0 |
T1 |
2 |
1 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
10 |
9 |
0 |
0 |
T5 |
10 |
9 |
0 |
0 |
T6 |
10 |
9 |
0 |
0 |
T7 |
59 |
58 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
58 |
0 |
0 |
T12 |
0 |
58 |
0 |
0 |
T24 |
0 |
1 |
0 |
0 |
T70 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_d0_sys.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_d0_sys.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_d0_sys.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
27905 |
27400 |
0 |
0 |
selKnown1 |
3955 |
3450 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
27905 |
27400 |
0 |
0 |
T1 |
6 |
5 |
0 |
0 |
T2 |
2 |
1 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
55 |
54 |
0 |
0 |
T5 |
55 |
54 |
0 |
0 |
T6 |
55 |
54 |
0 |
0 |
T7 |
330 |
329 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
329 |
0 |
0 |
T12 |
0 |
329 |
0 |
0 |
T13 |
0 |
18 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
3955 |
3450 |
0 |
0 |
T1 |
2 |
1 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
10 |
9 |
0 |
0 |
T5 |
10 |
9 |
0 |
0 |
T6 |
10 |
9 |
0 |
0 |
T7 |
59 |
58 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
58 |
0 |
0 |
T12 |
0 |
58 |
0 |
0 |
T24 |
0 |
1 |
0 |
0 |
T70 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_daon_sys_io_div4.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_daon_sys_io_div4.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_daon_sys_io_div4.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
27855 |
27350 |
0 |
0 |
selKnown1 |
3955 |
3450 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
27855 |
27350 |
0 |
0 |
T1 |
6 |
5 |
0 |
0 |
T2 |
2 |
1 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
55 |
54 |
0 |
0 |
T5 |
55 |
54 |
0 |
0 |
T6 |
55 |
54 |
0 |
0 |
T7 |
330 |
329 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
329 |
0 |
0 |
T12 |
0 |
329 |
0 |
0 |
T13 |
0 |
18 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
3955 |
3450 |
0 |
0 |
T1 |
2 |
1 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
10 |
9 |
0 |
0 |
T5 |
10 |
9 |
0 |
0 |
T6 |
10 |
9 |
0 |
0 |
T7 |
59 |
58 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
58 |
0 |
0 |
T12 |
0 |
58 |
0 |
0 |
T24 |
0 |
1 |
0 |
0 |
T70 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_daon_sys_io_div4.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_daon_sys_io_div4.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_daon_sys_io_div4.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
27905 |
27400 |
0 |
0 |
selKnown1 |
3955 |
3450 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
27905 |
27400 |
0 |
0 |
T1 |
6 |
5 |
0 |
0 |
T2 |
2 |
1 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
55 |
54 |
0 |
0 |
T5 |
55 |
54 |
0 |
0 |
T6 |
55 |
54 |
0 |
0 |
T7 |
330 |
329 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
329 |
0 |
0 |
T12 |
0 |
329 |
0 |
0 |
T13 |
0 |
18 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
3955 |
3450 |
0 |
0 |
T1 |
2 |
1 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
10 |
9 |
0 |
0 |
T5 |
10 |
9 |
0 |
0 |
T6 |
10 |
9 |
0 |
0 |
T7 |
59 |
58 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
58 |
0 |
0 |
T12 |
0 |
58 |
0 |
0 |
T24 |
0 |
1 |
0 |
0 |
T70 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_d0_spi_device.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_d0_spi_device.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_d0_spi_device.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
29205 |
28700 |
0 |
0 |
selKnown1 |
3955 |
3450 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
29205 |
28700 |
0 |
0 |
T1 |
6 |
5 |
0 |
0 |
T2 |
2 |
1 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
55 |
54 |
0 |
0 |
T5 |
55 |
54 |
0 |
0 |
T6 |
55 |
54 |
0 |
0 |
T7 |
351 |
350 |
0 |
0 |
T8 |
7 |
6 |
0 |
0 |
T9 |
7 |
6 |
0 |
0 |
T10 |
7 |
6 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
3955 |
3450 |
0 |
0 |
T1 |
2 |
1 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
10 |
9 |
0 |
0 |
T5 |
10 |
9 |
0 |
0 |
T6 |
10 |
9 |
0 |
0 |
T7 |
59 |
58 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
58 |
0 |
0 |
T12 |
0 |
58 |
0 |
0 |
T24 |
0 |
1 |
0 |
0 |
T70 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_d0_spi_device.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_d0_spi_device.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_d0_spi_device.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
27905 |
27400 |
0 |
0 |
selKnown1 |
3955 |
3450 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
27905 |
27400 |
0 |
0 |
T1 |
6 |
5 |
0 |
0 |
T2 |
2 |
1 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
55 |
54 |
0 |
0 |
T5 |
55 |
54 |
0 |
0 |
T6 |
55 |
54 |
0 |
0 |
T7 |
330 |
329 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
329 |
0 |
0 |
T12 |
0 |
329 |
0 |
0 |
T13 |
0 |
18 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
3955 |
3450 |
0 |
0 |
T1 |
2 |
1 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
10 |
9 |
0 |
0 |
T5 |
10 |
9 |
0 |
0 |
T6 |
10 |
9 |
0 |
0 |
T7 |
59 |
58 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
58 |
0 |
0 |
T12 |
0 |
58 |
0 |
0 |
T24 |
0 |
1 |
0 |
0 |
T70 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_d0_spi_host0.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_d0_spi_host0.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_d0_spi_host0.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
29255 |
28750 |
0 |
0 |
selKnown1 |
3955 |
3450 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
29255 |
28750 |
0 |
0 |
T1 |
6 |
5 |
0 |
0 |
T2 |
2 |
1 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
55 |
54 |
0 |
0 |
T5 |
55 |
54 |
0 |
0 |
T6 |
55 |
54 |
0 |
0 |
T7 |
350 |
349 |
0 |
0 |
T8 |
9 |
8 |
0 |
0 |
T9 |
9 |
8 |
0 |
0 |
T10 |
9 |
8 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
3955 |
3450 |
0 |
0 |
T1 |
2 |
1 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
10 |
9 |
0 |
0 |
T5 |
10 |
9 |
0 |
0 |
T6 |
10 |
9 |
0 |
0 |
T7 |
59 |
58 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
58 |
0 |
0 |
T12 |
0 |
58 |
0 |
0 |
T24 |
0 |
1 |
0 |
0 |
T70 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_d0_spi_host0.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_d0_spi_host0.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_d0_spi_host0.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
27905 |
27400 |
0 |
0 |
selKnown1 |
3955 |
3450 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
27905 |
27400 |
0 |
0 |
T1 |
6 |
5 |
0 |
0 |
T2 |
2 |
1 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
55 |
54 |
0 |
0 |
T5 |
55 |
54 |
0 |
0 |
T6 |
55 |
54 |
0 |
0 |
T7 |
330 |
329 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
329 |
0 |
0 |
T12 |
0 |
329 |
0 |
0 |
T13 |
0 |
18 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
3955 |
3450 |
0 |
0 |
T1 |
2 |
1 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
10 |
9 |
0 |
0 |
T5 |
10 |
9 |
0 |
0 |
T6 |
10 |
9 |
0 |
0 |
T7 |
59 |
58 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
58 |
0 |
0 |
T12 |
0 |
58 |
0 |
0 |
T24 |
0 |
1 |
0 |
0 |
T70 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_d0_spi_host1.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_d0_spi_host1.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_d0_spi_host1.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
29405 |
28900 |
0 |
0 |
selKnown1 |
3955 |
3450 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
29405 |
28900 |
0 |
0 |
T1 |
6 |
5 |
0 |
0 |
T2 |
2 |
1 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
55 |
54 |
0 |
0 |
T5 |
55 |
54 |
0 |
0 |
T6 |
55 |
54 |
0 |
0 |
T7 |
352 |
351 |
0 |
0 |
T8 |
10 |
9 |
0 |
0 |
T9 |
10 |
9 |
0 |
0 |
T10 |
10 |
9 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
3955 |
3450 |
0 |
0 |
T1 |
2 |
1 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
10 |
9 |
0 |
0 |
T5 |
10 |
9 |
0 |
0 |
T6 |
10 |
9 |
0 |
0 |
T7 |
59 |
58 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
58 |
0 |
0 |
T12 |
0 |
58 |
0 |
0 |
T24 |
0 |
1 |
0 |
0 |
T70 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_d0_spi_host1.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_d0_spi_host1.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_d0_spi_host1.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
27905 |
27400 |
0 |
0 |
selKnown1 |
3955 |
3450 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
27905 |
27400 |
0 |
0 |
T1 |
6 |
5 |
0 |
0 |
T2 |
2 |
1 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
55 |
54 |
0 |
0 |
T5 |
55 |
54 |
0 |
0 |
T6 |
55 |
54 |
0 |
0 |
T7 |
330 |
329 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
329 |
0 |
0 |
T12 |
0 |
329 |
0 |
0 |
T13 |
0 |
18 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
3955 |
3450 |
0 |
0 |
T1 |
2 |
1 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
10 |
9 |
0 |
0 |
T5 |
10 |
9 |
0 |
0 |
T6 |
10 |
9 |
0 |
0 |
T7 |
59 |
58 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
58 |
0 |
0 |
T12 |
0 |
58 |
0 |
0 |
T24 |
0 |
1 |
0 |
0 |
T70 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_d0_usb.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_d0_usb.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_d0_usb.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
29155 |
28650 |
0 |
0 |
selKnown1 |
3955 |
3450 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
29155 |
28650 |
0 |
0 |
T1 |
6 |
5 |
0 |
0 |
T2 |
2 |
1 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
55 |
54 |
0 |
0 |
T5 |
55 |
54 |
0 |
0 |
T6 |
55 |
54 |
0 |
0 |
T7 |
348 |
347 |
0 |
0 |
T8 |
9 |
8 |
0 |
0 |
T9 |
9 |
8 |
0 |
0 |
T10 |
9 |
8 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
3955 |
3450 |
0 |
0 |
T1 |
2 |
1 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
10 |
9 |
0 |
0 |
T5 |
10 |
9 |
0 |
0 |
T6 |
10 |
9 |
0 |
0 |
T7 |
59 |
58 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
58 |
0 |
0 |
T12 |
0 |
58 |
0 |
0 |
T24 |
0 |
1 |
0 |
0 |
T70 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_d0_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_d0_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_d0_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
27905 |
27400 |
0 |
0 |
selKnown1 |
3955 |
3450 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
27905 |
27400 |
0 |
0 |
T1 |
6 |
5 |
0 |
0 |
T2 |
2 |
1 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
55 |
54 |
0 |
0 |
T5 |
55 |
54 |
0 |
0 |
T6 |
55 |
54 |
0 |
0 |
T7 |
330 |
329 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
329 |
0 |
0 |
T12 |
0 |
329 |
0 |
0 |
T13 |
0 |
18 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
3955 |
3450 |
0 |
0 |
T1 |
2 |
1 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
10 |
9 |
0 |
0 |
T5 |
10 |
9 |
0 |
0 |
T6 |
10 |
9 |
0 |
0 |
T7 |
59 |
58 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
58 |
0 |
0 |
T12 |
0 |
58 |
0 |
0 |
T24 |
0 |
1 |
0 |
0 |
T70 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_d0_usb_aon.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_d0_usb_aon.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_d0_usb_aon.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
29505 |
29000 |
0 |
0 |
selKnown1 |
3955 |
3450 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
29505 |
29000 |
0 |
0 |
T1 |
7 |
6 |
0 |
0 |
T2 |
2 |
1 |
0 |
0 |
T3 |
7 |
6 |
0 |
0 |
T4 |
55 |
54 |
0 |
0 |
T5 |
55 |
54 |
0 |
0 |
T6 |
55 |
54 |
0 |
0 |
T7 |
350 |
349 |
0 |
0 |
T8 |
13 |
12 |
0 |
0 |
T9 |
13 |
12 |
0 |
0 |
T10 |
13 |
12 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
3955 |
3450 |
0 |
0 |
T1 |
2 |
1 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
10 |
9 |
0 |
0 |
T5 |
10 |
9 |
0 |
0 |
T6 |
10 |
9 |
0 |
0 |
T7 |
59 |
58 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
58 |
0 |
0 |
T12 |
0 |
58 |
0 |
0 |
T24 |
0 |
1 |
0 |
0 |
T70 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_d0_usb_aon.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_d0_usb_aon.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_d0_usb_aon.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
27755 |
27250 |
0 |
0 |
selKnown1 |
3955 |
3450 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
27755 |
27250 |
0 |
0 |
T1 |
6 |
5 |
0 |
0 |
T2 |
2 |
1 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
55 |
54 |
0 |
0 |
T5 |
55 |
54 |
0 |
0 |
T6 |
55 |
54 |
0 |
0 |
T7 |
329 |
328 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
328 |
0 |
0 |
T12 |
0 |
328 |
0 |
0 |
T13 |
0 |
18 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
3955 |
3450 |
0 |
0 |
T1 |
2 |
1 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
10 |
9 |
0 |
0 |
T5 |
10 |
9 |
0 |
0 |
T6 |
10 |
9 |
0 |
0 |
T7 |
59 |
58 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
58 |
0 |
0 |
T12 |
0 |
58 |
0 |
0 |
T24 |
0 |
1 |
0 |
0 |
T70 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_d0_i2c0.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_d0_i2c0.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_d0_i2c0.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
29455 |
28950 |
0 |
0 |
selKnown1 |
3955 |
3450 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
29455 |
28950 |
0 |
0 |
T1 |
6 |
5 |
0 |
0 |
T2 |
2 |
1 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
55 |
54 |
0 |
0 |
T5 |
55 |
54 |
0 |
0 |
T6 |
55 |
54 |
0 |
0 |
T7 |
352 |
351 |
0 |
0 |
T8 |
11 |
10 |
0 |
0 |
T9 |
11 |
10 |
0 |
0 |
T10 |
11 |
10 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
3955 |
3450 |
0 |
0 |
T1 |
2 |
1 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
10 |
9 |
0 |
0 |
T5 |
10 |
9 |
0 |
0 |
T6 |
10 |
9 |
0 |
0 |
T7 |
59 |
58 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
58 |
0 |
0 |
T12 |
0 |
58 |
0 |
0 |
T24 |
0 |
1 |
0 |
0 |
T70 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_d0_i2c0.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_d0_i2c0.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_d0_i2c0.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
27905 |
27400 |
0 |
0 |
selKnown1 |
3955 |
3450 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
27905 |
27400 |
0 |
0 |
T1 |
6 |
5 |
0 |
0 |
T2 |
2 |
1 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
55 |
54 |
0 |
0 |
T5 |
55 |
54 |
0 |
0 |
T6 |
55 |
54 |
0 |
0 |
T7 |
330 |
329 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
329 |
0 |
0 |
T12 |
0 |
329 |
0 |
0 |
T13 |
0 |
18 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
3955 |
3450 |
0 |
0 |
T1 |
2 |
1 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
10 |
9 |
0 |
0 |
T5 |
10 |
9 |
0 |
0 |
T6 |
10 |
9 |
0 |
0 |
T7 |
59 |
58 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
58 |
0 |
0 |
T12 |
0 |
58 |
0 |
0 |
T24 |
0 |
1 |
0 |
0 |
T70 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_d0_i2c1.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_d0_i2c1.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_d0_i2c1.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
29405 |
28900 |
0 |
0 |
selKnown1 |
3955 |
3450 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
29405 |
28900 |
0 |
0 |
T1 |
6 |
5 |
0 |
0 |
T2 |
2 |
1 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
55 |
54 |
0 |
0 |
T5 |
55 |
54 |
0 |
0 |
T6 |
55 |
54 |
0 |
0 |
T7 |
348 |
347 |
0 |
0 |
T8 |
14 |
13 |
0 |
0 |
T9 |
14 |
13 |
0 |
0 |
T10 |
14 |
13 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
3955 |
3450 |
0 |
0 |
T1 |
2 |
1 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
10 |
9 |
0 |
0 |
T5 |
10 |
9 |
0 |
0 |
T6 |
10 |
9 |
0 |
0 |
T7 |
59 |
58 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
58 |
0 |
0 |
T12 |
0 |
58 |
0 |
0 |
T24 |
0 |
1 |
0 |
0 |
T70 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_d0_i2c1.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_d0_i2c1.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_d0_i2c1.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
27905 |
27400 |
0 |
0 |
selKnown1 |
3955 |
3450 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
27905 |
27400 |
0 |
0 |
T1 |
6 |
5 |
0 |
0 |
T2 |
2 |
1 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
55 |
54 |
0 |
0 |
T5 |
55 |
54 |
0 |
0 |
T6 |
55 |
54 |
0 |
0 |
T7 |
330 |
329 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
329 |
0 |
0 |
T12 |
0 |
329 |
0 |
0 |
T13 |
0 |
18 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
3955 |
3450 |
0 |
0 |
T1 |
2 |
1 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
10 |
9 |
0 |
0 |
T5 |
10 |
9 |
0 |
0 |
T6 |
10 |
9 |
0 |
0 |
T7 |
59 |
58 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
58 |
0 |
0 |
T12 |
0 |
58 |
0 |
0 |
T24 |
0 |
1 |
0 |
0 |
T70 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_d0_i2c2.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_d0_i2c2.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_d0_i2c2.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
29705 |
29200 |
0 |
0 |
selKnown1 |
3955 |
3450 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
29705 |
29200 |
0 |
0 |
T1 |
6 |
5 |
0 |
0 |
T2 |
2 |
1 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
55 |
54 |
0 |
0 |
T5 |
55 |
54 |
0 |
0 |
T6 |
55 |
54 |
0 |
0 |
T7 |
353 |
352 |
0 |
0 |
T8 |
15 |
14 |
0 |
0 |
T9 |
15 |
14 |
0 |
0 |
T10 |
15 |
14 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
3955 |
3450 |
0 |
0 |
T1 |
2 |
1 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
10 |
9 |
0 |
0 |
T5 |
10 |
9 |
0 |
0 |
T6 |
10 |
9 |
0 |
0 |
T7 |
59 |
58 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
58 |
0 |
0 |
T12 |
0 |
58 |
0 |
0 |
T24 |
0 |
1 |
0 |
0 |
T70 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_d0_i2c2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_d0_i2c2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_d0_i2c2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
27905 |
27400 |
0 |
0 |
selKnown1 |
3955 |
3450 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
27905 |
27400 |
0 |
0 |
T1 |
6 |
5 |
0 |
0 |
T2 |
2 |
1 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
55 |
54 |
0 |
0 |
T5 |
55 |
54 |
0 |
0 |
T6 |
55 |
54 |
0 |
0 |
T7 |
330 |
329 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
329 |
0 |
0 |
T12 |
0 |
329 |
0 |
0 |
T13 |
0 |
18 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
3955 |
3450 |
0 |
0 |
T1 |
2 |
1 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
10 |
9 |
0 |
0 |
T5 |
10 |
9 |
0 |
0 |
T6 |
10 |
9 |
0 |
0 |
T7 |
59 |
58 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
58 |
0 |
0 |
T12 |
0 |
58 |
0 |
0 |
T24 |
0 |
1 |
0 |
0 |
T70 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_root_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_root_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_root_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
8305 |
7800 |
0 |
0 |
selKnown1 |
3955 |
3450 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8305 |
7800 |
0 |
0 |
T2 |
18 |
17 |
0 |
0 |
T3 |
1 |
0 |
0 |
0 |
T4 |
11 |
10 |
0 |
0 |
T5 |
11 |
10 |
0 |
0 |
T6 |
11 |
10 |
0 |
0 |
T7 |
70 |
69 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
69 |
0 |
0 |
T12 |
0 |
69 |
0 |
0 |
T14 |
0 |
17 |
0 |
0 |
T23 |
1 |
0 |
0 |
0 |
T25 |
0 |
26 |
0 |
0 |
T43 |
0 |
10 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
3955 |
3450 |
0 |
0 |
T1 |
2 |
1 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
10 |
9 |
0 |
0 |
T5 |
10 |
9 |
0 |
0 |
T6 |
10 |
9 |
0 |
0 |
T7 |
59 |
58 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
58 |
0 |
0 |
T12 |
0 |
58 |
0 |
0 |
T24 |
0 |
1 |
0 |
0 |
T70 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_clean_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_clean_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_clean_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
11755 |
11250 |
0 |
0 |
selKnown1 |
3955 |
3450 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
11755 |
11250 |
0 |
0 |
T1 |
2 |
1 |
0 |
0 |
T2 |
18 |
17 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
20 |
19 |
0 |
0 |
T5 |
20 |
19 |
0 |
0 |
T6 |
20 |
19 |
0 |
0 |
T7 |
128 |
127 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
127 |
0 |
0 |
T12 |
0 |
127 |
0 |
0 |
T24 |
0 |
1 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
3955 |
3450 |
0 |
0 |
T1 |
2 |
1 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
10 |
9 |
0 |
0 |
T5 |
10 |
9 |
0 |
0 |
T6 |
10 |
9 |
0 |
0 |
T7 |
59 |
58 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
58 |
0 |
0 |
T12 |
0 |
58 |
0 |
0 |
T24 |
0 |
1 |
0 |
0 |
T70 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_out_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_out_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_out_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
10955 |
10450 |
0 |
0 |
selKnown1 |
3955 |
3450 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
10955 |
10450 |
0 |
0 |
T1 |
2 |
1 |
0 |
0 |
T2 |
2 |
1 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
20 |
19 |
0 |
0 |
T5 |
20 |
19 |
0 |
0 |
T6 |
20 |
19 |
0 |
0 |
T7 |
128 |
127 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
127 |
0 |
0 |
T12 |
0 |
127 |
0 |
0 |
T24 |
0 |
1 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
3955 |
3450 |
0 |
0 |
T1 |
2 |
1 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
10 |
9 |
0 |
0 |
T5 |
10 |
9 |
0 |
0 |
T6 |
10 |
9 |
0 |
0 |
T7 |
59 |
58 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
58 |
0 |
0 |
T12 |
0 |
58 |
0 |
0 |
T24 |
0 |
1 |
0 |
0 |
T70 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.gen_rst_por_aon[1].gen_rst_por_domain.u_por_domain_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.gen_rst_por_aon[1].gen_rst_por_domain.u_por_domain_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.gen_rst_por_aon[1].gen_rst_por_domain.u_por_domain_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
10955 |
10450 |
0 |
0 |
selKnown1 |
3955 |
3450 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
10955 |
10450 |
0 |
0 |
T1 |
2 |
1 |
0 |
0 |
T2 |
2 |
1 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
20 |
19 |
0 |
0 |
T5 |
20 |
19 |
0 |
0 |
T6 |
20 |
19 |
0 |
0 |
T7 |
128 |
127 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
127 |
0 |
0 |
T12 |
0 |
127 |
0 |
0 |
T24 |
0 |
1 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
3955 |
3450 |
0 |
0 |
T1 |
2 |
1 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
10 |
9 |
0 |
0 |
T5 |
10 |
9 |
0 |
0 |
T6 |
10 |
9 |
0 |
0 |
T7 |
59 |
58 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
58 |
0 |
0 |
T12 |
0 |
58 |
0 |
0 |
T24 |
0 |
1 |
0 |
0 |
T70 |
0 |
1 |
0 |
0 |