Unified Coverage Report :: Module :: rstmgr_sw_rst_sva_if

Module : rstmgr_sw_rst_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_sw_rst_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_sw_rst_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_sw_rst_sva_if

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
21	8	8

---

Cond Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Covered	Percent
Conditions	24	24	100.00
Logical	24	24	100.00
Non-Logical	0	0
Event	0	0

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[0])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[1])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[2])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[3])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[4])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T7
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[5])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[6])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[7])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions[0].RstEnOff_A	20876770	18250	0	0
gen_assertions[0].RstEnOn_A	20876770	1550	0	0
gen_assertions[0].RstNOff_A	20876770	18250	0	0
gen_assertions[0].RstNOn_A	20876770	1550	0	0
gen_assertions[1].RstEnOff_A	83502355	16650	0	0
gen_assertions[1].RstEnOn_A	83502355	1550	0	0
gen_assertions[1].RstNOff_A	83502355	16650	0	0
gen_assertions[1].RstNOn_A	83502355	1550	0	0
gen_assertions[2].RstEnOff_A	41752770	16800	0	0
gen_assertions[2].RstEnOn_A	41752770	1650	0	0
gen_assertions[2].RstNOff_A	41752770	16800	0	0
gen_assertions[2].RstNOn_A	41752770	1650	0	0
gen_assertions[3].RstEnOff_A	41754345	16550	0	0
gen_assertions[3].RstEnOn_A	41754345	1400	0	0
gen_assertions[3].RstNOff_A	41754345	16550	0	0
gen_assertions[3].RstNOn_A	41754345	1400	0	0
gen_assertions[4].RstEnOff_A	2626665	28855	0	0
gen_assertions[4].RstEnOn_A	2626665	1800	0	0
gen_assertions[4].RstNOff_A	2626665	28855	0	0
gen_assertions[4].RstNOn_A	2626665	1800	0	0
gen_assertions[5].RstEnOff_A	20876770	18500	0	0
gen_assertions[5].RstEnOn_A	20876770	1700	0	0
gen_assertions[5].RstNOff_A	20876770	18500	0	0
gen_assertions[5].RstNOn_A	20876770	1700	0	0
gen_assertions[6].RstEnOff_A	20876770	18450	0	0
gen_assertions[6].RstEnOn_A	20876770	1650	0	0
gen_assertions[6].RstNOff_A	20876770	18450	0	0
gen_assertions[6].RstNOn_A	20876770	1650	0	0
gen_assertions[7].RstEnOff_A	20876770	18750	0	0
gen_assertions[7].RstEnOn_A	20876770	2050	0	0
gen_assertions[7].RstNOff_A	20876770	18750	0	0
gen_assertions[7].RstNOn_A	20876770	2050	0	0

gen_assertions[0].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20876770	18250	0	0
T1	5367	4	0	0
T2	5521	0	0	0
T3	5367	4	0	0
T4	41354	35	0	0
T5	41354	35	0	0
T6	41354	35	0	0
T7	264796	223	0	0
T8	11347	6	0	0
T9	11347	6	0	0
T10	11347	6	0	0
T23	0	6	0	0

gen_assertions[0].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20876770	1550	0	0
T7	264796	23	0	0
T8	11347	6	0	0
T9	11347	6	0	0
T10	11347	6	0	0
T11	264796	23	0	0
T12	264796	23	0	0
T13	5782	2	0	0
T23	11347	6	0	0
T37	0	2	0	0
T44	11347	6	0	0
T60	1888	0	0	0

gen_assertions[0].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20876770	18250	0	0
T1	5367	4	0	0
T2	5521	0	0	0
T3	5367	4	0	0
T4	41354	35	0	0
T5	41354	35	0	0
T6	41354	35	0	0
T7	264796	223	0	0
T8	11347	6	0	0
T9	11347	6	0	0
T10	11347	6	0	0
T23	0	6	0	0

gen_assertions[0].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20876770	1550	0	0
T7	264796	23	0	0
T8	11347	6	0	0
T9	11347	6	0	0
T10	11347	6	0	0
T11	264796	23	0	0
T12	264796	23	0	0
T13	5782	2	0	0
T23	11347	6	0	0
T37	0	2	0	0
T44	11347	6	0	0
T60	1888	0	0	0

gen_assertions[1].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	83502355	16650	0	0
T1	21473	4	0	0
T2	22092	0	0	0
T3	21473	4	0	0
T4	165425	31	0	0
T5	165425	31	0	0
T6	165425	31	0	0
T7	105906	205	0	0
T8	45395	8	0	0
T9	45395	8	0	0
T10	45395	8	0	0
T23	0	8	0	0

gen_assertions[1].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	83502355	1550	0	0
T7	105906	23	0	0
T8	45395	8	0	0
T9	45395	8	0	0
T10	45395	8	0	0
T11	105906	23	0	0
T12	105906	23	0	0
T13	23136	0	0	0
T23	45395	8	0	0
T41	0	8	0	0
T44	45395	8	0	0
T60	7560	0	0	0
T71	0	23	0	0

gen_assertions[1].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	83502355	16650	0	0
T1	21473	4	0	0
T2	22092	0	0	0
T3	21473	4	0	0
T4	165425	31	0	0
T5	165425	31	0	0
T6	165425	31	0	0
T7	105906	205	0	0
T8	45395	8	0	0
T9	45395	8	0	0
T10	45395	8	0	0
T23	0	8	0	0

gen_assertions[1].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	83502355	1550	0	0
T7	105906	23	0	0
T8	45395	8	0	0
T9	45395	8	0	0
T10	45395	8	0	0
T11	105906	23	0	0
T12	105906	23	0	0
T13	23136	0	0	0
T23	45395	8	0	0
T41	0	8	0	0
T44	45395	8	0	0
T60	7560	0	0	0
T71	0	23	0	0

gen_assertions[2].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	41752770	16800	0	0
T1	10735	4	0	0
T2	11046	0	0	0
T3	10735	4	0	0
T4	82708	31	0	0
T5	82708	31	0	0
T6	82708	31	0	0
T7	529561	207	0	0
T8	22698	9	0	0
T9	22698	9	0	0
T10	22698	9	0	0
T23	0	9	0	0

gen_assertions[2].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	41752770	1650	0	0
T7	529561	24	0	0
T8	22698	9	0	0
T9	22698	9	0	0
T10	22698	9	0	0
T11	529561	24	0	0
T12	529561	24	0	0
T13	11568	0	0	0
T23	22698	9	0	0
T41	0	9	0	0
T44	22698	9	0	0
T60	3780	0	0	0
T71	0	24	0	0

gen_assertions[2].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	41752770	16800	0	0
T1	10735	4	0	0
T2	11046	0	0	0
T3	10735	4	0	0
T4	82708	31	0	0
T5	82708	31	0	0
T6	82708	31	0	0
T7	529561	207	0	0
T8	22698	9	0	0
T9	22698	9	0	0
T10	22698	9	0	0
T23	0	9	0	0

gen_assertions[2].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	41752770	1650	0	0
T7	529561	24	0	0
T8	22698	9	0	0
T9	22698	9	0	0
T10	22698	9	0	0
T11	529561	24	0	0
T12	529561	24	0	0
T13	11568	0	0	0
T23	22698	9	0	0
T41	0	9	0	0
T44	22698	9	0	0
T60	3780	0	0	0
T71	0	24	0	0

gen_assertions[3].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	41754345	16550	0	0
T1	10735	4	0	0
T2	11046	0	0	0
T3	10735	4	0	0
T4	82715	31	0	0
T5	82715	31	0	0
T6	82715	31	0	0
T7	529588	203	0	0
T8	22698	8	0	0
T9	22698	8	0	0
T10	22698	8	0	0
T23	0	8	0	0

gen_assertions[3].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	41754345	1400	0	0
T7	529588	20	0	0
T8	22698	8	0	0
T9	22698	8	0	0
T10	22698	8	0	0
T11	529588	20	0	0
T12	529588	20	0	0
T13	11568	0	0	0
T23	22698	8	0	0
T41	0	8	0	0
T44	22698	8	0	0
T60	3780	0	0	0
T71	0	20	0	0

gen_assertions[3].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	41754345	16550	0	0
T1	10735	4	0	0
T2	11046	0	0	0
T3	10735	4	0	0
T4	82715	31	0	0
T5	82715	31	0	0
T6	82715	31	0	0
T7	529588	203	0	0
T8	22698	8	0	0
T9	22698	8	0	0
T10	22698	8	0	0
T23	0	8	0	0

gen_assertions[3].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	41754345	1400	0	0
T7	529588	20	0	0
T8	22698	8	0	0
T9	22698	8	0	0
T10	22698	8	0	0
T11	529588	20	0	0
T12	529588	20	0	0
T13	11568	0	0	0
T23	22698	8	0	0
T41	0	8	0	0
T44	22698	8	0	0
T60	3780	0	0	0
T71	0	20	0	0

gen_assertions[4].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2626665	28855	0	0
T1	671	7	0	0
T2	690	2	0	0
T3	671	7	0	0
T4	5189	55	0	0
T5	5189	55	0	0
T6	5189	55	0	0
T7	33393	348	0	0
T8	1418	13	0	0
T9	1418	13	0	0
T10	1418	13	0	0

gen_assertions[4].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2626665	1800	0	0
T1	671	1	0	0
T2	690	0	0	0
T3	671	1	0	0
T4	5189	0	0	0
T5	5189	0	0	0
T6	5189	0	0	0
T7	33393	23	0	0
T8	1418	12	0	0
T9	1418	12	0	0
T10	1418	12	0	0
T11	0	23	0	0
T12	0	23	0	0
T23	0	12	0	0
T44	0	12	0	0

gen_assertions[4].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2626665	28855	0	0
T1	671	7	0	0
T2	690	2	0	0
T3	671	7	0	0
T4	5189	55	0	0
T5	5189	55	0	0
T6	5189	55	0	0
T7	33393	348	0	0
T8	1418	13	0	0
T9	1418	13	0	0
T10	1418	13	0	0

gen_assertions[4].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2626665	1800	0	0
T1	671	1	0	0
T2	690	0	0	0
T3	671	1	0	0
T4	5189	0	0	0
T5	5189	0	0	0
T6	5189	0	0	0
T7	33393	23	0	0
T8	1418	12	0	0
T9	1418	12	0	0
T10	1418	12	0	0
T11	0	23	0	0
T12	0	23	0	0
T23	0	12	0	0
T44	0	12	0	0

gen_assertions[5].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20876770	18500	0	0
T1	5367	4	0	0
T2	5521	0	0	0
T3	5367	4	0	0
T4	41354	35	0	0
T5	41354	35	0	0
T6	41354	35	0	0
T7	264796	224	0	0
T8	11347	10	0	0
T9	11347	10	0	0
T10	11347	10	0	0
T23	0	10	0	0

gen_assertions[5].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20876770	1700	0	0
T7	264796	24	0	0
T8	11347	10	0	0
T9	11347	10	0	0
T10	11347	10	0	0
T11	264796	24	0	0
T12	264796	24	0	0
T13	5782	0	0	0
T23	11347	10	0	0
T41	0	10	0	0
T44	11347	10	0	0
T60	1888	0	0	0
T71	0	24	0	0

gen_assertions[5].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20876770	18500	0	0
T1	5367	4	0	0
T2	5521	0	0	0
T3	5367	4	0	0
T4	41354	35	0	0
T5	41354	35	0	0
T6	41354	35	0	0
T7	264796	224	0	0
T8	11347	10	0	0
T9	11347	10	0	0
T10	11347	10	0	0
T23	0	10	0	0

gen_assertions[5].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20876770	1700	0	0
T7	264796	24	0	0
T8	11347	10	0	0
T9	11347	10	0	0
T10	11347	10	0	0
T11	264796	24	0	0
T12	264796	24	0	0
T13	5782	0	0	0
T23	11347	10	0	0
T41	0	10	0	0
T44	11347	10	0	0
T60	1888	0	0	0
T71	0	24	0	0

gen_assertions[6].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20876770	18450	0	0
T1	5367	4	0	0
T2	5521	0	0	0
T3	5367	4	0	0
T4	41354	35	0	0
T5	41354	35	0	0
T6	41354	35	0	0
T7	264796	220	0	0
T8	11347	13	0	0
T9	11347	13	0	0
T10	11347	13	0	0
T23	0	13	0	0

gen_assertions[6].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20876770	1650	0	0
T7	264796	20	0	0
T8	11347	13	0	0
T9	11347	13	0	0
T10	11347	13	0	0
T11	264796	20	0	0
T12	264796	20	0	0
T13	5782	0	0	0
T23	11347	13	0	0
T41	0	13	0	0
T44	11347	13	0	0
T60	1888	0	0	0
T71	0	20	0	0

gen_assertions[6].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20876770	18450	0	0
T1	5367	4	0	0
T2	5521	0	0	0
T3	5367	4	0	0
T4	41354	35	0	0
T5	41354	35	0	0
T6	41354	35	0	0
T7	264796	220	0	0
T8	11347	13	0	0
T9	11347	13	0	0
T10	11347	13	0	0
T23	0	13	0	0

gen_assertions[6].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20876770	1650	0	0
T7	264796	20	0	0
T8	11347	13	0	0
T9	11347	13	0	0
T10	11347	13	0	0
T11	264796	20	0	0
T12	264796	20	0	0
T13	5782	0	0	0
T23	11347	13	0	0
T41	0	13	0	0
T44	11347	13	0	0
T60	1888	0	0	0
T71	0	20	0	0

gen_assertions[7].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20876770	18750	0	0
T1	5367	4	0	0
T2	5521	0	0	0
T3	5367	4	0	0
T4	41354	35	0	0
T5	41354	35	0	0
T6	41354	35	0	0
T7	264796	225	0	0
T8	11347	14	0	0
T9	11347	14	0	0
T10	11347	14	0	0
T23	0	14	0	0

gen_assertions[7].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20876770	2050	0	0
T7	264796	27	0	0
T8	11347	14	0	0
T9	11347	14	0	0
T10	11347	14	0	0
T11	264796	27	0	0
T12	264796	27	0	0
T13	5782	0	0	0
T23	11347	14	0	0
T41	0	14	0	0
T44	11347	14	0	0
T60	1888	0	0	0
T71	0	27	0	0

gen_assertions[7].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20876770	18750	0	0
T1	5367	4	0	0
T2	5521	0	0	0
T3	5367	4	0	0
T4	41354	35	0	0
T5	41354	35	0	0
T6	41354	35	0	0
T7	264796	225	0	0
T8	11347	14	0	0
T9	11347	14	0	0
T10	11347	14	0	0
T23	0	14	0	0

gen_assertions[7].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20876770	2050	0	0
T7	264796	27	0	0
T8	11347	14	0	0
T9	11347	14	0	0
T10	11347	14	0	0
T11	264796	27	0	0
T12	264796	27	0	0
T13	5782	0	0	0
T23	11347	14	0	0
T41	0	14	0	0
T44	11347	14	0	0
T60	1888	0	0	0
T71	0	27	0	0