Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : prim_mubi4_sender
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_daon_por.u_prim_mubi4_sender 100.00 100.00 100.00
tb.dut.u_daon_por_io.u_prim_mubi4_sender 100.00 100.00 100.00
tb.dut.u_daon_por_io_div2.u_prim_mubi4_sender 100.00 100.00 100.00
tb.dut.u_daon_por_io_div4.u_prim_mubi4_sender 100.00 100.00 100.00
tb.dut.u_daon_por_usb.u_prim_mubi4_sender 100.00 100.00 100.00
tb.dut.u_daon_lc.u_prim_mubi4_sender 100.00 100.00 100.00
tb.dut.u_d0_lc.u_prim_mubi4_sender 100.00 100.00 100.00
tb.dut.u_daon_lc_shadowed.u_prim_mubi4_sender 100.00 100.00 100.00
tb.dut.u_d0_lc_shadowed.u_prim_mubi4_sender 100.00 100.00 100.00
tb.dut.u_daon_lc_aon.u_prim_mubi4_sender 100.00 100.00 100.00
tb.dut.u_daon_lc_io.u_prim_mubi4_sender 100.00 100.00 100.00
tb.dut.u_d0_lc_io.u_prim_mubi4_sender 100.00 100.00 100.00
tb.dut.u_daon_lc_io_div2.u_prim_mubi4_sender 100.00 100.00 100.00
tb.dut.u_d0_lc_io_div2.u_prim_mubi4_sender 100.00 100.00 100.00
tb.dut.u_daon_lc_io_div4.u_prim_mubi4_sender 100.00 100.00 100.00
tb.dut.u_d0_lc_io_div4.u_prim_mubi4_sender 100.00 100.00 100.00
tb.dut.u_daon_lc_io_div4_shadowed.u_prim_mubi4_sender 100.00 100.00 100.00
tb.dut.u_d0_lc_io_div4_shadowed.u_prim_mubi4_sender 100.00 100.00 100.00
tb.dut.u_daon_lc_usb.u_prim_mubi4_sender 100.00 100.00 100.00
tb.dut.u_d0_lc_usb.u_prim_mubi4_sender 100.00 100.00 100.00
tb.dut.u_d0_sys.u_prim_mubi4_sender 100.00 100.00 100.00
tb.dut.u_daon_sys_io_div4.u_prim_mubi4_sender 100.00 100.00 100.00
tb.dut.u_d0_spi_device.u_prim_mubi4_sender 100.00 100.00 100.00
tb.dut.u_d0_spi_host0.u_prim_mubi4_sender 100.00 100.00 100.00
tb.dut.u_d0_spi_host1.u_prim_mubi4_sender 100.00 100.00 100.00
tb.dut.u_d0_usb.u_prim_mubi4_sender 100.00 100.00 100.00
tb.dut.u_d0_usb_aon.u_prim_mubi4_sender 100.00 100.00 100.00
tb.dut.u_d0_i2c0.u_prim_mubi4_sender 100.00 100.00 100.00
tb.dut.u_d0_i2c1.u_prim_mubi4_sender 100.00 100.00 100.00
tb.dut.u_d0_i2c2.u_prim_mubi4_sender 100.00 100.00 100.00
tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_prim_mubi4_sender 100.00 100.00 100.00
tb.dut.gen_rst_por_aon[1].gen_rst_por_domain.u_prim_mubi4_sender 100.00 100.00 100.00



Module Instance : tb.dut.u_daon_por.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_daon_por


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_daon_por_io.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_daon_por_io


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_daon_por_io_div2.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_daon_por_io_div2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_daon_por_io_div4.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_daon_por_io_div4


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_daon_por_usb.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_daon_por_usb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_daon_lc.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_daon_lc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_d0_lc.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_d0_lc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_daon_lc_shadowed.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_daon_lc_shadowed


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_d0_lc_shadowed.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_d0_lc_shadowed


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_daon_lc_aon.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_daon_lc_aon


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_daon_lc_io.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_daon_lc_io


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_d0_lc_io.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_d0_lc_io


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_daon_lc_io_div2.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_daon_lc_io_div2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_d0_lc_io_div2.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_d0_lc_io_div2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_daon_lc_io_div4.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_daon_lc_io_div4


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_d0_lc_io_div4.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_d0_lc_io_div4


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_daon_lc_io_div4_shadowed.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_daon_lc_io_div4_shadowed


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_d0_lc_io_div4_shadowed.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_d0_lc_io_div4_shadowed


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_daon_lc_usb.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_daon_lc_usb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_d0_lc_usb.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_d0_lc_usb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_d0_sys.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_d0_sys


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_daon_sys_io_div4.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_daon_sys_io_div4


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_d0_spi_device.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.67 100.00 90.00 100.00 u_d0_spi_device


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_d0_spi_host0.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.67 100.00 90.00 100.00 u_d0_spi_host0


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_d0_spi_host1.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.67 100.00 90.00 100.00 u_d0_spi_host1


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_d0_usb.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.67 100.00 90.00 100.00 u_d0_usb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_d0_usb_aon.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.67 100.00 90.00 100.00 u_d0_usb_aon


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_d0_i2c0.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.67 100.00 90.00 100.00 u_d0_i2c0


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_d0_i2c1.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.67 100.00 90.00 100.00 u_d0_i2c1


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_d0_i2c2.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.67 100.00 90.00 100.00 u_d0_i2c2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.55 100.00 98.21 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.gen_rst_por_aon[1].gen_rst_por_domain.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.55 100.00 98.21 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00

Line Coverage for Module : prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 unreachable
82 1 1
85 1 1


Assert Coverage for Module : prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 1409217380 901181535 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1409217380 901181535 0 0
T1 362304 282892 0 0
T2 372784 71187 0 0
T3 362304 282892 0 0
T4 2791584 1867048 0 0
T5 2791584 1867048 0 0
T6 2791584 1867048 0 0
T7 8103678 12166659 0 0
T8 766040 704171 0 0
T9 766040 704171 0 0
T10 766040 704171 0 0

Line Coverage for Instance : tb.dut.u_daon_por.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 unreachable
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_daon_por.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 86984190 60610260 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 86984190 60610260 0 0
T1 22363 18366 0 0
T2 23013 5040 0 0
T3 22363 18366 0 0
T4 172316 127894 0 0
T5 172316 127894 0 0
T6 172316 127894 0 0
T7 110321 820100 0 0
T8 47289 44617 0 0
T9 47289 44617 0 0
T10 47289 44617 0 0

Line Coverage for Instance : tb.dut.u_daon_por_io.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 unreachable
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_daon_por_io.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 83502355 58184630 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 83502355 58184630 0 0
T1 21473 17636 0 0
T2 22092 4839 0 0
T3 21473 17636 0 0
T4 165425 122772 0 0
T5 165425 122772 0 0
T6 165425 122772 0 0
T7 105906 787275 0 0
T8 45395 42830 0 0
T9 45395 42830 0 0
T10 45395 42830 0 0

Line Coverage for Instance : tb.dut.u_daon_por_io_div2.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 unreachable
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_daon_por_io_div2.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 41752770 29088175 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 41752770 29088175 0 0
T1 10735 8817 0 0
T2 11046 2419 0 0
T3 10735 8817 0 0
T4 82708 61379 0 0
T5 82708 61379 0 0
T6 82708 61379 0 0
T7 529561 393598 0 0
T8 22698 21416 0 0
T9 22698 21416 0 0
T10 22698 21416 0 0

Line Coverage for Instance : tb.dut.u_daon_por_io_div4.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 unreachable
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_daon_por_io_div4.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 20876770 14538100 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 20876770 14538100 0 0
T1 5367 4409 0 0
T2 5521 1208 0 0
T3 5367 4409 0 0
T4 41354 30678 0 0
T5 41354 30678 0 0
T6 41354 30678 0 0
T7 264796 196734 0 0
T8 11347 10707 0 0
T9 11347 10707 0 0
T10 11347 10707 0 0

Line Coverage for Instance : tb.dut.u_daon_por_usb.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 unreachable
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_daon_por_usb.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 41754345 29090275 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 41754345 29090275 0 0
T1 10735 8817 0 0
T2 11046 2419 0 0
T3 10735 8817 0 0
T4 82715 61381 0 0
T5 82715 61381 0 0
T6 82715 61381 0 0
T7 529588 393597 0 0
T8 22698 21416 0 0
T9 22698 21416 0 0
T10 22698 21416 0 0

Line Coverage for Instance : tb.dut.u_daon_lc.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 unreachable
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_daon_lc.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 86984190 55396825 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 86984190 55396825 0 0
T1 22363 17363 0 0
T2 23013 5029 0 0
T3 22363 17363 0 0
T4 172316 113302 0 0
T5 172316 113302 0 0
T6 172316 113302 0 0
T7 110321 746625 0 0
T8 47289 44612 0 0
T9 47289 44612 0 0
T10 47289 44612 0 0

Line Coverage for Instance : tb.dut.u_d0_lc.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 unreachable
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_d0_lc.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 86984190 54470215 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 86984190 54470215 0 0
T1 22363 17195 0 0
T2 23013 3796 0 0
T3 22363 17195 0 0
T4 172316 111678 0 0
T5 172316 111678 0 0
T6 172316 111678 0 0
T7 110321 736415 0 0
T8 47289 44545 0 0
T9 47289 44545 0 0
T10 47289 44545 0 0

Line Coverage for Instance : tb.dut.u_daon_lc_shadowed.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 unreachable
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_daon_lc_shadowed.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 86984190 55394575 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 86984190 55394575 0 0
T1 22363 17363 0 0
T2 23013 5029 0 0
T3 22363 17363 0 0
T4 172316 113302 0 0
T5 172316 113302 0 0
T6 172316 113302 0 0
T7 110321 746625 0 0
T8 47289 44612 0 0
T9 47289 44612 0 0
T10 47289 44612 0 0

Line Coverage for Instance : tb.dut.u_d0_lc_shadowed.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 unreachable
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_d0_lc_shadowed.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 86984190 54473165 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 86984190 54473165 0 0
T1 22363 17195 0 0
T2 23013 3796 0 0
T3 22363 17195 0 0
T4 172316 111678 0 0
T5 172316 111678 0 0
T6 172316 111678 0 0
T7 110321 736415 0 0
T8 47289 44545 0 0
T9 47289 44545 0 0
T10 47289 44545 0 0

Line Coverage for Instance : tb.dut.u_daon_lc_aon.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 unreachable
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_daon_lc_aon.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 2626665 1645610 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2626665 1645610 0 0
T1 671 514 0 0
T2 690 149 0 0
T3 671 514 0 0
T4 5189 3354 0 0
T5 5189 3354 0 0
T6 5189 3354 0 0
T7 33393 22310 0 0
T8 1418 1337 0 0
T9 1418 1337 0 0
T10 1418 1337 0 0

Line Coverage for Instance : tb.dut.u_daon_lc_io.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 unreachable
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_daon_lc_io.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 83502355 53177850 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 83502355 53177850 0 0
T1 21473 16670 0 0
T2 22092 4828 0 0
T3 21473 16670 0 0
T4 165425 108766 0 0
T5 165425 108766 0 0
T6 165425 108766 0 0
T7 105906 716737 0 0
T8 45395 42825 0 0
T9 45395 42825 0 0
T10 45395 42825 0 0

Line Coverage for Instance : tb.dut.u_d0_lc_io.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 unreachable
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_d0_lc_io.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 83502355 52290935 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 83502355 52290935 0 0
T1 21473 16510 0 0
T2 22092 3644 0 0
T3 21473 16510 0 0
T4 165425 107206 0 0
T5 165425 107206 0 0
T6 165425 107206 0 0
T7 105906 706929 0 0
T8 45395 42761 0 0
T9 45395 42761 0 0
T10 45395 42761 0 0

Line Coverage for Instance : tb.dut.u_daon_lc_io_div2.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 unreachable
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_daon_lc_io_div2.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 41752770 26577900 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 41752770 26577900 0 0
T1 10735 8331 0 0
T2 11046 2413 0 0
T3 10735 8331 0 0
T4 82708 54356 0 0
T5 82708 54356 0 0
T6 82708 54356 0 0
T7 529561 358225 0 0
T8 22698 21413 0 0
T9 22698 21413 0 0
T10 22698 21413 0 0

Line Coverage for Instance : tb.dut.u_d0_lc_io_div2.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 unreachable
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_d0_lc_io_div2.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 41752770 26133340 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 41752770 26133340 0 0
T1 10735 8251 0 0
T2 11046 1821 0 0
T3 10735 8251 0 0
T4 82708 53576 0 0
T5 82708 53576 0 0
T6 82708 53576 0 0
T7 529561 353321 0 0
T8 22698 21381 0 0
T9 22698 21381 0 0
T10 22698 21381 0 0

Line Coverage for Instance : tb.dut.u_daon_lc_io_div4.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 unreachable
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_daon_lc_io_div4.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 20876770 13250940 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 20876770 13250940 0 0
T1 5367 4159 0 0
T2 5521 1204 0 0
T3 5367 4159 0 0
T4 41354 27106 0 0
T5 41354 27106 0 0
T6 41354 27106 0 0
T7 264796 178682 0 0
T8 11347 10705 0 0
T9 11347 10705 0 0
T10 11347 10705 0 0

Line Coverage for Instance : tb.dut.u_d0_lc_io_div4.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 unreachable
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_d0_lc_io_div4.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 20876770 13028660 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 20876770 13028660 0 0
T1 5367 4119 0 0
T2 5521 908 0 0
T3 5367 4119 0 0
T4 41354 26716 0 0
T5 41354 26716 0 0
T6 41354 26716 0 0
T7 264796 176230 0 0
T8 11347 10689 0 0
T9 11347 10689 0 0
T10 11347 10689 0 0

Line Coverage for Instance : tb.dut.u_daon_lc_io_div4_shadowed.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 unreachable
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_daon_lc_io_div4_shadowed.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 20876770 13250940 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 20876770 13250940 0 0
T1 5367 4159 0 0
T2 5521 1204 0 0
T3 5367 4159 0 0
T4 41354 27106 0 0
T5 41354 27106 0 0
T6 41354 27106 0 0
T7 264796 178682 0 0
T8 11347 10705 0 0
T9 11347 10705 0 0
T10 11347 10705 0 0

Line Coverage for Instance : tb.dut.u_d0_lc_io_div4_shadowed.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 unreachable
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_d0_lc_io_div4_shadowed.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 20876770 13028660 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 20876770 13028660 0 0
T1 5367 4119 0 0
T2 5521 908 0 0
T3 5367 4119 0 0
T4 41354 26716 0 0
T5 41354 26716 0 0
T6 41354 26716 0 0
T7 264796 176230 0 0
T8 11347 10689 0 0
T9 11347 10689 0 0
T10 11347 10689 0 0

Line Coverage for Instance : tb.dut.u_daon_lc_usb.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 unreachable
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_daon_lc_usb.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 41754345 26578050 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 41754345 26578050 0 0
T1 10735 8332 0 0
T2 11046 2413 0 0
T3 10735 8332 0 0
T4 82715 54358 0 0
T5 82715 54358 0 0
T6 82715 54358 0 0
T7 529588 358222 0 0
T8 22698 21413 0 0
T9 22698 21413 0 0
T10 22698 21413 0 0

Line Coverage for Instance : tb.dut.u_d0_lc_usb.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 unreachable
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_d0_lc_usb.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 41754345 26133490 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 41754345 26133490 0 0
T1 10735 8252 0 0
T2 11046 1821 0 0
T3 10735 8252 0 0
T4 82715 53578 0 0
T5 82715 53578 0 0
T6 82715 53578 0 0
T7 529588 353318 0 0
T8 22698 21381 0 0
T9 22698 21381 0 0
T10 22698 21381 0 0

Line Coverage for Instance : tb.dut.u_d0_sys.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 unreachable
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_d0_sys.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 86984190 54082115 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 86984190 54082115 0 0
T1 22363 17095 0 0
T2 23013 3796 0 0
T3 22363 17095 0 0
T4 172316 110991 0 0
T5 172316 110991 0 0
T6 172316 110991 0 0
T7 110321 731590 0 0
T8 47289 44545 0 0
T9 47289 44545 0 0
T10 47289 44545 0 0

Line Coverage for Instance : tb.dut.u_daon_sys_io_div4.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 unreachable
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_daon_sys_io_div4.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 20876770 13156790 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 20876770 13156790 0 0
T1 5367 4135 0 0
T2 5521 1204 0 0
T3 5367 4135 0 0
T4 41354 26942 0 0
T5 41354 26942 0 0
T6 41354 26942 0 0
T7 264796 177526 0 0
T8 11347 10705 0 0
T9 11347 10705 0 0
T10 11347 10705 0 0

Line Coverage for Instance : tb.dut.u_d0_spi_device.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 unreachable
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_d0_spi_device.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 20876770 12665310 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 20876770 12665310 0 0
T1 5367 4119 0 0
T2 5521 908 0 0
T3 5367 4119 0 0
T4 41354 26716 0 0
T5 41354 26716 0 0
T6 41354 26716 0 0
T7 264796 170190 0 0
T8 11347 9470 0 0
T9 11347 9470 0 0
T10 11347 9470 0 0

Line Coverage for Instance : tb.dut.u_d0_spi_host0.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 unreachable
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_d0_spi_host0.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 83502355 50801835 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 83502355 50801835 0 0
T1 21473 16510 0 0
T2 22092 3644 0 0
T3 21473 16510 0 0
T4 165425 107206 0 0
T5 165425 107206 0 0
T6 165425 107206 0 0
T7 105906 683094 0 0
T8 45395 36814 0 0
T9 45395 36814 0 0
T10 45395 36814 0 0

Line Coverage for Instance : tb.dut.u_d0_spi_host1.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 unreachable
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_d0_spi_host1.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 41752770 25406740 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 41752770 25406740 0 0
T1 10735 8251 0 0
T2 11046 1821 0 0
T3 10735 8251 0 0
T4 82708 53576 0 0
T5 82708 53576 0 0
T6 82708 53576 0 0
T7 529561 341983 0 0
T8 22698 18187 0 0
T9 22698 18187 0 0
T10 22698 18187 0 0

Line Coverage for Instance : tb.dut.u_d0_usb.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 unreachable
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_d0_usb.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 41754345 25531790 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 41754345 25531790 0 0
T1 10735 8252 0 0
T2 11046 1821 0 0
T3 10735 8252 0 0
T4 82715 53578 0 0
T5 82715 53578 0 0
T6 82715 53578 0 0
T7 529588 343920 0 0
T8 22698 18777 0 0
T9 22698 18777 0 0
T10 22698 18777 0 0

Line Coverage for Instance : tb.dut.u_d0_usb_aon.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 unreachable
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_d0_usb_aon.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 2626665 1570850 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2626665 1570850 0 0
T1 671 494 0 0
T2 690 112 0 0
T3 671 494 0 0
T4 5189 3303 0 0
T5 5189 3303 0 0
T6 5189 3303 0 0
T7 33393 21307 0 0
T8 1418 1103 0 0
T9 1418 1103 0 0
T10 1418 1103 0 0

Line Coverage for Instance : tb.dut.u_d0_i2c0.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 unreachable
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_d0_i2c0.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 20876770 12649160 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 20876770 12649160 0 0
T1 5367 4119 0 0
T2 5521 908 0 0
T3 5367 4119 0 0
T4 41354 26716 0 0
T5 41354 26716 0 0
T6 41354 26716 0 0
T7 264796 170234 0 0
T8 11347 9100 0 0
T9 11347 9100 0 0
T10 11347 9100 0 0

Line Coverage for Instance : tb.dut.u_d0_i2c1.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 unreachable
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_d0_i2c1.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 20876770 12712060 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 20876770 12712060 0 0
T1 5367 4119 0 0
T2 5521 908 0 0
T3 5367 4119 0 0
T4 41354 26716 0 0
T5 41354 26716 0 0
T6 41354 26716 0 0
T7 264796 171526 0 0
T8 11347 9067 0 0
T9 11347 9067 0 0
T10 11347 9067 0 0

Line Coverage for Instance : tb.dut.u_d0_i2c2.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 unreachable
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_d0_i2c2.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 20876770 12608710 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 20876770 12608710 0 0
T1 5367 4119 0 0
T2 5521 908 0 0
T3 5367 4119 0 0
T4 41354 26716 0 0
T5 41354 26716 0 0
T6 41354 26716 0 0
T7 264796 169395 0 0
T8 11347 9128 0 0
T9 11347 9128 0 0
T10 11347 9128 0 0

Line Coverage for Instance : tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 unreachable
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 2626665 1838570 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2626665 1838570 0 0
T1 671 553 0 0
T2 690 153 0 0
T3 671 553 0 0
T4 5189 3863 0 0
T5 5189 3863 0 0
T6 5189 3863 0 0
T7 33393 24940 0 0
T8 1418 1339 0 0
T9 1418 1339 0 0
T10 1418 1339 0 0

Line Coverage for Instance : tb.dut.gen_rst_por_aon[1].gen_rst_por_domain.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 unreachable
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.gen_rst_por_aon[1].gen_rst_por_domain.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 2626665 1815010 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2626665 1815010 0 0
T1 671 549 0 0
T2 690 116 0 0
T3 671 549 0 0
T4 5189 3823 0 0
T5 5189 3823 0 0
T6 5189 3823 0 0
T7 33393 24684 0 0
T8 1418 1337 0 0
T9 1418 1337 0 0
T10 1418 1337 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%