Unified Coverage Report :: Module :: rstmgr_csr_assert_fpv

Module : rstmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rstmgr_csr_assert_0/rstmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rstmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rstmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	19487580	6120	0	0
alert_regwen_rd_A	19487580	15255	0	0
cpu_regwen_rd_A	19487580	14055	0	0
sw_rst_ctrl_n_0_rd_A	19487580	29520	0	0
sw_rst_ctrl_n_1_rd_A	19487580	31610	0	0
sw_rst_ctrl_n_2_rd_A	19487580	30085	0	0
sw_rst_ctrl_n_3_rd_A	19487580	29865	0	0
sw_rst_ctrl_n_4_rd_A	19487580	32060	0	0
sw_rst_ctrl_n_5_rd_A	19487580	26810	0	0
sw_rst_ctrl_n_6_rd_A	19487580	26735	0	0
sw_rst_ctrl_n_7_rd_A	19487580	28375	0	0
sw_rst_regwen_0_rd_A	19487580	13745	0	0
sw_rst_regwen_1_rd_A	19487580	14535	0	0
sw_rst_regwen_2_rd_A	19487580	11880	0	0
sw_rst_regwen_3_rd_A	19487580	15240	0	0
sw_rst_regwen_4_rd_A	19487580	17375	0	0
sw_rst_regwen_5_rd_A	19487580	12540	0	0
sw_rst_regwen_6_rd_A	19487580	13785	0	0
sw_rst_regwen_7_rd_A	19487580	13170	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19487580	6120	0	0
T45	2455	5	0	0
T49	2455	5	0	0
T50	2455	5	0	0
T51	7924	301	0	0
T52	7924	301	0	0
T55	7924	301	0	0
T59	3482	0	0	0
T72	7924	301	0	0
T82	0	5	0	0
T90	2455	5	0	0
T91	2455	5	0	0

alert_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19487580	15255	0	0
T4	35870	52	0	0
T5	35870	52	0	0
T6	35870	52	0	0
T7	235091	225	0	0
T8	11330	0	0	0
T9	11330	0	0	0
T10	11330	0	0	0
T11	235091	225	0	0
T12	0	225	0	0
T23	11330	0	0	0
T38	0	52	0	0
T39	0	52	0	0
T43	0	52	0	0
T44	11330	0	0	0
T77	0	52	0	0

cpu_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19487580	14055	0	0
T4	35870	41	0	0
T5	35870	41	0	0
T6	35870	41	0	0
T7	235091	205	0	0
T8	11330	0	0	0
T9	11330	0	0	0
T10	11330	0	0	0
T11	235091	205	0	0
T12	0	205	0	0
T23	11330	0	0	0
T38	0	41	0	0
T39	0	41	0	0
T43	0	41	0	0
T44	11330	0	0	0
T77	0	41	0	0

sw_rst_ctrl_n_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19487580	29520	0	0
T1	5127	12	0	0
T2	5480	0	0	0
T3	5127	12	0	0
T4	35870	14	0	0
T5	35870	14	0	0
T6	35870	14	0	0
T7	235091	408	0	0
T8	11330	116	0	0
T9	11330	116	0	0
T10	11330	116	0	0
T23	0	116	0	0

sw_rst_ctrl_n_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19487580	31610	0	0
T1	5127	9	0	0
T2	5480	0	0	0
T3	5127	9	0	0
T4	35870	37	0	0
T5	35870	37	0	0
T6	35870	37	0	0
T7	235091	451	0	0
T8	11330	102	0	0
T9	11330	102	0	0
T10	11330	102	0	0
T23	0	102	0	0

sw_rst_ctrl_n_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19487580	30085	0	0
T1	5127	7	0	0
T2	5480	0	0	0
T3	5127	7	0	0
T4	35870	27	0	0
T5	35870	27	0	0
T6	35870	27	0	0
T7	235091	405	0	0
T8	11330	119	0	0
T9	11330	119	0	0
T10	11330	119	0	0
T23	0	119	0	0

sw_rst_ctrl_n_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19487580	29865	0	0
T1	5127	5	0	0
T2	5480	0	0	0
T3	5127	5	0	0
T4	35870	29	0	0
T5	35870	29	0	0
T6	35870	29	0	0
T7	235091	384	0	0
T8	11330	134	0	0
T9	11330	134	0	0
T10	11330	134	0	0
T23	0	134	0	0

sw_rst_ctrl_n_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19487580	32060	0	0
T1	5127	14	0	0
T2	5480	0	0	0
T3	5127	14	0	0
T4	35870	30	0	0
T5	35870	30	0	0
T6	35870	30	0	0
T7	235091	386	0	0
T8	11330	151	0	0
T9	11330	151	0	0
T10	11330	151	0	0
T23	0	151	0	0

sw_rst_ctrl_n_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19487580	26810	0	0
T1	5127	4	0	0
T2	5480	0	0	0
T3	5127	4	0	0
T4	35870	12	0	0
T5	35870	12	0	0
T6	35870	12	0	0
T7	235091	343	0	0
T8	11330	134	0	0
T9	11330	134	0	0
T10	11330	134	0	0
T23	0	134	0	0

sw_rst_ctrl_n_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19487580	26735	0	0
T4	35870	30	0	0
T5	35870	30	0	0
T6	35870	30	0	0
T7	235091	335	0	0
T8	11330	123	0	0
T9	11330	123	0	0
T10	11330	123	0	0
T11	235091	335	0	0
T23	11330	123	0	0
T44	11330	123	0	0

sw_rst_ctrl_n_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19487580	28375	0	0
T1	5127	10	0	0
T2	5480	0	0	0
T3	5127	10	0	0
T4	35870	31	0	0
T5	35870	31	0	0
T6	35870	31	0	0
T7	235091	387	0	0
T8	11330	90	0	0
T9	11330	90	0	0
T10	11330	90	0	0
T23	0	90	0	0

sw_rst_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19487580	13745	0	0
T1	5127	5	0	0
T2	5480	0	0	0
T3	5127	5	0	0
T4	35870	25	0	0
T5	35870	25	0	0
T6	35870	25	0	0
T7	235091	196	0	0
T8	11330	17	0	0
T9	11330	17	0	0
T10	11330	17	0	0
T23	0	17	0	0

sw_rst_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19487580	14535	0	0
T4	35870	55	0	0
T5	35870	55	0	0
T6	35870	55	0	0
T7	235091	195	0	0
T8	11330	11	0	0
T9	11330	11	0	0
T10	11330	11	0	0
T11	235091	195	0	0
T23	11330	11	0	0
T44	11330	11	0	0

sw_rst_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19487580	11880	0	0
T4	35870	48	0	0
T5	35870	48	0	0
T6	35870	48	0	0
T7	235091	155	0	0
T8	11330	4	0	0
T9	11330	4	0	0
T10	11330	4	0	0
T11	235091	155	0	0
T23	11330	4	0	0
T44	11330	4	0	0

sw_rst_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19487580	15240	0	0
T1	5127	3	0	0
T2	5480	0	0	0
T3	5127	3	0	0
T4	35870	31	0	0
T5	35870	31	0	0
T6	35870	31	0	0
T7	235091	204	0	0
T8	11330	17	0	0
T9	11330	17	0	0
T10	11330	17	0	0
T23	0	17	0	0

sw_rst_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19487580	17375	0	0
T4	35870	33	0	0
T5	35870	33	0	0
T6	35870	33	0	0
T7	235091	263	0	0
T8	11330	18	0	0
T9	11330	18	0	0
T10	11330	18	0	0
T11	235091	263	0	0
T23	11330	18	0	0
T44	11330	18	0	0

sw_rst_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19487580	12540	0	0
T4	35870	34	0	0
T5	35870	34	0	0
T6	35870	34	0	0
T7	235091	172	0	0
T8	11330	8	0	0
T9	11330	8	0	0
T10	11330	8	0	0
T11	235091	172	0	0
T23	11330	8	0	0
T44	11330	8	0	0

sw_rst_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19487580	13785	0	0
T1	5127	4	0	0
T2	5480	0	0	0
T3	5127	4	0	0
T4	35870	22	0	0
T5	35870	22	0	0
T6	35870	22	0	0
T7	235091	179	0	0
T8	11330	26	0	0
T9	11330	26	0	0
T10	11330	26	0	0
T23	0	26	0	0

sw_rst_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19487580	13170	0	0
T4	35870	27	0	0
T5	35870	27	0	0
T6	35870	27	0	0
T7	235091	191	0	0
T8	11330	12	0	0
T9	11330	12	0	0
T10	11330	12	0	0
T11	235091	191	0	0
T23	11330	12	0	0
T44	11330	12	0	0