Unified Coverage Report :: Module :: pwrmgr_rstmgr_sva_if

Module : pwrmgr_rstmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_rstmgr_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_rstmgr_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_rstmgr_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	33	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' or '../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
33	1	1

---

Cond Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions_per_power_domains[0].LcHandshakeOff_A	18804095	16900	0	0
gen_assertions_per_power_domains[0].LcHandshakeOn_A	18804095	156650	0	0
gen_assertions_per_power_domains[0].SysHandshakeOff_A	18804095	13040390	0	0
gen_assertions_per_power_domains[0].SysHandshakeOn_A	18804095	250350	0	0
gen_assertions_per_power_domains[1].LcHandshakeOff_A	18804095	16900	0	0
gen_assertions_per_power_domains[1].LcHandshakeOn_A	18804095	156650	0	0
gen_assertions_per_power_domains[1].SysHandshakeOff_A	18804095	13040390	0	0
gen_assertions_per_power_domains[1].SysHandshakeOn_A	18804095	250350	0	0

gen_assertions_per_power_domains[0].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18804095	16900	0	0
T1	5127	4	0	0
T2	5480	0	0	0
T3	5127	4	0	0
T4	35870	35	0	0
T5	35870	35	0	0
T6	35870	35	0	0
T7	235091	202	0	0
T8	11330	0	0	0
T9	11330	0	0	0
T10	11330	0	0	0
T11	0	202	0	0
T12	0	202	0	0
T13	0	18	0	0
T24	0	4	0	0

gen_assertions_per_power_domains[0].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18804095	156650	0	0
T1	5127	38	0	0
T2	5480	0	0	0
T3	5127	38	0	0
T4	35870	317	0	0
T5	35870	317	0	0
T6	35870	317	0	0
T7	235091	1856	0	0
T8	11330	0	0	0
T9	11330	0	0	0
T10	11330	0	0	0
T11	0	1856	0	0
T12	0	1856	0	0
T13	0	162	0	0
T24	0	37	0	0

gen_assertions_per_power_domains[0].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18804095	13040390	0	0
T1	5127	4118	0	0
T2	5480	914	0	0
T3	5127	4118	0	0
T4	35870	26758	0	0
T5	35870	26758	0	0
T6	35870	26758	0	0
T7	235091	176309	0	0
T8	11330	10692	0	0
T9	11330	10692	0	0
T10	11330	10692	0	0

gen_assertions_per_power_domains[0].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18804095	250350	0	0
T1	5127	62	0	0
T2	5480	0	0	0
T3	5127	62	0	0
T4	35870	481	0	0
T5	35870	481	0	0
T6	35870	481	0	0
T7	235091	3012	0	0
T8	11330	0	0	0
T9	11330	0	0	0
T10	11330	0	0	0
T11	0	3012	0	0
T12	0	3012	0	0
T13	0	245	0	0
T24	0	48	0	0

gen_assertions_per_power_domains[1].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18804095	16900	0	0
T1	5127	4	0	0
T2	5480	0	0	0
T3	5127	4	0	0
T4	35870	35	0	0
T5	35870	35	0	0
T6	35870	35	0	0
T7	235091	202	0	0
T8	11330	0	0	0
T9	11330	0	0	0
T10	11330	0	0	0
T11	0	202	0	0
T12	0	202	0	0
T13	0	18	0	0
T24	0	4	0	0

gen_assertions_per_power_domains[1].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18804095	156650	0	0
T1	5127	38	0	0
T2	5480	0	0	0
T3	5127	38	0	0
T4	35870	317	0	0
T5	35870	317	0	0
T6	35870	317	0	0
T7	235091	1856	0	0
T8	11330	0	0	0
T9	11330	0	0	0
T10	11330	0	0	0
T11	0	1856	0	0
T12	0	1856	0	0
T13	0	162	0	0
T24	0	37	0	0

gen_assertions_per_power_domains[1].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18804095	13040390	0	0
T1	5127	4118	0	0
T2	5480	914	0	0
T3	5127	4118	0	0
T4	35870	26758	0	0
T5	35870	26758	0	0
T6	35870	26758	0	0
T7	235091	176309	0	0
T8	11330	10692	0	0
T9	11330	10692	0	0
T10	11330	10692	0	0

gen_assertions_per_power_domains[1].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18804095	250350	0	0
T1	5127	62	0	0
T2	5480	0	0	0
T3	5127	62	0	0
T4	35870	481	0	0
T5	35870	481	0	0
T6	35870	481	0	0
T7	235091	3012	0	0
T8	11330	0	0	0
T9	11330	0	0	0
T10	11330	0	0	0
T11	0	3012	0	0
T12	0	3012	0	0
T13	0	245	0	0
T24	0	48	0	0