Unified Coverage Report :: Module :: rstmgr_cascading_sva_if

Module : rstmgr_cascading_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_cascading_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_cascading_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_cascading_sva_if

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	100	1	1	100.00
ALWAYS	103	1	1	100.00
ALWAYS	107	1	1	100.00
ALWAYS	127	1	1	100.00
ALWAYS	138	1	1	100.00
ALWAYS	141	1	1	100.00
ALWAYS	144	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
100	1	1
103	1	1
107	1	1
127	1	1
138	1	1
141	1	1
144	1	1

---

Cond Coverage for Module : rstmgr_cascading_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       103
 EXPRESSION (((!scanmode)) || scan_rst_ni)
             ------1------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Covered	T1,T3,T4
1	0	Covered	T4,T5,T6

 LINE       107
 EXPRESSION (por_n_i[rstmgr_pkg::DomainAonSel] && ((!scanmode)))
             ----------------1----------------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_cascading_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	31	31	100.00	31	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	31	31	100.00	31	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CascadeEffAonToRstPorAboveFall_A	86984190	10955	0	0
CascadeEffAonToRstPorAboveRise_A	86984190	10955	0	0
CascadeEffAonToRstPorIoAboveFall_A	83502355	10955	0	0
CascadeEffAonToRstPorIoAboveRise_A	83502355	10955	0	0
CascadeEffAonToRstPorIoDiv2AboveFall_A	41752770	10955	0	0
CascadeEffAonToRstPorIoDiv2AboveRise_A	41752770	10955	0	0
CascadeEffAonToRstPorIoDiv4AboveFall_A	20876770	10955	0	0
CascadeEffAonToRstPorIoDiv4AboveRise_A	20876770	10955	0	0
CascadeEffAonToRstPorUcbAboveFall_A	41754345	10955	0	0
CascadeEffAonToRstPorUcbAboveRise_A	41754345	10955	0	0
CascadeLcToLcAboveFall_A	86984190	27855	0	0
CascadeLcToLcAboveRise_A	86984190	27855	0	0
CascadeLcToLcAonAboveFall_A	2626665	27855	0	0
CascadeLcToLcAonAboveRise_A	2626665	27855	0	0
CascadeLcToLcShadowedAboveFall_A	86984190	27855	0	0
CascadeLcToLcShadowedAboveRise_A	86984190	27855	0	0
CascadePorToAonAboveFall_A	2626665	8355	0	0
CascadeSysToSysAboveFall_A	86984190	27855	0	0
CascadeSysToSysAboveRise_A	86984190	27855	0	0
ScanRstToAonRise_A	2626665	300	0	0
StablePorToAonRise_A	2626665	10955	0	0
g_power_domains[0].CascadeLcToSysAboveFall_A	18804095	27855	0	0
g_power_domains[0].CascadeLcToSysAboveRise_A	18804095	27855	0	0
g_power_domains[0].CascadeLocalRstToLcAboveFall_A	18804095	27855	0	0
g_power_domains[0].CascadeLocalRstToLcAboveRise_A	18804095	27855	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A	20876770	27855	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A	20876770	27855	0	0
g_power_domains[1].CascadeLcToSysAboveFall_A	18804095	27855	0	0
g_power_domains[1].CascadeLcToSysAboveRise_A	18804095	27855	0	0
g_power_domains[1].CascadeLocalRstToLcAboveFall_A	18804095	27855	0	0
g_power_domains[1].CascadeLocalRstToLcAboveRise_A	18804095	27855	0	0

CascadeEffAonToRstPorAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	86984190	10955	0	0
T1	22363	2	0	0
T2	23013	2	0	0
T3	22363	2	0	0
T4	172316	20	0	0
T5	172316	20	0	0
T6	172316	20	0	0
T7	110321	128	0	0
T8	47289	1	0	0
T9	47289	1	0	0
T10	47289	1	0	0

CascadeEffAonToRstPorAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	86984190	10955	0	0
T1	22363	2	0	0
T2	23013	2	0	0
T3	22363	2	0	0
T4	172316	20	0	0
T5	172316	20	0	0
T6	172316	20	0	0
T7	110321	128	0	0
T8	47289	1	0	0
T9	47289	1	0	0
T10	47289	1	0	0

CascadeEffAonToRstPorIoAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	83502355	10955	0	0
T1	21473	2	0	0
T2	22092	2	0	0
T3	21473	2	0	0
T4	165425	20	0	0
T5	165425	20	0	0
T6	165425	20	0	0
T7	105906	128	0	0
T8	45395	1	0	0
T9	45395	1	0	0
T10	45395	1	0	0

CascadeEffAonToRstPorIoAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	83502355	10955	0	0
T1	21473	2	0	0
T2	22092	2	0	0
T3	21473	2	0	0
T4	165425	20	0	0
T5	165425	20	0	0
T6	165425	20	0	0
T7	105906	128	0	0
T8	45395	1	0	0
T9	45395	1	0	0
T10	45395	1	0	0

CascadeEffAonToRstPorIoDiv2AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	41752770	10955	0	0
T1	10735	2	0	0
T2	11046	2	0	0
T3	10735	2	0	0
T4	82708	20	0	0
T5	82708	20	0	0
T6	82708	20	0	0
T7	529561	128	0	0
T8	22698	1	0	0
T9	22698	1	0	0
T10	22698	1	0	0

CascadeEffAonToRstPorIoDiv2AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	41752770	10955	0	0
T1	10735	2	0	0
T2	11046	2	0	0
T3	10735	2	0	0
T4	82708	20	0	0
T5	82708	20	0	0
T6	82708	20	0	0
T7	529561	128	0	0
T8	22698	1	0	0
T9	22698	1	0	0
T10	22698	1	0	0

CascadeEffAonToRstPorIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20876770	10955	0	0
T1	5367	2	0	0
T2	5521	2	0	0
T3	5367	2	0	0
T4	41354	20	0	0
T5	41354	20	0	0
T6	41354	20	0	0
T7	264796	128	0	0
T8	11347	1	0	0
T9	11347	1	0	0
T10	11347	1	0	0

CascadeEffAonToRstPorIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20876770	10955	0	0
T1	5367	2	0	0
T2	5521	2	0	0
T3	5367	2	0	0
T4	41354	20	0	0
T5	41354	20	0	0
T6	41354	20	0	0
T7	264796	128	0	0
T8	11347	1	0	0
T9	11347	1	0	0
T10	11347	1	0	0

CascadeEffAonToRstPorUcbAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	41754345	10955	0	0
T1	10735	2	0	0
T2	11046	2	0	0
T3	10735	2	0	0
T4	82715	20	0	0
T5	82715	20	0	0
T6	82715	20	0	0
T7	529588	128	0	0
T8	22698	1	0	0
T9	22698	1	0	0
T10	22698	1	0	0

CascadeEffAonToRstPorUcbAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	41754345	10955	0	0
T1	10735	2	0	0
T2	11046	2	0	0
T3	10735	2	0	0
T4	82715	20	0	0
T5	82715	20	0	0
T6	82715	20	0	0
T7	529588	128	0	0
T8	22698	1	0	0
T9	22698	1	0	0
T10	22698	1	0	0

CascadeLcToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	86984190	27855	0	0
T1	22363	6	0	0
T2	23013	2	0	0
T3	22363	6	0	0
T4	172316	55	0	0
T5	172316	55	0	0
T6	172316	55	0	0
T7	110321	330	0	0
T8	47289	1	0	0
T9	47289	1	0	0
T10	47289	1	0	0

CascadeLcToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	86984190	27855	0	0
T1	22363	6	0	0
T2	23013	2	0	0
T3	22363	6	0	0
T4	172316	55	0	0
T5	172316	55	0	0
T6	172316	55	0	0
T7	110321	330	0	0
T8	47289	1	0	0
T9	47289	1	0	0
T10	47289	1	0	0

CascadeLcToLcAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2626665	27855	0	0
T1	671	6	0	0
T2	690	2	0	0
T3	671	6	0	0
T4	5189	55	0	0
T5	5189	55	0	0
T6	5189	55	0	0
T7	33393	330	0	0
T8	1418	1	0	0
T9	1418	1	0	0
T10	1418	1	0	0

CascadeLcToLcAonAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2626665	27855	0	0
T1	671	6	0	0
T2	690	2	0	0
T3	671	6	0	0
T4	5189	55	0	0
T5	5189	55	0	0
T6	5189	55	0	0
T7	33393	330	0	0
T8	1418	1	0	0
T9	1418	1	0	0
T10	1418	1	0	0

CascadeLcToLcShadowedAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	86984190	27855	0	0
T1	22363	6	0	0
T2	23013	2	0	0
T3	22363	6	0	0
T4	172316	55	0	0
T5	172316	55	0	0
T6	172316	55	0	0
T7	110321	330	0	0
T8	47289	1	0	0
T9	47289	1	0	0
T10	47289	1	0	0

CascadeLcToLcShadowedAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	86984190	27855	0	0
T1	22363	6	0	0
T2	23013	2	0	0
T3	22363	6	0	0
T4	172316	55	0	0
T5	172316	55	0	0
T6	172316	55	0	0
T7	110321	330	0	0
T8	47289	1	0	0
T9	47289	1	0	0
T10	47289	1	0	0

CascadePorToAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2626665	8355	0	0
T1	671	1	0	0
T2	690	19	0	0
T3	671	1	0	0
T4	5189	11	0	0
T5	5189	11	0	0
T6	5189	11	0	0
T7	33393	70	0	0
T8	1418	1	0	0
T9	1418	1	0	0
T10	1418	1	0	0

CascadeSysToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	86984190	27855	0	0
T1	22363	6	0	0
T2	23013	2	0	0
T3	22363	6	0	0
T4	172316	55	0	0
T5	172316	55	0	0
T6	172316	55	0	0
T7	110321	330	0	0
T8	47289	1	0	0
T9	47289	1	0	0
T10	47289	1	0	0

CascadeSysToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	86984190	27855	0	0
T1	22363	6	0	0
T2	23013	2	0	0
T3	22363	6	0	0
T4	172316	55	0	0
T5	172316	55	0	0
T6	172316	55	0	0
T7	110321	330	0	0
T8	47289	1	0	0
T9	47289	1	0	0
T10	47289	1	0	0

ScanRstToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2626665	300	0	0
T4	5189	1	0	0
T5	5189	1	0	0
T6	5189	1	0	0
T7	33393	5	0	0
T8	1418	0	0	0
T9	1418	0	0	0
T10	1418	0	0	0
T11	33393	5	0	0
T12	0	5	0	0
T23	1418	0	0	0
T38	0	1	0	0
T39	0	1	0	0
T43	0	1	0	0
T44	1418	0	0	0
T77	0	1	0	0

StablePorToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2626665	10955	0	0
T1	671	2	0	0
T2	690	2	0	0
T3	671	2	0	0
T4	5189	20	0	0
T5	5189	20	0	0
T6	5189	20	0	0
T7	33393	128	0	0
T8	1418	1	0	0
T9	1418	1	0	0
T10	1418	1	0	0

g_power_domains[0].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18804095	27855	0	0
T1	5127	6	0	0
T2	5480	2	0	0
T3	5127	6	0	0
T4	35870	55	0	0
T5	35870	55	0	0
T6	35870	55	0	0
T7	235091	330	0	0
T8	11330	1	0	0
T9	11330	1	0	0
T10	11330	1	0	0

g_power_domains[0].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18804095	27855	0	0
T1	5127	6	0	0
T2	5480	2	0	0
T3	5127	6	0	0
T4	35870	55	0	0
T5	35870	55	0	0
T6	35870	55	0	0
T7	235091	330	0	0
T8	11330	1	0	0
T9	11330	1	0	0
T10	11330	1	0	0

g_power_domains[0].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18804095	27855	0	0
T1	5127	6	0	0
T2	5480	2	0	0
T3	5127	6	0	0
T4	35870	55	0	0
T5	35870	55	0	0
T6	35870	55	0	0
T7	235091	330	0	0
T8	11330	1	0	0
T9	11330	1	0	0
T10	11330	1	0	0

g_power_domains[0].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18804095	27855	0	0
T1	5127	6	0	0
T2	5480	2	0	0
T3	5127	6	0	0
T4	35870	55	0	0
T5	35870	55	0	0
T6	35870	55	0	0
T7	235091	330	0	0
T8	11330	1	0	0
T9	11330	1	0	0
T10	11330	1	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20876770	27855	0	0
T1	5367	6	0	0
T2	5521	2	0	0
T3	5367	6	0	0
T4	41354	55	0	0
T5	41354	55	0	0
T6	41354	55	0	0
T7	264796	330	0	0
T8	11347	1	0	0
T9	11347	1	0	0
T10	11347	1	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20876770	27855	0	0
T1	5367	6	0	0
T2	5521	2	0	0
T3	5367	6	0	0
T4	41354	55	0	0
T5	41354	55	0	0
T6	41354	55	0	0
T7	264796	330	0	0
T8	11347	1	0	0
T9	11347	1	0	0
T10	11347	1	0	0

g_power_domains[1].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18804095	27855	0	0
T1	5127	6	0	0
T2	5480	2	0	0
T3	5127	6	0	0
T4	35870	55	0	0
T5	35870	55	0	0
T6	35870	55	0	0
T7	235091	330	0	0
T8	11330	1	0	0
T9	11330	1	0	0
T10	11330	1	0	0

g_power_domains[1].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18804095	27855	0	0
T1	5127	6	0	0
T2	5480	2	0	0
T3	5127	6	0	0
T4	35870	55	0	0
T5	35870	55	0	0
T6	35870	55	0	0
T7	235091	330	0	0
T8	11330	1	0	0
T9	11330	1	0	0
T10	11330	1	0	0

g_power_domains[1].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18804095	27855	0	0
T1	5127	6	0	0
T2	5480	2	0	0
T3	5127	6	0	0
T4	35870	55	0	0
T5	35870	55	0	0
T6	35870	55	0	0
T7	235091	330	0	0
T8	11330	1	0	0
T9	11330	1	0	0
T10	11330	1	0	0

g_power_domains[1].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18804095	27855	0	0
T1	5127	6	0	0
T2	5480	2	0	0
T3	5127	6	0	0
T4	35870	55	0	0
T5	35870	55	0	0
T6	35870	55	0	0
T7	235091	330	0	0
T8	11330	1	0	0
T9	11330	1	0	0
T10	11330	1	0	0