V1 |
smoke |
rstmgr_smoke |
1.570s |
262.325us |
50 |
50 |
100.00 |
V1 |
csr_hw_reset |
rstmgr_csr_hw_reset |
0.880s |
116.865us |
5 |
5 |
100.00 |
V1 |
csr_rw |
rstmgr_csr_rw |
0.870s |
97.499us |
20 |
20 |
100.00 |
V1 |
csr_bit_bash |
rstmgr_csr_bit_bash |
8.260s |
1.542ms |
5 |
5 |
100.00 |
V1 |
csr_aliasing |
rstmgr_csr_aliasing |
2.440s |
363.199us |
5 |
5 |
100.00 |
V1 |
csr_mem_rw_with_rand_reset |
rstmgr_csr_mem_rw_with_rand_reset |
1.710s |
170.373us |
20 |
20 |
100.00 |
V1 |
regwen_csr_and_corresponding_lockable_csr |
rstmgr_csr_rw |
0.870s |
97.499us |
20 |
20 |
100.00 |
|
|
rstmgr_csr_aliasing |
2.440s |
363.199us |
5 |
5 |
100.00 |
V1 |
|
TOTAL |
|
|
105 |
105 |
100.00 |
V2 |
reset_stretcher |
rstmgr_por_stretcher |
1.050s |
243.705us |
50 |
50 |
100.00 |
V2 |
sw_rst |
rstmgr_sw_rst |
2.780s |
536.620us |
50 |
50 |
100.00 |
V2 |
sw_rst_reset_race |
rstmgr_sw_rst_reset_race |
1.470s |
261.459us |
50 |
50 |
100.00 |
V2 |
reset_info |
rstmgr_reset |
7.950s |
2.056ms |
50 |
50 |
100.00 |
V2 |
cpu_info |
rstmgr_reset |
7.950s |
2.056ms |
50 |
50 |
100.00 |
V2 |
alert_info |
rstmgr_reset |
7.950s |
2.056ms |
50 |
50 |
100.00 |
V2 |
reset_info_capture |
rstmgr_reset |
7.950s |
2.056ms |
50 |
50 |
100.00 |
V2 |
stress_all |
rstmgr_stress_all |
47.190s |
13.252ms |
50 |
50 |
100.00 |
V2 |
alert_test |
rstmgr_alert_test |
0.880s |
151.117us |
50 |
50 |
100.00 |
V2 |
tl_d_oob_addr_access |
rstmgr_tl_errors |
3.770s |
592.540us |
20 |
20 |
100.00 |
V2 |
tl_d_illegal_access |
rstmgr_tl_errors |
3.770s |
592.540us |
20 |
20 |
100.00 |
V2 |
tl_d_outstanding_access |
rstmgr_csr_hw_reset |
0.880s |
116.865us |
5 |
5 |
100.00 |
|
|
rstmgr_csr_rw |
0.870s |
97.499us |
20 |
20 |
100.00 |
|
|
rstmgr_csr_aliasing |
2.440s |
363.199us |
5 |
5 |
100.00 |
|
|
rstmgr_same_csr_outstanding |
1.560s |
241.237us |
20 |
20 |
100.00 |
V2 |
tl_d_partial_access |
rstmgr_csr_hw_reset |
0.880s |
116.865us |
5 |
5 |
100.00 |
|
|
rstmgr_csr_rw |
0.870s |
97.499us |
20 |
20 |
100.00 |
|
|
rstmgr_csr_aliasing |
2.440s |
363.199us |
5 |
5 |
100.00 |
|
|
rstmgr_same_csr_outstanding |
1.560s |
241.237us |
20 |
20 |
100.00 |
V2 |
|
TOTAL |
|
|
340 |
340 |
100.00 |
V2S |
tl_intg_err |
rstmgr_sec_cm |
32.210s |
16.512ms |
5 |
5 |
100.00 |
|
|
rstmgr_tl_intg_err |
3.250s |
1.234ms |
20 |
20 |
100.00 |
V2S |
prim_count_check |
rstmgr_sec_cm |
32.210s |
16.512ms |
5 |
5 |
100.00 |
V2S |
prim_fsm_check |
rstmgr_sec_cm |
32.210s |
16.512ms |
5 |
5 |
100.00 |
V2S |
sec_cm_bus_integrity |
rstmgr_tl_intg_err |
3.250s |
1.234ms |
20 |
20 |
100.00 |
V2S |
sec_cm_scan_intersig_mubi |
rstmgr_sec_cm_scan_intersig_mubi |
1.230s |
159.166us |
50 |
50 |
100.00 |
V2S |
sec_cm_leaf_rst_bkgn_chk |
rstmgr_leaf_rst_cnsty |
9.310s |
2.356ms |
50 |
50 |
100.00 |
V2S |
sec_cm_leaf_rst_shadow |
rstmgr_leaf_rst_shadow_attack |
1.180s |
244.249us |
50 |
50 |
100.00 |
V2S |
sec_cm_leaf_fsm_sparse |
rstmgr_sec_cm |
32.210s |
16.512ms |
5 |
5 |
100.00 |
V2S |
sec_cm_sw_rst_config_regwen |
rstmgr_csr_rw |
0.870s |
97.499us |
20 |
20 |
100.00 |
V2S |
sec_cm_dump_ctrl_config_regwen |
rstmgr_csr_rw |
0.870s |
97.499us |
20 |
20 |
100.00 |
V2S |
|
TOTAL |
|
|
175 |
175 |
100.00 |
V3 |
stress_all_with_rand_reset |
rstmgr_stress_all_with_rand_reset |
|
|
0 |
0 |
-- |
V3 |
|
TOTAL |
|
|
0 |
0 |
-- |
|
|
TOTAL |
|
|
620 |
620 |
100.00 |