Group : rstmgr_env_pkg::rstmgr_sw_rst_cg_wrap::sw_rst_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : rstmgr_env_pkg::rstmgr_sw_rst_cg_wrap::sw_rst_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv

8 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
sw_rst_ctrl_n[0] 100.00 1 100 1 64 64
sw_rst_ctrl_n[1] 100.00 1 100 1 64 64
sw_rst_ctrl_n[2] 100.00 1 100 1 64 64
sw_rst_ctrl_n[3] 100.00 1 100 1 64 64
sw_rst_ctrl_n[4] 100.00 1 100 1 64 64
sw_rst_ctrl_n[5] 100.00 1 100 1 64 64
sw_rst_ctrl_n[6] 100.00 1 100 1 64 64
sw_rst_ctrl_n[7] 100.00 1 100 1 64 64




Group Instance : sw_rst_ctrl_n[0]
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance sw_rst_ctrl_n[0]

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 0 8 100.00
Crosses 4 0 4 100.00


Variables for Group Instance sw_rst_ctrl_n[0]
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
enable 2 0 2 100.00 100 1 1 2
enable_cp 2 0 2 100.00 100 1 1 2
rst_n 2 0 2 100.00 100 1 1 2
rst_n_cp 2 0 2 100.00 100 1 1 2


Crosses for Group Instance sw_rst_ctrl_n[0]
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
sw_rst_cross 4 0 4 100.00 100 1 1 0



Group Instance : sw_rst_ctrl_n[1]
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance sw_rst_ctrl_n[1]

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 0 8 100.00
Crosses 4 0 4 100.00


Variables for Group Instance sw_rst_ctrl_n[1]
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
enable 2 0 2 100.00 100 1 1 2
enable_cp 2 0 2 100.00 100 1 1 2
rst_n 2 0 2 100.00 100 1 1 2
rst_n_cp 2 0 2 100.00 100 1 1 2


Crosses for Group Instance sw_rst_ctrl_n[1]
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
sw_rst_cross 4 0 4 100.00 100 1 1 0



Group Instance : sw_rst_ctrl_n[2]
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance sw_rst_ctrl_n[2]

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 0 8 100.00
Crosses 4 0 4 100.00


Variables for Group Instance sw_rst_ctrl_n[2]
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
enable 2 0 2 100.00 100 1 1 2
enable_cp 2 0 2 100.00 100 1 1 2
rst_n 2 0 2 100.00 100 1 1 2
rst_n_cp 2 0 2 100.00 100 1 1 2


Crosses for Group Instance sw_rst_ctrl_n[2]
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
sw_rst_cross 4 0 4 100.00 100 1 1 0



Group Instance : sw_rst_ctrl_n[3]
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance sw_rst_ctrl_n[3]

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 0 8 100.00
Crosses 4 0 4 100.00


Variables for Group Instance sw_rst_ctrl_n[3]
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
enable 2 0 2 100.00 100 1 1 2
enable_cp 2 0 2 100.00 100 1 1 2
rst_n 2 0 2 100.00 100 1 1 2
rst_n_cp 2 0 2 100.00 100 1 1 2


Crosses for Group Instance sw_rst_ctrl_n[3]
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
sw_rst_cross 4 0 4 100.00 100 1 1 0



Group Instance : sw_rst_ctrl_n[4]
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance sw_rst_ctrl_n[4]

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 0 8 100.00
Crosses 4 0 4 100.00


Variables for Group Instance sw_rst_ctrl_n[4]
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
enable 2 0 2 100.00 100 1 1 2
enable_cp 2 0 2 100.00 100 1 1 2
rst_n 2 0 2 100.00 100 1 1 2
rst_n_cp 2 0 2 100.00 100 1 1 2


Crosses for Group Instance sw_rst_ctrl_n[4]
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
sw_rst_cross 4 0 4 100.00 100 1 1 0



Group Instance : sw_rst_ctrl_n[5]
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance sw_rst_ctrl_n[5]

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 0 8 100.00
Crosses 4 0 4 100.00


Variables for Group Instance sw_rst_ctrl_n[5]
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
enable 2 0 2 100.00 100 1 1 2
enable_cp 2 0 2 100.00 100 1 1 2
rst_n 2 0 2 100.00 100 1 1 2
rst_n_cp 2 0 2 100.00 100 1 1 2


Crosses for Group Instance sw_rst_ctrl_n[5]
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
sw_rst_cross 4 0 4 100.00 100 1 1 0



Group Instance : sw_rst_ctrl_n[6]
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance sw_rst_ctrl_n[6]

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 0 8 100.00
Crosses 4 0 4 100.00


Variables for Group Instance sw_rst_ctrl_n[6]
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
enable 2 0 2 100.00 100 1 1 2
enable_cp 2 0 2 100.00 100 1 1 2
rst_n 2 0 2 100.00 100 1 1 2
rst_n_cp 2 0 2 100.00 100 1 1 2


Crosses for Group Instance sw_rst_ctrl_n[6]
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
sw_rst_cross 4 0 4 100.00 100 1 1 0



Group Instance : sw_rst_ctrl_n[7]
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance sw_rst_ctrl_n[7]

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 0 8 100.00
Crosses 4 0 4 100.00


Variables for Group Instance sw_rst_ctrl_n[7]
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
enable 2 0 2 100.00 100 1 1 2
enable_cp 2 0 2 100.00 100 1 1 2
rst_n 2 0 2 100.00 100 1 1 2
rst_n_cp 2 0 2 100.00 100 1 1 2


Crosses for Group Instance sw_rst_ctrl_n[7]
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
sw_rst_cross 4 0 4 100.00 100 1 1 0


Summary for Variable enable

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for enable

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1600 1 T60 32 T61 32 T62 32
auto[1] 4942 1 T1 3 T3 10 T12 22



Summary for Variable enable_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for enable_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1600 1 T60 32 T61 32 T62 32
auto[1] 4942 1 T1 3 T3 10 T12 22



Summary for Variable rst_n

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for rst_n

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1878 1 T3 1 T12 6 T24 3
auto[1] 4664 1 T1 3 T3 9 T12 16



Summary for Variable rst_n_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for rst_n_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1878 1 T3 1 T12 6 T24 3
auto[1] 4664 1 T1 3 T3 9 T12 16



Summary for Cross sw_rst_cross

Samples crossed: enable rst_n
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for sw_rst_cross

Bins
enablerst_nCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 400 1 T60 8 T61 8 T62 8
auto[0] auto[1] 1200 1 T60 24 T61 24 T62 24
auto[1] auto[0] 1478 1 T3 1 T12 6 T24 3
auto[1] auto[1] 3464 1 T1 3 T3 9 T12 16


Summary for Variable enable

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for enable

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1469 1 T60 28 T61 28 T62 28
auto[1] 4830 1 T1 3 T3 8 T12 16



Summary for Variable enable_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for enable_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1469 1 T60 28 T61 28 T62 28
auto[1] 4830 1 T1 3 T3 8 T12 16



Summary for Variable rst_n

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for rst_n

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1815 1 T1 1 T60 12 T77 3
auto[1] 4484 1 T1 2 T3 8 T12 16



Summary for Variable rst_n_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for rst_n_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1815 1 T1 1 T60 12 T77 3
auto[1] 4484 1 T1 2 T3 8 T12 16



Summary for Cross sw_rst_cross

Samples crossed: enable rst_n
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for sw_rst_cross

Bins
enablerst_nCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 383 1 T60 7 T61 7 T62 7
auto[0] auto[1] 1086 1 T60 21 T61 21 T62 21
auto[1] auto[0] 1432 1 T1 1 T60 5 T77 3
auto[1] auto[1] 3398 1 T1 2 T3 8 T12 16


Summary for Variable enable

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for enable

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1266 1 T1 3 T60 24 T61 24
auto[1] 4922 1 T3 8 T12 11 T24 8



Summary for Variable enable_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for enable_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1266 1 T1 3 T60 24 T61 24
auto[1] 4922 1 T3 8 T12 11 T24 8



Summary for Variable rst_n

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for rst_n

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1707 1 T1 2 T60 10 T61 18
auto[1] 4481 1 T1 1 T3 8 T12 11



Summary for Variable rst_n_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for rst_n_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1707 1 T1 2 T60 10 T61 18
auto[1] 4481 1 T1 1 T3 8 T12 11



Summary for Cross sw_rst_cross

Samples crossed: enable rst_n
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for sw_rst_cross

Bins
enablerst_nCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 334 1 T1 2 T60 6 T61 6
auto[0] auto[1] 932 1 T1 1 T60 18 T61 18
auto[1] auto[0] 1373 1 T60 4 T61 12 T62 4
auto[1] auto[1] 3549 1 T3 8 T12 11 T24 8


Summary for Variable enable

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for enable

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1093 1 T1 3 T60 20 T61 20
auto[1] 5081 1 T3 8 T12 11 T24 8



Summary for Variable enable_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for enable_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1093 1 T1 3 T60 20 T61 20
auto[1] 5081 1 T3 8 T12 11 T24 8



Summary for Variable rst_n

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for rst_n

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1788 1 T1 1 T60 11 T61 14
auto[1] 4386 1 T1 2 T3 8 T12 11



Summary for Variable rst_n_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for rst_n_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1788 1 T1 1 T60 11 T61 14
auto[1] 4386 1 T1 2 T3 8 T12 11



Summary for Cross sw_rst_cross

Samples crossed: enable rst_n
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for sw_rst_cross

Bins
enablerst_nCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 300 1 T1 1 T60 5 T61 5
auto[0] auto[1] 793 1 T1 2 T60 15 T61 15
auto[1] auto[0] 1488 1 T60 6 T61 9 T62 5
auto[1] auto[1] 3593 1 T3 8 T12 11 T24 8


Summary for Variable enable

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for enable

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 884 1 T60 16 T61 16 T62 16
auto[1] 5290 1 T1 3 T3 8 T12 11



Summary for Variable enable_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for enable_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 884 1 T60 16 T61 16 T62 16
auto[1] 5290 1 T1 3 T3 8 T12 11



Summary for Variable rst_n

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for rst_n

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1741 1 T60 14 T61 13 T62 10
auto[1] 4433 1 T1 3 T3 8 T12 11



Summary for Variable rst_n_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for rst_n_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1741 1 T60 14 T61 13 T62 10
auto[1] 4433 1 T1 3 T3 8 T12 11



Summary for Cross sw_rst_cross

Samples crossed: enable rst_n
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for sw_rst_cross

Bins
enablerst_nCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 239 1 T60 4 T61 4 T62 4
auto[0] auto[1] 645 1 T60 12 T61 12 T62 12
auto[1] auto[0] 1502 1 T60 10 T61 9 T62 6
auto[1] auto[1] 3788 1 T1 3 T3 8 T12 11


Summary for Variable enable

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for enable

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 675 1 T60 12 T61 12 T62 12
auto[1] 5499 1 T1 3 T3 8 T12 11



Summary for Variable enable_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for enable_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 675 1 T60 12 T61 12 T62 12
auto[1] 5499 1 T1 3 T3 8 T12 11



Summary for Variable rst_n

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for rst_n

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1736 1 T60 13 T61 18 T62 11
auto[1] 4438 1 T1 3 T3 8 T12 11



Summary for Variable rst_n_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for rst_n_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1736 1 T60 13 T61 18 T62 11
auto[1] 4438 1 T1 3 T3 8 T12 11



Summary for Cross sw_rst_cross

Samples crossed: enable rst_n
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for sw_rst_cross

Bins
enablerst_nCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 188 1 T60 3 T61 3 T62 3
auto[0] auto[1] 487 1 T60 9 T61 9 T62 9
auto[1] auto[0] 1548 1 T60 10 T61 15 T62 8
auto[1] auto[1] 3951 1 T1 3 T3 8 T12 11


Summary for Variable enable

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for enable

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 469 1 T1 3 T60 8 T61 8
auto[1] 5705 1 T3 8 T12 11 T24 8



Summary for Variable enable_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for enable_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 469 1 T1 3 T60 8 T61 8
auto[1] 5705 1 T3 8 T12 11 T24 8



Summary for Variable rst_n

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for rst_n

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1763 1 T1 2 T60 11 T61 16
auto[1] 4411 1 T1 1 T3 8 T12 11



Summary for Variable rst_n_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for rst_n_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1763 1 T1 2 T60 11 T61 16
auto[1] 4411 1 T1 1 T3 8 T12 11



Summary for Cross sw_rst_cross

Samples crossed: enable rst_n
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for sw_rst_cross

Bins
enablerst_nCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 137 1 T1 2 T60 2 T61 2
auto[0] auto[1] 332 1 T1 1 T60 6 T61 6
auto[1] auto[0] 1626 1 T60 9 T61 14 T62 8
auto[1] auto[1] 4079 1 T3 8 T12 11 T24 8


Summary for Variable enable

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for enable

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 275 1 T60 4 T61 4 T62 4
auto[1] 5899 1 T1 3 T3 8 T12 11



Summary for Variable enable_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for enable_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 275 1 T60 4 T61 4 T62 4
auto[1] 5899 1 T1 3 T3 8 T12 11



Summary for Variable rst_n

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for rst_n

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1744 1 T60 12 T61 14 T62 9
auto[1] 4430 1 T1 3 T3 8 T12 11



Summary for Variable rst_n_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for rst_n_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1744 1 T60 12 T61 14 T62 9
auto[1] 4430 1 T1 3 T3 8 T12 11



Summary for Cross sw_rst_cross

Samples crossed: enable rst_n
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for sw_rst_cross

Bins
enablerst_nCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 87 1 T60 1 T61 1 T62 1
auto[0] auto[1] 188 1 T60 3 T61 3 T62 3
auto[1] auto[0] 1657 1 T60 11 T61 13 T62 8
auto[1] auto[1] 4242 1 T1 3 T3 8 T12 11

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%