Summary for Variable enable
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1600 |
1 |
|
|
T60 |
32 |
|
T61 |
32 |
|
T62 |
32 |
auto[1] |
4942 |
1 |
|
|
T1 |
3 |
|
T3 |
10 |
|
T12 |
22 |
Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1600 |
1 |
|
|
T60 |
32 |
|
T61 |
32 |
|
T62 |
32 |
auto[1] |
4942 |
1 |
|
|
T1 |
3 |
|
T3 |
10 |
|
T12 |
22 |
Summary for Variable rst_n
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for rst_n
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1878 |
1 |
|
|
T3 |
1 |
|
T12 |
6 |
|
T24 |
3 |
auto[1] |
4664 |
1 |
|
|
T1 |
3 |
|
T3 |
9 |
|
T12 |
16 |
Summary for Variable rst_n_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for rst_n_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1878 |
1 |
|
|
T3 |
1 |
|
T12 |
6 |
|
T24 |
3 |
auto[1] |
4664 |
1 |
|
|
T1 |
3 |
|
T3 |
9 |
|
T12 |
16 |
Summary for Cross sw_rst_cross
Samples crossed: enable rst_n
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for sw_rst_cross
Bins
enable | rst_n | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
400 |
1 |
|
|
T60 |
8 |
|
T61 |
8 |
|
T62 |
8 |
auto[0] |
auto[1] |
1200 |
1 |
|
|
T60 |
24 |
|
T61 |
24 |
|
T62 |
24 |
auto[1] |
auto[0] |
1478 |
1 |
|
|
T3 |
1 |
|
T12 |
6 |
|
T24 |
3 |
auto[1] |
auto[1] |
3464 |
1 |
|
|
T1 |
3 |
|
T3 |
9 |
|
T12 |
16 |
Summary for Variable enable
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1469 |
1 |
|
|
T60 |
28 |
|
T61 |
28 |
|
T62 |
28 |
auto[1] |
4830 |
1 |
|
|
T1 |
3 |
|
T3 |
8 |
|
T12 |
16 |
Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1469 |
1 |
|
|
T60 |
28 |
|
T61 |
28 |
|
T62 |
28 |
auto[1] |
4830 |
1 |
|
|
T1 |
3 |
|
T3 |
8 |
|
T12 |
16 |
Summary for Variable rst_n
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for rst_n
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1815 |
1 |
|
|
T1 |
1 |
|
T60 |
12 |
|
T77 |
3 |
auto[1] |
4484 |
1 |
|
|
T1 |
2 |
|
T3 |
8 |
|
T12 |
16 |
Summary for Variable rst_n_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for rst_n_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1815 |
1 |
|
|
T1 |
1 |
|
T60 |
12 |
|
T77 |
3 |
auto[1] |
4484 |
1 |
|
|
T1 |
2 |
|
T3 |
8 |
|
T12 |
16 |
Summary for Cross sw_rst_cross
Samples crossed: enable rst_n
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for sw_rst_cross
Bins
enable | rst_n | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
383 |
1 |
|
|
T60 |
7 |
|
T61 |
7 |
|
T62 |
7 |
auto[0] |
auto[1] |
1086 |
1 |
|
|
T60 |
21 |
|
T61 |
21 |
|
T62 |
21 |
auto[1] |
auto[0] |
1432 |
1 |
|
|
T1 |
1 |
|
T60 |
5 |
|
T77 |
3 |
auto[1] |
auto[1] |
3398 |
1 |
|
|
T1 |
2 |
|
T3 |
8 |
|
T12 |
16 |
Summary for Variable enable
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1266 |
1 |
|
|
T1 |
3 |
|
T60 |
24 |
|
T61 |
24 |
auto[1] |
4922 |
1 |
|
|
T3 |
8 |
|
T12 |
11 |
|
T24 |
8 |
Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1266 |
1 |
|
|
T1 |
3 |
|
T60 |
24 |
|
T61 |
24 |
auto[1] |
4922 |
1 |
|
|
T3 |
8 |
|
T12 |
11 |
|
T24 |
8 |
Summary for Variable rst_n
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for rst_n
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1707 |
1 |
|
|
T1 |
2 |
|
T60 |
10 |
|
T61 |
18 |
auto[1] |
4481 |
1 |
|
|
T1 |
1 |
|
T3 |
8 |
|
T12 |
11 |
Summary for Variable rst_n_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for rst_n_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1707 |
1 |
|
|
T1 |
2 |
|
T60 |
10 |
|
T61 |
18 |
auto[1] |
4481 |
1 |
|
|
T1 |
1 |
|
T3 |
8 |
|
T12 |
11 |
Summary for Cross sw_rst_cross
Samples crossed: enable rst_n
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for sw_rst_cross
Bins
enable | rst_n | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
334 |
1 |
|
|
T1 |
2 |
|
T60 |
6 |
|
T61 |
6 |
auto[0] |
auto[1] |
932 |
1 |
|
|
T1 |
1 |
|
T60 |
18 |
|
T61 |
18 |
auto[1] |
auto[0] |
1373 |
1 |
|
|
T60 |
4 |
|
T61 |
12 |
|
T62 |
4 |
auto[1] |
auto[1] |
3549 |
1 |
|
|
T3 |
8 |
|
T12 |
11 |
|
T24 |
8 |
Summary for Variable enable
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1093 |
1 |
|
|
T1 |
3 |
|
T60 |
20 |
|
T61 |
20 |
auto[1] |
5081 |
1 |
|
|
T3 |
8 |
|
T12 |
11 |
|
T24 |
8 |
Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1093 |
1 |
|
|
T1 |
3 |
|
T60 |
20 |
|
T61 |
20 |
auto[1] |
5081 |
1 |
|
|
T3 |
8 |
|
T12 |
11 |
|
T24 |
8 |
Summary for Variable rst_n
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for rst_n
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1788 |
1 |
|
|
T1 |
1 |
|
T60 |
11 |
|
T61 |
14 |
auto[1] |
4386 |
1 |
|
|
T1 |
2 |
|
T3 |
8 |
|
T12 |
11 |
Summary for Variable rst_n_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for rst_n_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1788 |
1 |
|
|
T1 |
1 |
|
T60 |
11 |
|
T61 |
14 |
auto[1] |
4386 |
1 |
|
|
T1 |
2 |
|
T3 |
8 |
|
T12 |
11 |
Summary for Cross sw_rst_cross
Samples crossed: enable rst_n
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for sw_rst_cross
Bins
enable | rst_n | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
300 |
1 |
|
|
T1 |
1 |
|
T60 |
5 |
|
T61 |
5 |
auto[0] |
auto[1] |
793 |
1 |
|
|
T1 |
2 |
|
T60 |
15 |
|
T61 |
15 |
auto[1] |
auto[0] |
1488 |
1 |
|
|
T60 |
6 |
|
T61 |
9 |
|
T62 |
5 |
auto[1] |
auto[1] |
3593 |
1 |
|
|
T3 |
8 |
|
T12 |
11 |
|
T24 |
8 |
Summary for Variable enable
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
884 |
1 |
|
|
T60 |
16 |
|
T61 |
16 |
|
T62 |
16 |
auto[1] |
5290 |
1 |
|
|
T1 |
3 |
|
T3 |
8 |
|
T12 |
11 |
Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
884 |
1 |
|
|
T60 |
16 |
|
T61 |
16 |
|
T62 |
16 |
auto[1] |
5290 |
1 |
|
|
T1 |
3 |
|
T3 |
8 |
|
T12 |
11 |
Summary for Variable rst_n
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for rst_n
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1741 |
1 |
|
|
T60 |
14 |
|
T61 |
13 |
|
T62 |
10 |
auto[1] |
4433 |
1 |
|
|
T1 |
3 |
|
T3 |
8 |
|
T12 |
11 |
Summary for Variable rst_n_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for rst_n_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1741 |
1 |
|
|
T60 |
14 |
|
T61 |
13 |
|
T62 |
10 |
auto[1] |
4433 |
1 |
|
|
T1 |
3 |
|
T3 |
8 |
|
T12 |
11 |
Summary for Cross sw_rst_cross
Samples crossed: enable rst_n
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for sw_rst_cross
Bins
enable | rst_n | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
239 |
1 |
|
|
T60 |
4 |
|
T61 |
4 |
|
T62 |
4 |
auto[0] |
auto[1] |
645 |
1 |
|
|
T60 |
12 |
|
T61 |
12 |
|
T62 |
12 |
auto[1] |
auto[0] |
1502 |
1 |
|
|
T60 |
10 |
|
T61 |
9 |
|
T62 |
6 |
auto[1] |
auto[1] |
3788 |
1 |
|
|
T1 |
3 |
|
T3 |
8 |
|
T12 |
11 |
Summary for Variable enable
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
675 |
1 |
|
|
T60 |
12 |
|
T61 |
12 |
|
T62 |
12 |
auto[1] |
5499 |
1 |
|
|
T1 |
3 |
|
T3 |
8 |
|
T12 |
11 |
Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
675 |
1 |
|
|
T60 |
12 |
|
T61 |
12 |
|
T62 |
12 |
auto[1] |
5499 |
1 |
|
|
T1 |
3 |
|
T3 |
8 |
|
T12 |
11 |
Summary for Variable rst_n
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for rst_n
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1736 |
1 |
|
|
T60 |
13 |
|
T61 |
18 |
|
T62 |
11 |
auto[1] |
4438 |
1 |
|
|
T1 |
3 |
|
T3 |
8 |
|
T12 |
11 |
Summary for Variable rst_n_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for rst_n_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1736 |
1 |
|
|
T60 |
13 |
|
T61 |
18 |
|
T62 |
11 |
auto[1] |
4438 |
1 |
|
|
T1 |
3 |
|
T3 |
8 |
|
T12 |
11 |
Summary for Cross sw_rst_cross
Samples crossed: enable rst_n
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for sw_rst_cross
Bins
enable | rst_n | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
188 |
1 |
|
|
T60 |
3 |
|
T61 |
3 |
|
T62 |
3 |
auto[0] |
auto[1] |
487 |
1 |
|
|
T60 |
9 |
|
T61 |
9 |
|
T62 |
9 |
auto[1] |
auto[0] |
1548 |
1 |
|
|
T60 |
10 |
|
T61 |
15 |
|
T62 |
8 |
auto[1] |
auto[1] |
3951 |
1 |
|
|
T1 |
3 |
|
T3 |
8 |
|
T12 |
11 |
Summary for Variable enable
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
469 |
1 |
|
|
T1 |
3 |
|
T60 |
8 |
|
T61 |
8 |
auto[1] |
5705 |
1 |
|
|
T3 |
8 |
|
T12 |
11 |
|
T24 |
8 |
Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
469 |
1 |
|
|
T1 |
3 |
|
T60 |
8 |
|
T61 |
8 |
auto[1] |
5705 |
1 |
|
|
T3 |
8 |
|
T12 |
11 |
|
T24 |
8 |
Summary for Variable rst_n
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for rst_n
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1763 |
1 |
|
|
T1 |
2 |
|
T60 |
11 |
|
T61 |
16 |
auto[1] |
4411 |
1 |
|
|
T1 |
1 |
|
T3 |
8 |
|
T12 |
11 |
Summary for Variable rst_n_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for rst_n_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1763 |
1 |
|
|
T1 |
2 |
|
T60 |
11 |
|
T61 |
16 |
auto[1] |
4411 |
1 |
|
|
T1 |
1 |
|
T3 |
8 |
|
T12 |
11 |
Summary for Cross sw_rst_cross
Samples crossed: enable rst_n
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for sw_rst_cross
Bins
enable | rst_n | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
137 |
1 |
|
|
T1 |
2 |
|
T60 |
2 |
|
T61 |
2 |
auto[0] |
auto[1] |
332 |
1 |
|
|
T1 |
1 |
|
T60 |
6 |
|
T61 |
6 |
auto[1] |
auto[0] |
1626 |
1 |
|
|
T60 |
9 |
|
T61 |
14 |
|
T62 |
8 |
auto[1] |
auto[1] |
4079 |
1 |
|
|
T3 |
8 |
|
T12 |
11 |
|
T24 |
8 |
Summary for Variable enable
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
275 |
1 |
|
|
T60 |
4 |
|
T61 |
4 |
|
T62 |
4 |
auto[1] |
5899 |
1 |
|
|
T1 |
3 |
|
T3 |
8 |
|
T12 |
11 |
Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
275 |
1 |
|
|
T60 |
4 |
|
T61 |
4 |
|
T62 |
4 |
auto[1] |
5899 |
1 |
|
|
T1 |
3 |
|
T3 |
8 |
|
T12 |
11 |
Summary for Variable rst_n
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for rst_n
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1744 |
1 |
|
|
T60 |
12 |
|
T61 |
14 |
|
T62 |
9 |
auto[1] |
4430 |
1 |
|
|
T1 |
3 |
|
T3 |
8 |
|
T12 |
11 |
Summary for Variable rst_n_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for rst_n_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1744 |
1 |
|
|
T60 |
12 |
|
T61 |
14 |
|
T62 |
9 |
auto[1] |
4430 |
1 |
|
|
T1 |
3 |
|
T3 |
8 |
|
T12 |
11 |
Summary for Cross sw_rst_cross
Samples crossed: enable rst_n
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for sw_rst_cross
Bins
enable | rst_n | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
87 |
1 |
|
|
T60 |
1 |
|
T61 |
1 |
|
T62 |
1 |
auto[0] |
auto[1] |
188 |
1 |
|
|
T60 |
3 |
|
T61 |
3 |
|
T62 |
3 |
auto[1] |
auto[0] |
1657 |
1 |
|
|
T60 |
11 |
|
T61 |
13 |
|
T62 |
8 |
auto[1] |
auto[1] |
4242 |
1 |
|
|
T1 |
3 |
|
T3 |
8 |
|
T12 |
11 |