Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	636376	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

382146

1

T1

121

T2

1095

T3

48

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	544067	1			T1	186		T2	1666		T3	72
values[0x0]	236671	1			T1	88		T2	637		T3	35
values[0x1]	237784	1			T1	105		T2	725		T3	40

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	533867	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

484655

1

T1

161

T2

1378

T3

64

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	5296	1			T2	5		T7	5		T8	15
valid_sources[0x01]	4258	1			T1	1		T2	7		T7	19
valid_sources[0x02]	4087	1			T2	8		T3	1		T7	10
valid_sources[0x03]	6602	1			T1	2		T2	11		T7	9
valid_sources[0x04]	3252	1			T1	1		T2	12		T7	10
valid_sources[0x05]	4020	1			T2	13		T3	2		T7	8
valid_sources[0x06]	4638	1			T1	3		T2	12		T7	9
valid_sources[0x07]	4265	1			T1	3		T2	21		T3	2
valid_sources[0x08]	3645	1			T1	4		T2	9		T7	7
valid_sources[0x09]	3600	1			T1	1		T2	14		T7	14
valid_sources[0x0a]	4189	1			T1	4		T2	18		T7	6
valid_sources[0x0b]	3654	1			T2	8		T7	11		T8	12
valid_sources[0x0c]	2976	1			T1	2		T2	8		T7	11
valid_sources[0x0d]	4744	1			T1	2		T2	10		T7	12
valid_sources[0x0e]	6241	1			T1	1		T2	9		T3	1
valid_sources[0x0f]	4546	1			T1	3		T2	8		T3	2
valid_sources[0x10]	3273	1			T1	2		T2	12		T7	9
valid_sources[0x11]	3208	1			T1	1		T2	15		T7	6
valid_sources[0x12]	3480	1			T1	2		T2	15		T6	1
valid_sources[0x13]	3422	1			T1	2		T2	22		T3	1
valid_sources[0x14]	2914	1			T1	2		T2	11		T7	14
valid_sources[0x15]	4910	1			T2	8		T7	15		T8	14
valid_sources[0x16]	4510	1			T2	5		T7	10		T8	14
valid_sources[0x17]	4211	1			T2	14		T3	2		T7	11
valid_sources[0x18]	3928	1			T1	1		T2	14		T3	3
valid_sources[0x19]	3338	1			T1	2		T2	11		T3	1
valid_sources[0x1a]	4314	1			T2	11		T3	1		T7	6
valid_sources[0x1b]	3395	1			T1	2		T2	12		T6	3
valid_sources[0x1c]	3257	1			T1	2		T2	10		T7	10
valid_sources[0x1d]	4588	1			T1	1		T2	15		T3	2
valid_sources[0x1e]	6494	1			T1	1		T2	12		T7	15
valid_sources[0x1f]	3516	1			T2	11		T3	2		T7	7
valid_sources[0x20]	3309	1			T1	1		T2	14		T3	2
valid_sources[0x21]	3671	1			T1	1		T2	11		T7	12
valid_sources[0x22]	3511	1			T2	6		T3	1		T7	8
valid_sources[0x23]	4018	1			T2	12		T3	2		T7	12
valid_sources[0x24]	3418	1			T1	1		T2	16		T3	2
valid_sources[0x25]	3376	1			T1	4		T2	19		T3	1
valid_sources[0x26]	3387	1			T1	1		T2	15		T7	8
valid_sources[0x27]	6899	1			T2	9		T7	9		T8	13
valid_sources[0x28]	3394	1			T2	9		T3	2		T7	15
valid_sources[0x29]	4020	1			T2	8		T3	1		T7	11
valid_sources[0x2a]	3838	1			T1	1		T2	8		T7	14
valid_sources[0x2b]	3371	1			T1	1		T2	14		T3	5
valid_sources[0x2c]	3914	1			T2	16		T3	4		T7	19
valid_sources[0x2d]	3237	1			T2	14		T3	3		T7	7
valid_sources[0x2e]	3189	1			T1	1		T2	13		T7	11
valid_sources[0x2f]	3007	1			T2	8		T7	6		T8	9
valid_sources[0x30]	3407	1			T1	3		T2	7		T3	2
valid_sources[0x31]	4110	1			T1	2		T2	9		T7	17
valid_sources[0x32]	4972	1			T1	3		T2	10		T7	18
valid_sources[0x33]	3282	1			T2	10		T7	17		T8	16
valid_sources[0x34]	3209	1			T1	3		T2	12		T3	2
valid_sources[0x35]	3349	1			T1	3		T2	10		T3	1
valid_sources[0x36]	4365	1			T1	4		T2	12		T7	12
valid_sources[0x37]	3729	1			T1	2		T2	10		T7	11
valid_sources[0x38]	3438	1			T1	1		T2	16		T7	7
valid_sources[0x39]	3674	1			T1	2		T2	10		T6	2
valid_sources[0x3a]	3685	1			T2	9		T3	1		T6	3
valid_sources[0x3b]	3576	1			T1	4		T2	10		T7	6
valid_sources[0x3c]	3751	1			T2	13		T7	10		T8	16
valid_sources[0x3d]	3126	1			T1	1		T2	6		T7	6
valid_sources[0x3e]	2961	1			T1	2		T2	18		T7	9
valid_sources[0x3f]	3398	1			T2	8		T3	5		T6	1
valid_sources[0x40]	6296	1			T1	3		T2	7		T7	7
valid_sources[0x41]	4172	1			T1	2		T2	5		T7	11
valid_sources[0x42]	3913	1			T1	1		T2	8		T7	6
valid_sources[0x43]	3223	1			T1	3		T2	16		T7	10
valid_sources[0x44]	3112	1			T1	2		T2	12		T7	4
valid_sources[0x45]	3371	1			T1	1		T2	12		T7	7
valid_sources[0x46]	6682	1			T1	4		T2	13		T3	1
valid_sources[0x47]	4165	1			T1	2		T2	9		T3	1
valid_sources[0x48]	3549	1			T1	3		T2	16		T5	1
valid_sources[0x49]	3621	1			T1	2		T2	14		T7	7
valid_sources[0x4a]	3108	1			T2	15		T3	1		T7	5
valid_sources[0x4b]	3333	1			T1	5		T2	12		T7	6
valid_sources[0x4c]	3340	1			T2	11		T3	1		T7	11
valid_sources[0x4d]	3194	1			T1	1		T2	11		T7	7
valid_sources[0x4e]	6790	1			T1	2		T2	10		T3	2
valid_sources[0x4f]	3345	1			T1	1		T2	18		T7	14
valid_sources[0x50]	3513	1			T1	1		T2	7		T3	1
valid_sources[0x51]	3625	1			T1	2		T2	6		T3	1
valid_sources[0x52]	3561	1			T1	1		T2	7		T7	11
valid_sources[0x53]	3346	1			T1	1		T2	18		T3	3
valid_sources[0x54]	6919	1			T1	5		T2	19		T7	10
valid_sources[0x55]	3483	1			T1	1		T2	8		T3	2
valid_sources[0x56]	7147	1			T2	14		T7	19		T8	14
valid_sources[0x57]	3814	1			T2	9		T7	7		T8	8
valid_sources[0x58]	3270	1			T1	1		T2	13		T7	16
valid_sources[0x59]	3380	1			T2	10		T7	7		T8	12
valid_sources[0x5a]	4148	1			T1	2		T2	11		T7	4
valid_sources[0x5b]	3700	1			T1	1		T2	18		T7	13
valid_sources[0x5c]	3304	1			T1	2		T2	17		T3	2
valid_sources[0x5d]	3535	1			T1	2		T2	12		T3	2
valid_sources[0x5e]	3373	1			T1	1		T2	14		T6	1
valid_sources[0x5f]	4092	1			T1	2		T2	16		T7	13
valid_sources[0x60]	4032	1			T1	2		T2	9		T7	7
valid_sources[0x61]	4572	1			T1	1		T2	9		T7	15
valid_sources[0x62]	3692	1			T1	2		T2	14		T7	14
valid_sources[0x63]	4503	1			T2	12		T7	12		T8	15
valid_sources[0x64]	3772	1			T1	1		T2	11		T6	1
valid_sources[0x65]	3210	1			T2	10		T7	13		T8	20
valid_sources[0x66]	3692	1			T1	2		T2	6		T3	1
valid_sources[0x67]	4086	1			T2	8		T7	7		T8	10
valid_sources[0x68]	3439	1			T2	13		T3	1		T7	11
valid_sources[0x69]	5992	1			T1	4		T2	13		T3	2
valid_sources[0x6a]	3611	1			T1	1		T2	22		T3	1
valid_sources[0x6b]	7586	1			T1	1		T2	9		T7	6
valid_sources[0x6c]	4207	1			T1	2		T2	8		T7	11
valid_sources[0x6d]	3728	1			T1	1		T2	12		T7	7
valid_sources[0x6e]	3154	1			T1	1		T2	4		T3	1
valid_sources[0x6f]	4162	1			T1	4		T2	13		T7	9
valid_sources[0x70]	3147	1			T1	1		T2	12		T7	11
valid_sources[0x71]	2894	1			T1	1		T2	19		T3	3
valid_sources[0x72]	3293	1			T2	10		T7	11		T8	11
valid_sources[0x73]	6719	1			T1	2		T2	13		T3	4
valid_sources[0x74]	3588	1			T1	1		T2	13		T3	2
valid_sources[0x75]	3147	1			T1	2		T2	11		T7	6
valid_sources[0x76]	6771	1			T1	7		T2	15		T7	12
valid_sources[0x77]	3567	1			T2	9		T7	8		T8	8
valid_sources[0x78]	6149	1			T1	2		T2	4		T3	1
valid_sources[0x79]	5011	1			T1	1		T2	18		T3	1
valid_sources[0x7a]	3334	1			T1	2		T2	13		T7	10
valid_sources[0x7b]	3343	1			T1	2		T2	14		T7	11
valid_sources[0x7c]	3437	1			T2	21		T7	10		T8	11
valid_sources[0x7d]	5935	1			T1	5		T2	8		T7	15
valid_sources[0x7e]	3721	1			T1	1		T2	10		T7	4
valid_sources[0x7f]	4569	1			T1	2		T2	14		T3	3
valid_sources[0x80]	3333	1			T2	16		T7	18		T8	16

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

255395

1

T1

74

T2

781

T3

30

values[0x0]

all_enables

biggest_size

82508

1

T1

31

T2

207

T3

12

values[0x1]

all_enables

biggest_size

44243

1

T1

16

T2

107

T3

6