Line Coverage for Module :
rv_dm
| Line No. | Total | Covered | Percent |
TOTAL | | 15 | 15 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
CONT_ASSIGN | 110 | 1 | 1 | 100.00 |
CONT_ASSIGN | 115 | 1 | 1 | 100.00 |
CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
CONT_ASSIGN | 141 | 1 | 1 | 100.00 |
CONT_ASSIGN | 206 | 1 | 1 | 100.00 |
CONT_ASSIGN | 207 | 1 | 1 | 100.00 |
CONT_ASSIGN | 211 | 1 | 1 | 100.00 |
CONT_ASSIGN | 294 | 1 | 1 | 100.00 |
CONT_ASSIGN | 300 | 1 | 1 | 100.00 |
CONT_ASSIGN | 302 | 1 | 1 | 100.00 |
CONT_ASSIGN | 308 | 1 | 1 | 100.00 |
CONT_ASSIGN | 309 | 1 | 1 | 100.00 |
CONT_ASSIGN | 384 | 1 | 1 | 100.00 |
CONT_ASSIGN | 412 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rv_dm_0.1/rtl/rv_dm.sv' or '../src/lowrisc_ip_rv_dm_0.1/rtl/rv_dm.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
109 |
1 |
1 |
110 |
1 |
1 |
115 |
1 |
1 |
118 |
1 |
1 |
141 |
1 |
1 |
206 |
1 |
1 |
207 |
1 |
1 |
211 |
1 |
1 |
294 |
1 |
1 |
300 |
1 |
1 |
302 |
1 |
1 |
308 |
1 |
1 |
309 |
1 |
1 |
384 |
1 |
1 |
412 |
1 |
1 |
Cond Coverage for Module :
rv_dm
| Total | Covered | Percent |
Conditions | 29 | 22 | 75.86 |
Logical | 29 | 22 | 75.86 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 115
EXPRESSION (regs_intg_error | rom_intg_error | sba_gate_intg_error | rom_gate_intg_error)
-------1------- -------2------ ---------3--------- ---------4---------
-1- | -2- | -3- | -4- | Status | Tests |
0 | 0 | 0 | 0 | Covered | T1,T2,T3 |
0 | 0 | 0 | 1 | Not Covered | |
0 | 0 | 1 | 0 | Not Covered | |
0 | 1 | 0 | 0 | Not Covered | |
1 | 0 | 0 | 0 | Covered | T35,T36,T37 |
LINE 118
SUB-EXPRESSION (regs_reg2hw.alert_test.q & regs_reg2hw.alert_test.qe)
------------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T33,T34 |
1 | 0 | Covered | T1,T2,T14 |
1 | 1 | Covered | T33,T34,T47 |
LINE 207
EXPRESSION (ndmreset_req_qual & reset_req_en)
--------1-------- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T9,T20 |
LINE 302
EXPRESSION (debug_req & debug_req_en)
----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T9,T7,T66 |
LINE 337
EXPRESSION (dmi_req_ready & dmi_en)
------1------ ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T5,T31,T32 |
1 | 1 | Covered | T1,T2,T3 |
LINE 337
EXPRESSION (dmi_rsp_valid & dmi_en)
------1------ ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 412
EXPRESSION (device_we || device_re)
----1---- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T20,T7 |
1 | 0 | Covered | T1,T19,T20 |
LINE 428
EXPRESSION (dmi_req_valid & dmi_en)
------1------ ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 428
EXPRESSION (dmi_rsp_ready & dmi_en)
------1------ ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T5,T31,T32 |
1 | 1 | Covered | T1,T2,T3 |
Toggle Coverage for Module :
rv_dm
| Total | Covered | Percent |
Totals |
94 |
75 |
79.79 |
Total Bits |
1112 |
1018 |
91.55 |
Total Bits 0->1 |
556 |
509 |
91.55 |
Total Bits 1->0 |
556 |
509 |
91.55 |
| | | |
Ports |
94 |
75 |
79.79 |
Port Bits |
1112 |
1018 |
91.55 |
Port Bits 0->1 |
556 |
509 |
91.55 |
Port Bits 1->0 |
556 |
509 |
91.55 |
Port Details
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
rst_ni |
Yes |
Yes |
T12,T14,T15 |
Yes |
T1,T2,T3 |
INPUT |
lc_hw_debug_en_i[3:0] |
Yes |
Yes |
T31,T32,T5 |
Yes |
T5,T31,T16 |
INPUT |
pinmux_hw_debug_en_i[3:0] |
Yes |
Yes |
T31,T32,T5 |
Yes |
T5,T31,T16 |
INPUT |
scanmode_i[0] |
No |
No |
|
Yes |
T5 |
INPUT |
scanmode_i[2:1] |
No |
Yes |
T5 |
No |
|
INPUT |
scanmode_i[3] |
No |
No |
|
Yes |
T5 |
INPUT |
scan_rst_ni |
Yes |
Yes |
T12,T14,T15 |
Yes |
T1,T2,T3 |
INPUT |
ndmreset_req_o |
Yes |
Yes |
T1,T9,T20 |
Yes |
T1,T9,T20 |
OUTPUT |
dmactive_o |
Yes |
Yes |
T9,T12,T14 |
Yes |
T1,T2,T3 |
OUTPUT |
debug_req_o |
Yes |
Yes |
T9,T7,T66 |
Yes |
T9,T7,T66 |
OUTPUT |
unavailable_i |
Yes |
Yes |
T1,T9,T21 |
Yes |
T1,T9,T10 |
INPUT |
regs_tl_d_i.d_ready |
Yes |
Yes |
T2,T3,T11 |
Yes |
T1,T2,T3 |
INPUT |
regs_tl_d_i.a_user.data_intg[6:0] |
Yes |
Yes |
T2,T14,T29 |
Yes |
T2,T14,T29 |
INPUT |
regs_tl_d_i.a_user.cmd_intg[6:0] |
Yes |
Yes |
T14,T29,T54 |
Yes |
T1,T2,T14 |
INPUT |
regs_tl_d_i.a_user.instr_type[3:0] |
Yes |
Yes |
T14,T29,T54 |
Yes |
T2,T14,T29 |
INPUT |
regs_tl_d_i.a_user.rsvd[4:0] |
Yes |
Yes |
T1,T14,T29 |
Yes |
T14,T29,T54 |
INPUT |
regs_tl_d_i.a_data[31:0] |
Yes |
Yes |
T2,T14,T29 |
Yes |
T1,T2,T14 |
INPUT |
regs_tl_d_i.a_mask[3:0] |
Yes |
Yes |
T2,T14,T29 |
Yes |
T2,T14,T29 |
INPUT |
regs_tl_d_i.a_address[31:0] |
Yes |
Yes |
T2,T14,T29 |
Yes |
T2,T14,T29 |
INPUT |
regs_tl_d_i.a_source[7:0] |
Yes |
Yes |
T14,T29,T54 |
Yes |
T2,T14,T29 |
INPUT |
regs_tl_d_i.a_size[1:0] |
Yes |
Yes |
T14,T29,T54 |
Yes |
T2,T14,T29 |
INPUT |
regs_tl_d_i.a_param[2:0] |
Yes |
Yes |
T2,T14,T29 |
Yes |
T2,T14,T29 |
INPUT |
regs_tl_d_i.a_opcode[2:0] |
Yes |
Yes |
T2,T14,T29 |
Yes |
T2,T14,T29 |
INPUT |
regs_tl_d_i.a_valid |
Yes |
Yes |
T2,T33,T34 |
Yes |
T2,T33,T34 |
INPUT |
regs_tl_d_o.a_ready |
Yes |
Yes |
T2,T33,T34 |
Yes |
T2,T33,T34 |
OUTPUT |
regs_tl_d_o.d_error |
Yes |
Yes |
T46,T55,T42 |
Yes |
T41,T46,T55 |
OUTPUT |
regs_tl_d_o.d_user.data_intg[6:0] |
No |
No |
|
No |
|
OUTPUT |
regs_tl_d_o.d_user.rsp_intg[5:0] |
Yes |
Yes |
*T33,*T34,*T47 |
Yes |
T2,T33,T34 |
OUTPUT |
regs_tl_d_o.d_user.rsp_intg[6] |
No |
No |
|
No |
|
OUTPUT |
regs_tl_d_o.d_data[31:0] |
Yes |
Yes |
T44,T45,T46 |
Yes |
T2,T33,T34 |
OUTPUT |
regs_tl_d_o.d_sink |
No |
No |
|
No |
|
OUTPUT |
regs_tl_d_o.d_source[7:0] |
Yes |
Yes |
T47,T48,T50 |
Yes |
T33,T47,T48 |
OUTPUT |
regs_tl_d_o.d_size[1:0] |
Yes |
Yes |
T33,T34,T47 |
Yes |
T2,T33,T34 |
OUTPUT |
regs_tl_d_o.d_param[2:0] |
No |
No |
|
No |
|
OUTPUT |
regs_tl_d_o.d_opcode[0] |
Yes |
Yes |
*T41,*T44,*T45 |
Yes |
T41,T44,T45 |
OUTPUT |
regs_tl_d_o.d_opcode[2:1] |
No |
No |
|
No |
|
OUTPUT |
regs_tl_d_o.d_valid |
Yes |
Yes |
T2,T33,T34 |
Yes |
T2,T33,T34 |
OUTPUT |
mem_tl_d_i.d_ready |
Yes |
Yes |
T2,T3,T11 |
Yes |
T1,T2,T3 |
INPUT |
mem_tl_d_i.a_user.data_intg[6:0] |
Yes |
Yes |
T1,T17,T19 |
Yes |
T1,T11,T34 |
INPUT |
mem_tl_d_i.a_user.cmd_intg[6:0] |
Yes |
Yes |
T1,T3,T70 |
Yes |
T1,T11,T20 |
INPUT |
mem_tl_d_i.a_user.instr_type[3:0] |
Yes |
Yes |
T33,T17,T4 |
Yes |
T34,T70,T48 |
INPUT |
mem_tl_d_i.a_user.rsvd[4:0] |
Yes |
Yes |
T11,T4,T36 |
Yes |
T3,T34,T70 |
INPUT |
mem_tl_d_i.a_data[31:0] |
Yes |
Yes |
T1,T11,T34 |
Yes |
T1,T33,T20 |
INPUT |
mem_tl_d_i.a_mask[3:0] |
Yes |
Yes |
T1,T3,T33 |
Yes |
T1,T70,T17 |
INPUT |
mem_tl_d_i.a_address[31:0] |
Yes |
Yes |
T1,T3,T34 |
Yes |
T1,T70,T71 |
INPUT |
mem_tl_d_i.a_source[7:0] |
Yes |
Yes |
T1,T34,T71 |
Yes |
T3,T33,T70 |
INPUT |
mem_tl_d_i.a_size[1:0] |
Yes |
Yes |
T11,T33,T20 |
Yes |
T20,T7,T4 |
INPUT |
mem_tl_d_i.a_param[2:0] |
Yes |
Yes |
T70,T17,T48 |
Yes |
T11,T34,T4 |
INPUT |
mem_tl_d_i.a_opcode[2:0] |
Yes |
Yes |
T1,T70,T20 |
Yes |
T1,T11,T34 |
INPUT |
mem_tl_d_i.a_valid |
Yes |
Yes |
T1,T19,T20 |
Yes |
T1,T19,T20 |
INPUT |
mem_tl_d_o.a_ready |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
mem_tl_d_o.d_error |
Yes |
Yes |
T1,T2,T3 |
Yes |
T12,T14,T15 |
OUTPUT |
mem_tl_d_o.d_user.data_intg[6:0] |
Yes |
Yes |
T1,T20,T7 |
Yes |
T1,T20,T7 |
OUTPUT |
mem_tl_d_o.d_user.rsp_intg[5:0] |
Yes |
Yes |
*T1,*T20,*T7 |
Yes |
T1,T19,T20 |
OUTPUT |
mem_tl_d_o.d_user.rsp_intg[6] |
No |
No |
|
No |
|
OUTPUT |
mem_tl_d_o.d_data[31:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T12,T14 |
OUTPUT |
mem_tl_d_o.d_sink |
No |
No |
|
No |
|
OUTPUT |
mem_tl_d_o.d_source[7:0] |
Yes |
Yes |
T1,T7,T4 |
Yes |
T1,T19,T7 |
OUTPUT |
mem_tl_d_o.d_size[1:0] |
Yes |
Yes |
T20,T7,T4 |
Yes |
T20,T7,T4 |
OUTPUT |
mem_tl_d_o.d_param[2:0] |
No |
No |
|
No |
|
OUTPUT |
mem_tl_d_o.d_opcode[0] |
Yes |
Yes |
*T1,*T2,*T3 |
Yes |
T1,T12,T14 |
OUTPUT |
mem_tl_d_o.d_opcode[2:1] |
No |
No |
|
No |
|
OUTPUT |
mem_tl_d_o.d_valid |
Yes |
Yes |
T1,T19,T20 |
Yes |
T1,T19,T20 |
OUTPUT |
sba_tl_h_o.d_ready |
Yes |
Yes |
T12,T14,T15 |
Yes |
T1,T2,T3 |
OUTPUT |
sba_tl_h_o.a_user.data_intg[6:0] |
Yes |
Yes |
T3,T11,T12 |
Yes |
T3,T11,T12 |
OUTPUT |
sba_tl_h_o.a_user.cmd_intg[6:0] |
Yes |
Yes |
T3,T11,T12 |
Yes |
T1,T2,T3 |
OUTPUT |
sba_tl_h_o.a_user.instr_type[0] |
Yes |
Yes |
*T12,*T14,*T15 |
Yes |
T1,T2,T3 |
OUTPUT |
sba_tl_h_o.a_user.instr_type[2:1] |
No |
No |
|
No |
|
OUTPUT |
sba_tl_h_o.a_user.instr_type[3] |
Yes |
Yes |
T12,T14,T15 |
Yes |
T1,T2,T3 |
OUTPUT |
sba_tl_h_o.a_user.rsvd[4:0] |
No |
No |
|
No |
|
OUTPUT |
sba_tl_h_o.a_data[31:0] |
Yes |
Yes |
T3,T11,T12 |
Yes |
T3,T11,T12 |
OUTPUT |
sba_tl_h_o.a_mask[3:0] |
Yes |
Yes |
T3,T11,T12 |
Yes |
T1,T2,T3 |
OUTPUT |
sba_tl_h_o.a_address[1:0] |
No |
No |
|
No |
|
OUTPUT |
sba_tl_h_o.a_address[31:2] |
Yes |
Yes |
T3,T11,T12 |
Yes |
T3,T11,T12 |
OUTPUT |
sba_tl_h_o.a_source[7:0] |
No |
No |
|
No |
|
OUTPUT |
sba_tl_h_o.a_size[0] |
No |
No |
|
No |
|
OUTPUT |
sba_tl_h_o.a_size[1] |
Yes |
Yes |
T12,T14,T15 |
Yes |
T1,T2,T3 |
OUTPUT |
sba_tl_h_o.a_param[2:0] |
No |
No |
|
No |
|
OUTPUT |
sba_tl_h_o.a_opcode[0] |
Yes |
Yes |
*T3,*T11,*T12 |
Yes |
T3,T11,T12 |
OUTPUT |
sba_tl_h_o.a_opcode[1] |
No |
No |
|
No |
|
OUTPUT |
sba_tl_h_o.a_opcode[2] |
Yes |
Yes |
T3,T11,T12 |
Yes |
T1,T2,T3 |
OUTPUT |
sba_tl_h_o.a_valid |
Yes |
Yes |
T3,T11,T12 |
Yes |
T3,T11,T12 |
OUTPUT |
sba_tl_h_i.a_ready |
Yes |
Yes |
T2,T3,T11 |
Yes |
T1,T2,T3 |
INPUT |
sba_tl_h_i.d_error |
Yes |
Yes |
T3,T11,T12 |
Yes |
T3,T11,T12 |
INPUT |
sba_tl_h_i.d_user.data_intg[6:0] |
Yes |
Yes |
T3,T11,T12 |
Yes |
T2,T3,T11 |
INPUT |
sba_tl_h_i.d_user.rsp_intg[6:0] |
Yes |
Yes |
T1,T3,T11 |
Yes |
T3,T11,T12 |
INPUT |
sba_tl_h_i.d_data[31:0] |
Yes |
Yes |
T3,T11,T12 |
Yes |
T3,T11,T12 |
INPUT |
sba_tl_h_i.d_sink |
Yes |
Yes |
T3,T11,T12 |
Yes |
T1,T3,T11 |
INPUT |
sba_tl_h_i.d_source[7:0] |
Yes |
Yes |
T3,T11,T15 |
Yes |
T2,T3,T11 |
INPUT |
sba_tl_h_i.d_size[1:0] |
Yes |
Yes |
T1,T3,T11 |
Yes |
T3,T11,T12 |
INPUT |
sba_tl_h_i.d_param[2:0] |
Yes |
Yes |
T3,T11,T15 |
Yes |
T1,T3,T11 |
INPUT |
sba_tl_h_i.d_opcode[2:0] |
Yes |
Yes |
T2,T3,T11 |
Yes |
T3,T11,T12 |
INPUT |
sba_tl_h_i.d_valid |
Yes |
Yes |
T3,T11,T12 |
Yes |
T3,T11,T12 |
INPUT |
alert_rx_i[0].ack_n |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
alert_rx_i[0].ack_p |
Yes |
Yes |
T33,T34,T47 |
Yes |
T33,T34,T47 |
INPUT |
alert_rx_i[0].ping_n |
No |
No |
|
No |
|
INPUT |
alert_rx_i[0].ping_p |
No |
No |
|
No |
|
INPUT |
alert_tx_o[0].alert_n |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
alert_tx_o[0].alert_p |
Yes |
Yes |
T33,T34,T47 |
Yes |
T33,T34,T47 |
OUTPUT |
jtag_i.tdi |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
jtag_i.trst_n |
Yes |
Yes |
T12,T14,T15 |
Yes |
T1,T2,T3 |
INPUT |
jtag_i.tms |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
jtag_i.tck |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
jtag_o.tdo_oe |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
jtag_o.tdo |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
*Tests covering at least one bit in the range
Assert Coverage for Module :
rv_dm
Assertion Details
DebugReqOKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
25366898 |
25330786 |
0 |
0 |
T1 |
7541 |
7489 |
0 |
0 |
T2 |
1190 |
1140 |
0 |
0 |
T3 |
30351 |
30295 |
0 |
0 |
T9 |
31080 |
31023 |
0 |
0 |
T11 |
54606 |
54542 |
0 |
0 |
T12 |
109397 |
109315 |
0 |
0 |
T14 |
448784 |
448149 |
0 |
0 |
T15 |
194299 |
193583 |
0 |
0 |
T28 |
23260 |
23201 |
0 |
0 |
T29 |
358816 |
358208 |
0 |
0 |
DmactiveOKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
25366898 |
25330786 |
0 |
0 |
T1 |
7541 |
7489 |
0 |
0 |
T2 |
1190 |
1140 |
0 |
0 |
T3 |
30351 |
30295 |
0 |
0 |
T9 |
31080 |
31023 |
0 |
0 |
T11 |
54606 |
54542 |
0 |
0 |
T12 |
109397 |
109315 |
0 |
0 |
T14 |
448784 |
448149 |
0 |
0 |
T15 |
194299 |
193583 |
0 |
0 |
T28 |
23260 |
23201 |
0 |
0 |
T29 |
358816 |
358208 |
0 |
0 |
FpvSecCmRegWeOnehotCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
25366898 |
70 |
0 |
0 |
T6 |
28470 |
0 |
0 |
0 |
T22 |
180269 |
0 |
0 |
0 |
T35 |
6760 |
20 |
0 |
0 |
T36 |
5359 |
10 |
0 |
0 |
T37 |
0 |
10 |
0 |
0 |
T72 |
0 |
20 |
0 |
0 |
T73 |
0 |
10 |
0 |
0 |
T74 |
1030 |
0 |
0 |
0 |
T75 |
1282 |
0 |
0 |
0 |
T76 |
26520 |
0 |
0 |
0 |
T77 |
1590 |
0 |
0 |
0 |
T78 |
6071 |
0 |
0 |
0 |
T79 |
1482 |
0 |
0 |
0 |
FpvSecCmRomTlLcGateFsm_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
25366898 |
0 |
0 |
0 |
FpvSecCmSbaTlLcGateFsm_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
25366898 |
0 |
0 |
0 |
JtagRspOTdoKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
13622367 |
13622047 |
0 |
0 |
T1 |
2606 |
2606 |
0 |
0 |
T2 |
148 |
148 |
0 |
0 |
T3 |
62013 |
62013 |
0 |
0 |
T9 |
3989 |
3989 |
0 |
0 |
T11 |
170439 |
170439 |
0 |
0 |
T12 |
114570 |
114560 |
0 |
0 |
T14 |
79757 |
79749 |
0 |
0 |
T15 |
376531 |
376521 |
0 |
0 |
T28 |
41770 |
41770 |
0 |
0 |
T29 |
49816 |
49807 |
0 |
0 |
JtagRspOTdoOeKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
13622367 |
13622047 |
0 |
0 |
T1 |
2606 |
2606 |
0 |
0 |
T2 |
148 |
148 |
0 |
0 |
T3 |
62013 |
62013 |
0 |
0 |
T9 |
3989 |
3989 |
0 |
0 |
T11 |
170439 |
170439 |
0 |
0 |
T12 |
114570 |
114560 |
0 |
0 |
T14 |
79757 |
79749 |
0 |
0 |
T15 |
376531 |
376521 |
0 |
0 |
T28 |
41770 |
41770 |
0 |
0 |
T29 |
49816 |
49807 |
0 |
0 |
NdmresetOKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
25366898 |
25330786 |
0 |
0 |
T1 |
7541 |
7489 |
0 |
0 |
T2 |
1190 |
1140 |
0 |
0 |
T3 |
30351 |
30295 |
0 |
0 |
T9 |
31080 |
31023 |
0 |
0 |
T11 |
54606 |
54542 |
0 |
0 |
T12 |
109397 |
109315 |
0 |
0 |
T14 |
448784 |
448149 |
0 |
0 |
T15 |
194299 |
193583 |
0 |
0 |
T28 |
23260 |
23201 |
0 |
0 |
T29 |
358816 |
358208 |
0 |
0 |
RvDmLcEnDebugVal_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
25366898 |
25330786 |
0 |
0 |
T1 |
7541 |
7489 |
0 |
0 |
T2 |
1190 |
1140 |
0 |
0 |
T3 |
30351 |
30295 |
0 |
0 |
T9 |
31080 |
31023 |
0 |
0 |
T11 |
54606 |
54542 |
0 |
0 |
T12 |
109397 |
109315 |
0 |
0 |
T14 |
448784 |
448149 |
0 |
0 |
T15 |
194299 |
193583 |
0 |
0 |
T28 |
23260 |
23201 |
0 |
0 |
T29 |
358816 |
358208 |
0 |
0 |
TlMemAReadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
25366898 |
25330786 |
0 |
0 |
T1 |
7541 |
7489 |
0 |
0 |
T2 |
1190 |
1140 |
0 |
0 |
T3 |
30351 |
30295 |
0 |
0 |
T9 |
31080 |
31023 |
0 |
0 |
T11 |
54606 |
54542 |
0 |
0 |
T12 |
109397 |
109315 |
0 |
0 |
T14 |
448784 |
448149 |
0 |
0 |
T15 |
194299 |
193583 |
0 |
0 |
T28 |
23260 |
23201 |
0 |
0 |
T29 |
358816 |
358208 |
0 |
0 |
TlMemDValidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
25366898 |
25330786 |
0 |
0 |
T1 |
7541 |
7489 |
0 |
0 |
T2 |
1190 |
1140 |
0 |
0 |
T3 |
30351 |
30295 |
0 |
0 |
T9 |
31080 |
31023 |
0 |
0 |
T11 |
54606 |
54542 |
0 |
0 |
T12 |
109397 |
109315 |
0 |
0 |
T14 |
448784 |
448149 |
0 |
0 |
T15 |
194299 |
193583 |
0 |
0 |
T28 |
23260 |
23201 |
0 |
0 |
T29 |
358816 |
358208 |
0 |
0 |
TlRegsAReadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
25366898 |
25330786 |
0 |
0 |
T1 |
7541 |
7489 |
0 |
0 |
T2 |
1190 |
1140 |
0 |
0 |
T3 |
30351 |
30295 |
0 |
0 |
T9 |
31080 |
31023 |
0 |
0 |
T11 |
54606 |
54542 |
0 |
0 |
T12 |
109397 |
109315 |
0 |
0 |
T14 |
448784 |
448149 |
0 |
0 |
T15 |
194299 |
193583 |
0 |
0 |
T28 |
23260 |
23201 |
0 |
0 |
T29 |
358816 |
358208 |
0 |
0 |
TlRegsDValidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
25366898 |
25330786 |
0 |
0 |
T1 |
7541 |
7489 |
0 |
0 |
T2 |
1190 |
1140 |
0 |
0 |
T3 |
30351 |
30295 |
0 |
0 |
T9 |
31080 |
31023 |
0 |
0 |
T11 |
54606 |
54542 |
0 |
0 |
T12 |
109397 |
109315 |
0 |
0 |
T14 |
448784 |
448149 |
0 |
0 |
T15 |
194299 |
193583 |
0 |
0 |
T28 |
23260 |
23201 |
0 |
0 |
T29 |
358816 |
358208 |
0 |
0 |
TlSbaAValidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
25366898 |
25330786 |
0 |
0 |
T1 |
7541 |
7489 |
0 |
0 |
T2 |
1190 |
1140 |
0 |
0 |
T3 |
30351 |
30295 |
0 |
0 |
T9 |
31080 |
31023 |
0 |
0 |
T11 |
54606 |
54542 |
0 |
0 |
T12 |
109397 |
109315 |
0 |
0 |
T14 |
448784 |
448149 |
0 |
0 |
T15 |
194299 |
193583 |
0 |
0 |
T28 |
23260 |
23201 |
0 |
0 |
T29 |
358816 |
358208 |
0 |
0 |
TlSbaDReadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
25366898 |
25330786 |
0 |
0 |
T1 |
7541 |
7489 |
0 |
0 |
T2 |
1190 |
1140 |
0 |
0 |
T3 |
30351 |
30295 |
0 |
0 |
T9 |
31080 |
31023 |
0 |
0 |
T11 |
54606 |
54542 |
0 |
0 |
T12 |
109397 |
109315 |
0 |
0 |
T14 |
448784 |
448149 |
0 |
0 |
T15 |
194299 |
193583 |
0 |
0 |
T28 |
23260 |
23201 |
0 |
0 |
T29 |
358816 |
358208 |
0 |
0 |
paramCheckNrHarts
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
151 |
151 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T14 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
T29 |
1 |
1 |
0 |
0 |