SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_lc_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_pm_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_tlul_lc_gate_sba.u_err_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_tlul_lc_gate_rom.u_err_en_sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
88.73 | 100.00 | 75.86 | 91.55 | 87.50 | dut |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
88.73 | 100.00 | 75.86 | 91.55 | 87.50 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
68.13 | 86.27 | 72.22 | 57.14 | 75.00 | 50.00 | u_tlul_lc_gate_sba |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
81.44 | 96.08 | 77.78 | 100.00 | 83.33 | 50.00 | u_tlul_lc_gate_rom |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 6 | 6 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 5 | 5 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 3 | 3 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 4 | 4 | 100.00 | 4 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 4 | 4 | 100.00 | 4 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 604 | 604 | 0 | 0 |
OutputsKnown_A | 101467592 | 101323144 | 0 | 0 |
gen_flops.OutputDelay_A | 50733796 | 50658296 | 0 | 906 |
gen_no_flops.OutputDelay_A | 50733796 | 50661572 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 604 | 604 | 0 | 0 |
T1 | 4 | 4 | 0 | 0 |
T2 | 4 | 4 | 0 | 0 |
T3 | 4 | 4 | 0 | 0 |
T9 | 4 | 4 | 0 | 0 |
T11 | 4 | 4 | 0 | 0 |
T12 | 4 | 4 | 0 | 0 |
T14 | 4 | 4 | 0 | 0 |
T15 | 4 | 4 | 0 | 0 |
T28 | 4 | 4 | 0 | 0 |
T29 | 4 | 4 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 101467592 | 101323144 | 0 | 0 |
T1 | 30164 | 29956 | 0 | 0 |
T2 | 4760 | 4560 | 0 | 0 |
T3 | 121404 | 121180 | 0 | 0 |
T9 | 124320 | 124092 | 0 | 0 |
T11 | 218424 | 218168 | 0 | 0 |
T12 | 437588 | 437260 | 0 | 0 |
T14 | 1795136 | 1792596 | 0 | 0 |
T15 | 777196 | 774332 | 0 | 0 |
T28 | 93040 | 92804 | 0 | 0 |
T29 | 1435264 | 1432832 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 50733796 | 50658296 | 0 | 906 |
T1 | 15082 | 14972 | 0 | 6 |
T2 | 2380 | 2274 | 0 | 6 |
T3 | 60702 | 60584 | 0 | 6 |
T9 | 62160 | 62040 | 0 | 6 |
T11 | 109212 | 109078 | 0 | 6 |
T12 | 218794 | 218622 | 0 | 6 |
T14 | 897568 | 896244 | 0 | 6 |
T15 | 388598 | 387100 | 0 | 6 |
T28 | 46520 | 46396 | 0 | 6 |
T29 | 717632 | 716356 | 0 | 6 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 50733796 | 50661572 | 0 | 0 |
T1 | 15082 | 14978 | 0 | 0 |
T2 | 2380 | 2280 | 0 | 0 |
T3 | 60702 | 60590 | 0 | 0 |
T9 | 62160 | 62046 | 0 | 0 |
T11 | 109212 | 109084 | 0 | 0 |
T12 | 218794 | 218630 | 0 | 0 |
T14 | 897568 | 896298 | 0 | 0 |
T15 | 388598 | 387166 | 0 | 0 |
T28 | 46520 | 46402 | 0 | 0 |
T29 | 717632 | 716416 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 6 | 6 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 5 | 5 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 151 | 151 | 0 | 0 |
OutputsKnown_A | 25366898 | 25330786 | 0 | 0 |
gen_flops.OutputDelay_A | 25366898 | 25329148 | 0 | 453 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 151 | 151 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T14 | 1 | 1 | 0 | 0 |
T15 | 1 | 1 | 0 | 0 |
T28 | 1 | 1 | 0 | 0 |
T29 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 25366898 | 25330786 | 0 | 0 |
T1 | 7541 | 7489 | 0 | 0 |
T2 | 1190 | 1140 | 0 | 0 |
T3 | 30351 | 30295 | 0 | 0 |
T9 | 31080 | 31023 | 0 | 0 |
T11 | 54606 | 54542 | 0 | 0 |
T12 | 109397 | 109315 | 0 | 0 |
T14 | 448784 | 448149 | 0 | 0 |
T15 | 194299 | 193583 | 0 | 0 |
T28 | 23260 | 23201 | 0 | 0 |
T29 | 358816 | 358208 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 25366898 | 25329148 | 0 | 453 |
T1 | 7541 | 7486 | 0 | 3 |
T2 | 1190 | 1137 | 0 | 3 |
T3 | 30351 | 30292 | 0 | 3 |
T9 | 31080 | 31020 | 0 | 3 |
T11 | 54606 | 54539 | 0 | 3 |
T12 | 109397 | 109311 | 0 | 3 |
T14 | 448784 | 448122 | 0 | 3 |
T15 | 194299 | 193550 | 0 | 3 |
T28 | 23260 | 23198 | 0 | 3 |
T29 | 358816 | 358178 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 3 | 3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 151 | 151 | 0 | 0 |
OutputsKnown_A | 25366898 | 25330786 | 0 | 0 |
gen_flops.OutputDelay_A | 25366898 | 25329148 | 0 | 453 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 151 | 151 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T14 | 1 | 1 | 0 | 0 |
T15 | 1 | 1 | 0 | 0 |
T28 | 1 | 1 | 0 | 0 |
T29 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 25366898 | 25330786 | 0 | 0 |
T1 | 7541 | 7489 | 0 | 0 |
T2 | 1190 | 1140 | 0 | 0 |
T3 | 30351 | 30295 | 0 | 0 |
T9 | 31080 | 31023 | 0 | 0 |
T11 | 54606 | 54542 | 0 | 0 |
T12 | 109397 | 109315 | 0 | 0 |
T14 | 448784 | 448149 | 0 | 0 |
T15 | 194299 | 193583 | 0 | 0 |
T28 | 23260 | 23201 | 0 | 0 |
T29 | 358816 | 358208 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 25366898 | 25329148 | 0 | 453 |
T1 | 7541 | 7486 | 0 | 3 |
T2 | 1190 | 1137 | 0 | 3 |
T3 | 30351 | 30292 | 0 | 3 |
T9 | 31080 | 31020 | 0 | 3 |
T11 | 54606 | 54539 | 0 | 3 |
T12 | 109397 | 109311 | 0 | 3 |
T14 | 448784 | 448122 | 0 | 3 |
T15 | 194299 | 193550 | 0 | 3 |
T28 | 23260 | 23198 | 0 | 3 |
T29 | 358816 | 358178 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 151 | 151 | 0 | 0 |
OutputsKnown_A | 25366898 | 25330786 | 0 | 0 |
gen_no_flops.OutputDelay_A | 25366898 | 25330786 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 151 | 151 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T14 | 1 | 1 | 0 | 0 |
T15 | 1 | 1 | 0 | 0 |
T28 | 1 | 1 | 0 | 0 |
T29 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 25366898 | 25330786 | 0 | 0 |
T1 | 7541 | 7489 | 0 | 0 |
T2 | 1190 | 1140 | 0 | 0 |
T3 | 30351 | 30295 | 0 | 0 |
T9 | 31080 | 31023 | 0 | 0 |
T11 | 54606 | 54542 | 0 | 0 |
T12 | 109397 | 109315 | 0 | 0 |
T14 | 448784 | 448149 | 0 | 0 |
T15 | 194299 | 193583 | 0 | 0 |
T28 | 23260 | 23201 | 0 | 0 |
T29 | 358816 | 358208 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 25366898 | 25330786 | 0 | 0 |
T1 | 7541 | 7489 | 0 | 0 |
T2 | 1190 | 1140 | 0 | 0 |
T3 | 30351 | 30295 | 0 | 0 |
T9 | 31080 | 31023 | 0 | 0 |
T11 | 54606 | 54542 | 0 | 0 |
T12 | 109397 | 109315 | 0 | 0 |
T14 | 448784 | 448149 | 0 | 0 |
T15 | 194299 | 193583 | 0 | 0 |
T28 | 23260 | 23201 | 0 | 0 |
T29 | 358816 | 358208 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 151 | 151 | 0 | 0 |
OutputsKnown_A | 25366898 | 25330786 | 0 | 0 |
gen_no_flops.OutputDelay_A | 25366898 | 25330786 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 151 | 151 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T14 | 1 | 1 | 0 | 0 |
T15 | 1 | 1 | 0 | 0 |
T28 | 1 | 1 | 0 | 0 |
T29 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 25366898 | 25330786 | 0 | 0 |
T1 | 7541 | 7489 | 0 | 0 |
T2 | 1190 | 1140 | 0 | 0 |
T3 | 30351 | 30295 | 0 | 0 |
T9 | 31080 | 31023 | 0 | 0 |
T11 | 54606 | 54542 | 0 | 0 |
T12 | 109397 | 109315 | 0 | 0 |
T14 | 448784 | 448149 | 0 | 0 |
T15 | 194299 | 193583 | 0 | 0 |
T28 | 23260 | 23201 | 0 | 0 |
T29 | 358816 | 358208 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 25366898 | 25330786 | 0 | 0 |
T1 | 7541 | 7489 | 0 | 0 |
T2 | 1190 | 1140 | 0 | 0 |
T3 | 30351 | 30295 | 0 | 0 |
T9 | 31080 | 31023 | 0 | 0 |
T11 | 54606 | 54542 | 0 | 0 |
T12 | 109397 | 109315 | 0 | 0 |
T14 | 448784 | 448149 | 0 | 0 |
T15 | 194299 | 193583 | 0 | 0 |
T28 | 23260 | 23201 | 0 | 0 |
T29 | 358816 | 358208 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |