Module Definition
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Module : rv_dm_regs_reg_top
SCORELINECONDTOGGLEFSMBRANCHASSERT
82.14 75.00 82.14 71.43 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_rv_dm_0.1/rtl/rv_dm_regs_reg_top.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_reg_regs 82.14 75.00 82.14 71.43 100.00



Module Instance : tb.dut.u_reg_regs

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
82.14 75.00 82.14 71.43 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.73 93.50 93.58 93.49 93.10 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
89.59 100.00 79.31 91.55 87.50 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_alert_test 100.00 100.00
u_chk 97.78 100.00 93.33 100.00
u_prim_reg_we_check 100.00 100.00 100.00
u_reg_if 98.66 97.10 97.53 100.00 100.00
u_rsp_intg_gen 100.00 100.00 100.00


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : rv_dm_regs_reg_top
Line No.TotalCoveredPercent
TOTAL241875.00
ALWAYS6744100.00
CONT_ASSIGN7611100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN8911100.00
CONT_ASSIGN117100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN13011100.00
CONT_ASSIGN14411100.00
ALWAYS150200.00
CONT_ASSIGN15411100.00
ALWAYS15811100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16511100.00
ALWAYS16922100.00
ALWAYS175300.00
CONT_ASSIGN19200
CONT_ASSIGN20011100.00
CONT_ASSIGN20111100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rv_dm_0.1/rtl/rv_dm_regs_reg_top.sv' or '../src/lowrisc_ip_rv_dm_0.1/rtl/rv_dm_regs_reg_top.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
67 1 1
68 1 1
69 1 1
70 1 1
MISSING_ELSE
76 1 1
88 1 1
89 1 1
117 0 1
118 1 1
130 1 1
144 1 1
150 0 1
151 0 1
154 1 1
158 1 1
163 1 1
165 1 1
169 1 1
170 1 1
175 0 1
176 0 1
178 0 1
192 unreachable
200 1 1
201 1 1


Cond Coverage for Module : rv_dm_regs_reg_top
TotalCoveredPercent
Conditions282382.14
Logical282382.14
Non-Logical00
Event00

 LINE       57
 EXPRESSION (reg_we && ((!addrmiss)))
             ---1--    ------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT2,T29,T36

 LINE       69
 EXPRESSION (intg_err || reg_we_err)
             ----1---    -----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT37,T38,T39
10CoveredT40,T41,T42

 LINE       76
 EXPRESSION (err_q | intg_err | reg_we_err)
             --1--   ----2---   -----3----
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT37,T38,T39
010CoveredT40,T41,T42
100CoveredT37,T38,T39

 LINE       118
 EXPRESSION (addrmiss | wr_err | intg_err)
             ----1---   ---2--   ----3---
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT40,T41,T42
010CoveredT43,T44,T45
100Not Covered

 LINE       151
 EXPRESSION (reg_addr == rv_dm_reg_pkg::RV_DM_ALERT_TEST_OFFSET)
            --------------------------1-------------------------
-1-StatusTests
0Unreachable
1Not Covered

 LINE       154
 EXPRESSION ((reg_re || reg_we) ? ((~|addr_hit)) : 1'b0)
             ---------1--------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T29,T36

 LINE       154
 SUB-EXPRESSION (reg_re || reg_we)
                 ---1--    ---2--
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T29,T36
10CoveredT40,T46,T41

 LINE       158
 EXPRESSION (reg_we & addr_hit[0] & ((|(4'b1 & (~reg_be)))))
             ---1--   -----2-----   -----------3-----------
-1--2--3-StatusTests
011CoveredT12,T29,T47
101Not Covered
110CoveredT2,T29,T36
111CoveredT43,T44,T45

 LINE       163
 EXPRESSION (addr_hit[0] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T2,T3
110CoveredT40,T41,T43
111CoveredT2,T29,T36

Branch Coverage for Module : rv_dm_regs_reg_top
Line No.TotalCoveredPercent
Branches 7 5 71.43
TERNARY 154 2 2 100.00
IF 67 3 3 100.00
CASE 176 2 0 0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_rv_dm_0.1/rtl/rv_dm_regs_reg_top.sv' or '../src/lowrisc_ip_rv_dm_0.1/rtl/rv_dm_regs_reg_top.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 154 ((reg_re || reg_we)) ?

Branches:
-1-StatusTests
1 Covered T2,T29,T36
0 Covered T1,T2,T3


LineNo. Expression -1-: 67 if ((!rst_ni)) -2-: 69 if ((intg_err || reg_we_err))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T37,T38,T39
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 176 case (1'b1)

Branches:
-1-StatusTests
addr_hit[0] Not Covered
default Not Covered


Assert Coverage for Module : rv_dm_regs_reg_top
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
en2addrHit 43828780 2997 0 0
reAfterRv 43828780 2997 0 0
rePulse 43828780 1581 0 0
wePulse 43828780 1416 0 0


en2addrHit
NameAttemptsReal SuccessesFailuresIncomplete
Total 43828780 2997 0 0
T2 1003 9 0 0
T3 130801 0 0 0
T10 8555 0 0 0
T12 645723 0 0 0
T15 58538 0 0 0
T16 147379 0 0 0
T17 101777 0 0 0
T29 1800 9 0 0
T34 109150 0 0 0
T35 96128 0 0 0
T36 0 12 0 0
T48 0 10 0 0
T49 0 1 0 0
T50 0 1 0 0
T51 0 20 0 0
T52 0 4 0 0
T53 0 3 0 0
T54 0 7 0 0

reAfterRv
NameAttemptsReal SuccessesFailuresIncomplete
Total 43828780 2997 0 0
T2 1003 9 0 0
T3 130801 0 0 0
T10 8555 0 0 0
T12 645723 0 0 0
T15 58538 0 0 0
T16 147379 0 0 0
T17 101777 0 0 0
T29 1800 9 0 0
T34 109150 0 0 0
T35 96128 0 0 0
T36 0 12 0 0
T48 0 10 0 0
T49 0 1 0 0
T50 0 1 0 0
T51 0 20 0 0
T52 0 4 0 0
T53 0 3 0 0
T54 0 7 0 0

rePulse
NameAttemptsReal SuccessesFailuresIncomplete
Total 43828780 1581 0 0
T40 95928 29 0 0
T41 43413 14 0 0
T42 0 15 0 0
T43 12208 0 0 0
T46 75450 2 0 0
T55 395032 1 0 0
T56 4547 1 0 0
T57 38410 10 0 0
T58 0 1 0 0
T59 0 1 0 0
T60 0 64 0 0
T61 14234 0 0 0
T62 12117 0 0 0
T63 638225 0 0 0

wePulse
NameAttemptsReal SuccessesFailuresIncomplete
Total 43828780 1416 0 0
T2 1003 9 0 0
T3 130801 0 0 0
T10 8555 0 0 0
T12 645723 0 0 0
T15 58538 0 0 0
T16 147379 0 0 0
T17 101777 0 0 0
T29 1800 9 0 0
T34 109150 0 0 0
T35 96128 0 0 0
T36 0 12 0 0
T48 0 10 0 0
T49 0 1 0 0
T50 0 1 0 0
T51 0 20 0 0
T52 0 4 0 0
T53 0 3 0 0
T54 0 7 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%