Unified Coverage Report :: Module :: rv_dm

Module : rv_dm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.59	100.00	79.31	91.55			87.50

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_rv_dm_0.1/rtl/rv_dm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	89.59	100.00	79.31	91.55			87.50

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.59	100.00	79.31	91.55			87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
86.46	92.60	78.70	89.36	78.21	82.12	97.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
dap	86.43	98.36	92.76		72.00	94.02	75.00
gen_alert_tx[0].u_prim_alert_sender	83.33			83.33
i_tlul_adapter_reg	93.27	99.00	80.90	93.33		93.10	100.00
rv_dm_regs_csr_assert	0.00						0.00
tl_adapter_host_sba	95.14	100.00	100.00	75.71		100.00	100.00
tlul_assert_device_mem	95.24	100.00				85.71	100.00
tlul_assert_device_regs	94.54	100.00				85.71	97.90
tlul_assert_host_sba	94.30	100.00				85.71	97.18
u_dm_top	83.79	86.18	62.43		100.00	70.32	100.00
u_lc_en_sync	100.00	100.00				100.00	100.00
u_pm_en_sync	100.00	100.00				100.00	100.00
u_prim_clock_mux2	100.00	100.00	100.00				100.00
u_prim_rst_n_mux2	100.00	100.00	100.00				100.00
u_reg_regs	94.73	93.50	93.58	93.49		93.10	100.00
u_tlul_lc_gate_rom	83.22	93.94	57.50		100.00	77.14	87.50
u_tlul_lc_gate_sba	72.24	90.15	55.00		57.14	71.43	87.50

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rv_dm

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
CONT_ASSIGN	109	1	1	100.00
CONT_ASSIGN	110	1	1	100.00
CONT_ASSIGN	115	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	206	1	1	100.00
CONT_ASSIGN	207	1	1	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	294	1	1	100.00
CONT_ASSIGN	300	1	1	100.00
CONT_ASSIGN	302	1	1	100.00
CONT_ASSIGN	308	1	1	100.00
CONT_ASSIGN	309	1	1	100.00
CONT_ASSIGN	384	1	1	100.00
CONT_ASSIGN	412	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rv_dm_0.1/rtl/rv_dm.sv' or '../src/lowrisc_ip_rv_dm_0.1/rtl/rv_dm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
109	1	1
110	1	1
115	1	1
118	1	1
141	1	1
206	1	1
207	1	1
211	1	1
294	1	1
300	1	1
302	1	1
308	1	1
309	1	1
384	1	1
412	1	1

---

Cond Coverage for Module : rv_dm

	Total	Covered	Percent
Conditions	29	23	79.31
Logical	29	23	79.31
Non-Logical	0	0
Event	0	0

 LINE       115
 EXPRESSION (regs_intg_error | rom_intg_error | sba_gate_intg_error | rom_gate_intg_error)
             -------1-------   -------2------   ---------3---------   ---------4---------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T3
0	0	0	1	Not Covered
0	0	1	0	Not Covered
0	1	0	0	Not Covered
1	0	0	0	Covered	T37,T38,T39

 LINE       118
 SUB-EXPRESSION (regs_reg2hw.alert_test.q & regs_reg2hw.alert_test.qe)
                 ------------1-----------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T29,T36
1	0	Covered	T2,T29,T36
1	1	Covered	T2,T29,T36

 LINE       207
 EXPRESSION (ndmreset_req_qual & reset_req_en)
             --------1--------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T18,T5,T20

 LINE       302
 EXPRESSION (debug_req & debug_req_en)
             ----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T32
1	1	Covered	T7,T8,T9

 LINE       337
 EXPRESSION (dmi_req_ready & dmi_en)
             ------1------   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T19,T5,T6
1	1	Covered	T1,T2,T3

 LINE       337
 EXPRESSION (dmi_rsp_valid & dmi_en)
             ------1------   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       412
 EXPRESSION (device_we || device_re)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T18,T5
1	0	Covered	T7,T8,T9

 LINE       428
 EXPRESSION (dmi_req_valid & dmi_en)
             ------1------   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       428
 EXPRESSION (dmi_rsp_ready & dmi_en)
             ------1------   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T19,T5,T6
1	1	Covered	T1,T2,T3

---

Toggle Coverage for Module : rv_dm

	Total	Covered	Percent
Totals	94	75	79.79
Total Bits	1112	1018	91.55
Total Bits 0->1	556	509	91.55
Total Bits 1->0	556	509	91.55

Ports	94	75	79.79
Port Bits	1112	1018	91.55
Port Bits 0->1	556	509	91.55
Port Bits 1->0	556	509	91.55

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T3,T16,T17	Yes	T1,T2,T3	INPUT
lc_hw_debug_en_i[3:0]	Yes	Yes	T19,T5,T6	Yes	T19,T5,T6	INPUT
pinmux_hw_debug_en_i[3:0]	Yes	Yes	T19,T5,T6	Yes	T19,T5,T6	INPUT
scanmode_i[0]	No	No		Yes	T14,T21,T32	INPUT
scanmode_i[2:1]	No	Yes	T14,T21,T32	No		INPUT
scanmode_i[3]	No	No		Yes	T14,T21,T32	INPUT
scan_rst_ni	Yes	Yes	T3,T16,T17	Yes	T1,T2,T3	INPUT
ndmreset_req_o	Yes	Yes	T18,T5,T20	Yes	T18,T5,T20	OUTPUT
dmactive_o	Yes	Yes	T1,T3,T16	Yes	T1,T2,T3	OUTPUT
debug_req_o	Yes	Yes	T7,T8,T18	Yes	T7,T8,T9	OUTPUT
unavailable_i	Yes	Yes	T10,T7,T11	Yes	T10,T11,T22	INPUT
regs_tl_d_i.d_ready	Yes	Yes	T3,T12,T29	Yes	T1,T2,T3	INPUT
regs_tl_d_i.a_user.data_intg[6:0]	Yes	Yes	T2,T29,T36	Yes	T2,T29,T36	INPUT
regs_tl_d_i.a_user.cmd_intg[6:0]	Yes	Yes	T2,T29,T36	Yes	T2,T29,T36	INPUT
regs_tl_d_i.a_user.instr_type[3:0]	Yes	Yes	T29,T47,T53	Yes	T12,T29,T53	INPUT
regs_tl_d_i.a_user.rsvd[4:0]	Yes	Yes	T29,T53,T5	Yes	T29,T53,T71	INPUT
regs_tl_d_i.a_data[31:0]	Yes	Yes	T2,T29,T36	Yes	T2,T29,T36	INPUT
regs_tl_d_i.a_mask[3:0]	Yes	Yes	T12,T29,T53	Yes	T29,T53,T22	INPUT
regs_tl_d_i.a_address[31:0]	Yes	Yes	T29,T47,T72	Yes	T29,T22,T9	INPUT
regs_tl_d_i.a_source[7:0]	Yes	Yes	T29,T36,T51	Yes	T29,T36,T48	INPUT
regs_tl_d_i.a_size[1:0]	Yes	Yes	T2,T29,T36	Yes	T2,T12,T29	INPUT
regs_tl_d_i.a_param[2:0]	Yes	Yes	T29,T53,T72	Yes	T12,T29,T47	INPUT
regs_tl_d_i.a_opcode[2:0]	Yes	Yes	T2,T29,T36	Yes	T2,T29,T36	INPUT
regs_tl_d_i.a_valid	Yes	Yes	T2,T29,T36	Yes	T2,T29,T36	INPUT
regs_tl_d_o.a_ready	Yes	Yes	T2,T29,T36	Yes	T2,T29,T36	OUTPUT
regs_tl_d_o.d_error	Yes	Yes	T40,T46,T41	Yes	T40,T46,T41	OUTPUT
regs_tl_d_o.d_user.data_intg[6:0]	No	No		No		OUTPUT
regs_tl_d_o.d_user.rsp_intg[5:0]	Yes	Yes	*T29,*T36,*T48	Yes	T2,T29,T36	OUTPUT
regs_tl_d_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
regs_tl_d_o.d_data[31:0]	Yes	Yes	T40,T46,T41	Yes	T2,T29,T36	OUTPUT
regs_tl_d_o.d_sink	No	No		No		OUTPUT
regs_tl_d_o.d_source[7:0]	Yes	Yes	T36,T51,T54	Yes	T29,T36,T48	OUTPUT
regs_tl_d_o.d_size[1:0]	Yes	Yes	T2,T29,T36	Yes	T2,T29,T36	OUTPUT
regs_tl_d_o.d_param[2:0]	No	No		No		OUTPUT
regs_tl_d_o.d_opcode[0]	Yes	Yes	*T40,*T46,*T41	Yes	T40,T46,T41	OUTPUT
regs_tl_d_o.d_opcode[2:1]	No	No		No		OUTPUT
regs_tl_d_o.d_valid	Yes	Yes	T2,T29,T36	Yes	T2,T29,T36	OUTPUT
mem_tl_d_i.d_ready	Yes	Yes	T3,T12,T29	Yes	T1,T2,T3	INPUT
mem_tl_d_i.a_user.data_intg[6:0]	Yes	Yes	T2,T16,T69	Yes	T16,T36,T69	INPUT
mem_tl_d_i.a_user.cmd_intg[6:0]	Yes	Yes	T15,T16,T69	Yes	T29,T16,T48	INPUT
mem_tl_d_i.a_user.instr_type[3:0]	Yes	Yes	T2,T29,T16	Yes	T15,T16,T69	INPUT
mem_tl_d_i.a_user.rsvd[4:0]	Yes	Yes	T16,T36,T69	Yes	T2,T15,T16	INPUT
mem_tl_d_i.a_data[31:0]	Yes	Yes	T16,T69,T37	Yes	T29,T16,T70	INPUT
mem_tl_d_i.a_mask[3:0]	Yes	Yes	T15,T16,T36	Yes	T29,T16,T69	INPUT
mem_tl_d_i.a_address[31:0]	Yes	Yes	T16,T69,T37	Yes	T2,T16,T70	INPUT
mem_tl_d_i.a_source[7:0]	Yes	Yes	T16,T69,T7	Yes	T2,T29,T16	INPUT
mem_tl_d_i.a_size[1:0]	Yes	Yes	T16,T69,T7	Yes	T2,T16,T69	INPUT
mem_tl_d_i.a_param[2:0]	Yes	Yes	T15,T16,T36	Yes	T29,T16,T70	INPUT
mem_tl_d_i.a_opcode[2:0]	Yes	Yes	T16,T69,T7	Yes	T2,T29,T16	INPUT
mem_tl_d_i.a_valid	Yes	Yes	T7,T8,T9	Yes	T7,T8,T9	INPUT
mem_tl_d_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mem_tl_d_o.d_error	Yes	Yes	T1,T2,T3	Yes	T3,T16,T17	OUTPUT
mem_tl_d_o.d_user.data_intg[6:0]	Yes	Yes	T8,T18,T5	Yes	T8,T18,T5	OUTPUT
mem_tl_d_o.d_user.rsp_intg[5:0]	Yes	Yes	*T7,*T8,*T9	Yes	T7,T8,T9	OUTPUT
mem_tl_d_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
mem_tl_d_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T3,T16,T17	OUTPUT
mem_tl_d_o.d_sink	No	No		No		OUTPUT
mem_tl_d_o.d_source[7:0]	Yes	Yes	T7,T9,T18	Yes	T7,T9,T4	OUTPUT
mem_tl_d_o.d_size[1:0]	Yes	Yes	T7,T8,T9	Yes	T7,T8,T9	OUTPUT
mem_tl_d_o.d_param[2:0]	No	No		No		OUTPUT
mem_tl_d_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T3,T16,T17	OUTPUT
mem_tl_d_o.d_opcode[2:1]	No	No		No		OUTPUT
mem_tl_d_o.d_valid	Yes	Yes	T7,T8,T9	Yes	T7,T8,T9	OUTPUT
sba_tl_h_o.d_ready	Yes	Yes	T3,T16,T17	Yes	T1,T2,T3	OUTPUT
sba_tl_h_o.a_user.data_intg[6:0]	Yes	Yes	T3,T12,T15	Yes	T3,T12,T15	OUTPUT
sba_tl_h_o.a_user.cmd_intg[6:0]	Yes	Yes	T3,T12,T15	Yes	T1,T2,T3	OUTPUT
sba_tl_h_o.a_user.instr_type[0]	Yes	Yes	*T3,*T16,*T17	Yes	T1,T2,T3	OUTPUT
sba_tl_h_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
sba_tl_h_o.a_user.instr_type[3]	Yes	Yes	T3,T16,T17	Yes	T1,T2,T3	OUTPUT
sba_tl_h_o.a_user.rsvd[4:0]	No	No		No		OUTPUT
sba_tl_h_o.a_data[31:0]	Yes	Yes	T3,T12,T15	Yes	T3,T12,T15	OUTPUT
sba_tl_h_o.a_mask[3:0]	Yes	Yes	T3,T12,T15	Yes	T1,T2,T3	OUTPUT
sba_tl_h_o.a_address[1:0]	No	No		No		OUTPUT
sba_tl_h_o.a_address[31:2]	Yes	Yes	T3,T12,T15	Yes	T3,T12,T15	OUTPUT
sba_tl_h_o.a_source[7:0]	No	No		No		OUTPUT
sba_tl_h_o.a_size[0]	No	No		No		OUTPUT
sba_tl_h_o.a_size[1]	Yes	Yes	T3,T16,T17	Yes	T1,T2,T3	OUTPUT
sba_tl_h_o.a_param[2:0]	No	No		No		OUTPUT
sba_tl_h_o.a_opcode[0]	Yes	Yes	*T3,*T12,*T15	Yes	T3,T12,T15	OUTPUT
sba_tl_h_o.a_opcode[1]	No	No		No		OUTPUT
sba_tl_h_o.a_opcode[2]	Yes	Yes	T3,T12,T15	Yes	T1,T2,T3	OUTPUT
sba_tl_h_o.a_valid	Yes	Yes	T3,T12,T15	Yes	T3,T12,T15	OUTPUT
sba_tl_h_i.a_ready	Yes	Yes	T3,T12,T29	Yes	T1,T2,T3	INPUT
sba_tl_h_i.d_error	Yes	Yes	T3,T15,T16	Yes	T3,T29,T15	INPUT
sba_tl_h_i.d_user.data_intg[6:0]	Yes	Yes	T3,T12,T15	Yes	T3,T12,T15	INPUT
sba_tl_h_i.d_user.rsp_intg[6:0]	Yes	Yes	T3,T12,T15	Yes	T3,T12,T15	INPUT
sba_tl_h_i.d_data[31:0]	Yes	Yes	T3,T12,T29	Yes	T3,T12,T15	INPUT
sba_tl_h_i.d_sink	Yes	Yes	T3,T12,T15	Yes	T3,T12,T15	INPUT
sba_tl_h_i.d_source[7:0]	Yes	Yes	T15,T35,T50	Yes	T29,T15,T35	INPUT
sba_tl_h_i.d_size[1:0]	Yes	Yes	T3,T29,T15	Yes	T3,T15,T16	INPUT
sba_tl_h_i.d_param[2:0]	Yes	Yes	T29,T15,T35	Yes	T15,T35,T49	INPUT
sba_tl_h_i.d_opcode[2:0]	Yes	Yes	T3,T12,T15	Yes	T3,T12,T29	INPUT
sba_tl_h_i.d_valid	Yes	Yes	T3,T12,T15	Yes	T3,T12,T15	INPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T2,T29,T36	Yes	T2,T29,T36	INPUT
alert_rx_i[0].ping_n	No	No		No		INPUT
alert_rx_i[0].ping_p	No	No		No		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T2,T29,T36	Yes	T2,T29,T36	OUTPUT
jtag_i.tdi	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
jtag_i.trst_n	Yes	Yes	T3,T16,T17	Yes	T1,T2,T3	INPUT
jtag_i.tms	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
jtag_i.tck	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
jtag_o.tdo_oe	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
jtag_o.tdo	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT

*Tests covering at least one bit in the range

---

Assert Coverage for Module : rv_dm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DebugReqOKnown_A	23743303	23701359	0	0
DmactiveOKnown_A	23743303	23701359	0	0
FpvSecCmRegWeOnehotCheck_A	23743303	90	0	0
FpvSecCmRomTlLcGateFsm_A	23743303	0	0	0
FpvSecCmSbaTlLcGateFsm_A	23743303	0	0	0
JtagRspOTdoKnown_A	9067532	9067171	0	0
JtagRspOTdoOeKnown_A	9067532	9067171	0	0
NdmresetOKnown_A	23743303	23701359	0	0
RvDmLcEnDebugVal_A	23743303	23701359	0	0
TlMemAReadyKnown_A	23743303	23701359	0	0
TlMemDValidKnown_A	23743303	23701359	0	0
TlRegsAReadyKnown_A	23743303	23701359	0	0
TlRegsDValidKnown_A	23743303	23701359	0	0
TlSbaAValidKnown_A	23743303	23701359	0	0
TlSbaDReadyKnown_A	23743303	23701359	0	0
paramCheckNrHarts	158	158	0	0

DebugReqOKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23743303	23701359	0	0
T1	5702	5617	0	0
T2	1003	925	0	0
T3	130801	130062	0	0
T10	8555	8473	0	0
T12	645723	645646	0	0
T15	58538	58472	0	0
T16	147379	146597	0	0
T29	1800	1722	0	0
T34	109150	109144	0	0
T35	96128	96071	0	0

DmactiveOKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23743303	23701359	0	0
T1	5702	5617	0	0
T2	1003	925	0	0
T3	130801	130062	0	0
T10	8555	8473	0	0
T12	645723	645646	0	0
T15	58538	58472	0	0
T16	147379	146597	0	0
T29	1800	1722	0	0
T34	109150	109144	0	0
T35	96128	96071	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23743303	90	0	0
T8	13434	0	0	0
T9	8794	0	0	0
T37	10935	10	0	0
T38	11643	20	0	0
T39	0	20	0	0
T73	0	20	0	0
T74	0	20	0	0
T75	38278	0	0	0
T76	269127	0	0	0
T77	1815	0	0	0
T78	1405	0	0	0
T79	1297	0	0	0
T80	271702	0	0	0

FpvSecCmRomTlLcGateFsm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23743303	0	0	0

FpvSecCmSbaTlLcGateFsm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23743303	0	0	0

JtagRspOTdoKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9067532	9067171	0	0
T1	1351	1351	0	0
T2	107	107	0	0
T3	47513	47504	0	0
T10	1411	1411	0	0
T12	178580	178580	0	0
T15	18173	18173	0	0
T16	153482	153471	0	0
T29	147	147	0	0
T34	172338	172338	0	0
T35	80120	80120	0	0

JtagRspOTdoOeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9067532	9067171	0	0
T1	1351	1351	0	0
T2	107	107	0	0
T3	47513	47504	0	0
T10	1411	1411	0	0
T12	178580	178580	0	0
T15	18173	18173	0	0
T16	153482	153471	0	0
T29	147	147	0	0
T34	172338	172338	0	0
T35	80120	80120	0	0

NdmresetOKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23743303	23701359	0	0
T1	5702	5617	0	0
T2	1003	925	0	0
T3	130801	130062	0	0
T10	8555	8473	0	0
T12	645723	645646	0	0
T15	58538	58472	0	0
T16	147379	146597	0	0
T29	1800	1722	0	0
T34	109150	109144	0	0
T35	96128	96071	0	0

RvDmLcEnDebugVal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23743303	23701359	0	0
T1	5702	5617	0	0
T2	1003	925	0	0
T3	130801	130062	0	0
T10	8555	8473	0	0
T12	645723	645646	0	0
T15	58538	58472	0	0
T16	147379	146597	0	0
T29	1800	1722	0	0
T34	109150	109144	0	0
T35	96128	96071	0	0

TlMemAReadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23743303	23701359	0	0
T1	5702	5617	0	0
T2	1003	925	0	0
T3	130801	130062	0	0
T10	8555	8473	0	0
T12	645723	645646	0	0
T15	58538	58472	0	0
T16	147379	146597	0	0
T29	1800	1722	0	0
T34	109150	109144	0	0
T35	96128	96071	0	0

TlMemDValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23743303	23701359	0	0
T1	5702	5617	0	0
T2	1003	925	0	0
T3	130801	130062	0	0
T10	8555	8473	0	0
T12	645723	645646	0	0
T15	58538	58472	0	0
T16	147379	146597	0	0
T29	1800	1722	0	0
T34	109150	109144	0	0
T35	96128	96071	0	0

TlRegsAReadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23743303	23701359	0	0
T1	5702	5617	0	0
T2	1003	925	0	0
T3	130801	130062	0	0
T10	8555	8473	0	0
T12	645723	645646	0	0
T15	58538	58472	0	0
T16	147379	146597	0	0
T29	1800	1722	0	0
T34	109150	109144	0	0
T35	96128	96071	0	0

TlRegsDValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23743303	23701359	0	0
T1	5702	5617	0	0
T2	1003	925	0	0
T3	130801	130062	0	0
T10	8555	8473	0	0
T12	645723	645646	0	0
T15	58538	58472	0	0
T16	147379	146597	0	0
T29	1800	1722	0	0
T34	109150	109144	0	0
T35	96128	96071	0	0

TlSbaAValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23743303	23701359	0	0
T1	5702	5617	0	0
T2	1003	925	0	0
T3	130801	130062	0	0
T10	8555	8473	0	0
T12	645723	645646	0	0
T15	58538	58472	0	0
T16	147379	146597	0	0
T29	1800	1722	0	0
T34	109150	109144	0	0
T35	96128	96071	0	0

TlSbaDReadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23743303	23701359	0	0
T1	5702	5617	0	0
T2	1003	925	0	0
T3	130801	130062	0	0
T10	8555	8473	0	0
T12	645723	645646	0	0
T15	58538	58472	0	0
T16	147379	146597	0	0
T29	1800	1722	0	0
T34	109150	109144	0	0
T35	96128	96071	0	0

paramCheckNrHarts

Name	Attempts	Real Successes	Failures	Incomplete
Total	158	158	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T29	1	1	0	0
T34	1	1	0	0
T35	1	1	0	0