Unified Coverage Report :: Module :: dmi_jtag

Module : dmi_jtag

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
83.48	94.32	90.57		66.67	82.35

Source File(s) :
/workspace/default/sim-vcs/../src/pulp-platform_riscv-dbg_0.1_0/pulp_riscv_dbg/src/dmi_jtag.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.dap	83.48	94.32	90.57		66.67	82.35

---

Module Instance : tb.dut.dap

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
83.48	94.32	90.57		66.67	82.35

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
86.43	98.36	92.76		72.00	94.02	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
89.59	100.00	79.31	91.55			87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
i_dmi_cdc	88.54	100.00	89.09			98.41	66.67
i_dmi_jtag_tap	94.45	100.00	100.00		73.68	98.57	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : dmi_jtag

	Line No.	Total	Covered	Percent
TOTAL		88	83	94.32
CONT_ASSIGN	64	1	1	100.00
ALWAYS	71	7	7	100.00
ALWAYS	93	3	3	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	132	1	1	100.00
ALWAYS	140	49	44	89.80
CONT_ASSIGN	259	1	1	100.00
ALWAYS	262	12	12	100.00
ALWAYS	286	11	11	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/pulp-platform_riscv-dbg_0.1_0/pulp_riscv_dbg/src/dmi_jtag.sv' or '../src/pulp-platform_riscv-dbg_0.1_0/pulp_riscv_dbg/src/dmi_jtag.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
64	1	1
71	1	1
72	1	1
73	1	1
74	1	1
			MISSING_ELSE
			MISSING_ELSE
87	1	1
88	2	2
			MISSING_ELSE
			MISSING_ELSE
93	1	1
94	1	1
96	1	1
129	1	1
130	1	1
131	1	1
132	1	1
140	1	1
141	1	1
143	1	1
144	1	1
145	1	1
146	1	1
148	1	1
150	1	1
151	1	1
152	1	1
153	1	1
154	1	1
156	1	1
159	1	1
161	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
			MISSING_ELSE
			MISSING_ELSE
173	1	1
174	1	1
175	1	1
			==> MISSING_ELSE
181	1	1
182	1	1
184	1	1
187	0	1
188	0	1
191	1	1
192	1	1
198	1	1
			MISSING_ELSE
203	1	1
205	1	1
206	1	1
			==> MISSING_ELSE
212	1	1
213	1	1
214	0	1
215	1	1
218	1	1
			MISSING_ELSE
			MISSING_ELSE
232	1	1
233	0	1
			MISSING_ELSE
239	1	1
240	1	1
			MISSING_ELSE
243	1	1
244	1	1
			MISSING_ELSE
247	1	1
248	0	1
			MISSING_ELSE
252	1	1
253	1	1
			MISSING_ELSE
259	1	1
262	1	1
263	1	1
264	1	1
266	1	1
267	1	1
268	1	1
269	1	1
271	1	1
272	1	1
			MISSING_ELSE
			MISSING_ELSE
			MISSING_ELSE
277	1	1
278	1	1
279	1	1
			MISSING_ELSE
			MISSING_ELSE
286	1	1
287	1	1
288	1	1
289	1	1
290	1	1
291	1	1
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1

---

Cond Coverage for Module : dmi_jtag

	Total	Covered	Percent
Conditions	53	48	90.57
Logical	53	48	90.57
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (jtag_dmi_clear || (dtmcs_select && update && dtmcs_q.dmihardreset))
             -------1------    ------------------------2-----------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T14,T64
1	0	Covered	T14,T21,T65

 LINE       64
 SUB-EXPRESSION (dtmcs_select && update && dtmcs_q.dmihardreset)
                 ------1-----    ---2--    ----------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T6,T14,T64
1	0	1	Covered	T1,T3,T12
1	1	0	Covered	T1,T3,T12
1	1	1	Covered	T6,T14,T64

 LINE       132
 EXPRESSION ((state_q == Write) ? DTM_WRITE : DTM_READ)
             ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       132
 SUB-EXPRESSION (state_q == Write)
                ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       159
 EXPRESSION (dmi_select && update && (error_q == DMINoError))
             -----1----    ---2--    -----------3-----------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T18,T5,T66
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T3,T12
1	1	1	Covered	T1,T2,T3

 LINE       159
 SUB-EXPRESSION (error_q == DMINoError)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T3,T12
1	Covered	T1,T2,T3

 LINE       163
 EXPRESSION (dtm_op_e'(dmi.op) == DTM_READ)
            ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T12

 LINE       165
 EXPRESSION (dtm_op_e'(dmi.op) == DTM_WRITE)
            ----------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       232
 EXPRESSION (update && (state_q != Idle))
             ---1--    --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       232
 SUB-EXPRESSION (state_q != Idle)
                --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       239
 EXPRESSION (capture && (state_q inside {Read, WaitReadValid}))
             ---1---    -------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T12
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T12

 LINE       243
 EXPRESSION (error_dmi_busy && (error_q == DMINoError))
             -------1------    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T12

 LINE       243
 SUB-EXPRESSION (error_q == DMINoError)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T3,T12
1	Covered	T1,T2,T3

 LINE       247
 EXPRESSION (error_dmi_op_failed && (error_q == DMINoError))
             ---------1---------    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       247
 SUB-EXPRESSION (error_q == DMINoError)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T3,T12
1	Covered	T1,T2,T3

 LINE       252
 EXPRESSION (update && dtmcs_q.dmireset && dtmcs_select)
             ---1--    --------2-------    ------3-----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T12
1	0	1	Covered	T66,T67,T68
1	1	0	Covered	T1,T3,T12
1	1	1	Covered	T1,T3,T12

 LINE       268
 EXPRESSION ((error_q == DMINoError) && ((!error_dmi_busy)))
             -----------1-----------    ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T5,T13,T14
1	0	Covered	T1,T3,T12
1	1	Covered	T1,T2,T3

 LINE       268
 SUB-EXPRESSION (error_q == DMINoError)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       271
 EXPRESSION ((error_q == DMIBusy) || error_dmi_busy)
             ----------1---------    -------2------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Covered	T1,T3,T12
1	0	Covered	T5,T13,T14

 LINE       271
 SUB-EXPRESSION (error_q == DMIBusy)
                ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T13,T14

---

FSM Coverage for Module : dmi_jtag

Summary for FSM :: error_q

	Total	Covered	Percent
States	3	2	66.67	(Not included in score)
Transitions	4	2	50.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
DMIBusy	244	Covered	T1,T3,T12
DMINoError	291	Covered	T1,T2,T3
DMIOPFailed	248	Not Covered

transitions	Line No.	Covered	Tests
DMIBusy->DMINoError	291	Covered	T1,T3,T12
DMINoError->DMIBusy	244	Covered	T1,T3,T12
DMINoError->DMIOPFailed	248	Not Covered
DMIOPFailed->DMINoError	291	Not Covered

Summary for FSM :: state_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	8	6	75.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
Idle	288	Covered	T1,T2,T3
Read	164	Covered	T1,T3,T12
WaitReadValid	175	Covered	T1,T3,T12
WaitWriteValid	206	Covered	T1,T2,T3
Write	166	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
Idle->Read	164	Covered	T1,T3,T12
Idle->Write	166	Covered	T1,T2,T3
Read->Idle	288	Not Covered
Read->WaitReadValid	175	Covered	T1,T3,T12
WaitReadValid->Idle	288	Covered	T1,T3,T12
WaitWriteValid->Idle	288	Covered	T1,T2,T3
Write->Idle	288	Not Covered
Write->WaitWriteValid	206	Covered	T1,T2,T3

---

Branch Coverage for Module : dmi_jtag

	Line No.	Total	Covered	Percent
Branches		51	42	82.35
TERNARY	132	2	2	100.00
IF	72	3	3	100.00
IF	87	3	3	100.00
IF	93	2	2	100.00
IF	150	30	21	70.00
IF	263	9	9	100.00
IF	286	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/pulp-platform_riscv-dbg_0.1_0/pulp_riscv_dbg/src/dmi_jtag.sv' or '../src/pulp-platform_riscv-dbg_0.1_0/pulp_riscv_dbg/src/dmi_jtag.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	132	((state_q == Write)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	72	if (capture)
-2-:	73	if (dtmcs_select)

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	87	if (shift)
-2-:	88	if (dtmcs_select)

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	93	if ((!trst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	150	if (dmi_clear)
-2-:	156	case (state_q)
-3-:	159	if (((dmi_select && update) && (error_q == DMINoError)))
-4-:	163	if ((dtm_op_e'(dmi.op) == DTM_READ))
-5-:	165	if ((dtm_op_e'(dmi.op) == DTM_WRITE))
-6-:	174	if (dmi_req_ready)
-7-:	181	if (dmi_resp_valid)
-8-:	182	case (dmi_resp.resp)
-9-:	205	if (dmi_req_ready)
-10-:	212	if (dmi_resp_valid)
-11-:	213	case (dmi_resp.resp)
-12-:	224	if (dmi_resp_valid)
-13-:	232	if ((update && (state_q != Idle)))
-14-:	239	if ((capture && (state_q inside {Read, WaitReadValid})))
-15-:	243	if ((error_dmi_busy && (error_q == DMINoError)))
-16-:	247	if ((error_dmi_op_failed && (error_q == DMINoError)))
-17-:	252	if (((update && dtmcs_q.dmireset) && dtmcs_select))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	-17-	Status	Tests
1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T14,T21
0	Idle	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T12
0	Idle	1	0	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
0	Idle	1	0	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
0	Idle	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
0	Read	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T12
0	Read	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Not Covered
0	WaitReadValid	-	-	-	-	1	DTM_SUCCESS	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T12
0	WaitReadValid	-	-	-	-	1	DTM_ERR	-	-	-	-	-	-	-	-	-	Not Covered
0	WaitReadValid	-	-	-	-	1	DTM_BUSY	-	-	-	-	-	-	-	-	-	Covered	T5,T13,T14
0	WaitReadValid	-	-	-	-	1	default	-	-	-	-	-	-	-	-	-	Not Covered
0	WaitReadValid	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T12
0	Write	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
0	Write	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Not Covered
0	WaitWriteValid	-	-	-	-	-	-	-	1	DTM_ERR	-	-	-	-	-	-	Not Covered
0	WaitWriteValid	-	-	-	-	-	-	-	1	DTM_BUSY	-	-	-	-	-	-	Covered	T5,T13,T14
0	WaitWriteValid	-	-	-	-	-	-	-	1	default	-	-	-	-	-	-	Covered	T1,T2,T3
0	WaitWriteValid	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
0	default	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Not Covered
0	default	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Not Covered
0	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Not Covered
0	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T1,T2,T3
0	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	Covered	T1,T3,T12
0	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	Covered	T1,T2,T3
0	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T1,T3,T12
0	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T1,T2,T3
0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Not Covered
0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	Covered	T1,T2,T3
0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T3,T12
0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	263	if (dmi_clear)
-2-:	266	if (capture)
-3-:	267	if (dmi_select)
-4-:	268	if (((error_q == DMINoError) && (!error_dmi_busy)))
-5-:	271	if (((error_q == DMIBusy) || error_dmi_busy))
-6-:	277	if (shift)
-7-:	278	if (dmi_select)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests
1	-	-	-	-	-	-	Covered	T1,T2,T3
0	1	1	1	-	-	-	Covered	T1,T2,T3
0	1	1	0	1	-	-	Covered	T1,T2,T3
0	1	1	0	0	-	-	Covered	T1,T2,T3
0	1	0	-	-	-	-	Covered	T1,T2,T3
0	0	-	-	-	-	-	Covered	T1,T2,T3
0	-	-	-	-	1	1	Covered	T1,T2,T3
0	-	-	-	-	1	0	Covered	T1,T2,T3
0	-	-	-	-	0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	286	if ((!trst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3