SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
tl_intg_err_cgs_wrap[rv_dm_mem_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
tl_intg_err_cgs_wrap[rv_dm_regs_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 0 | 14 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 1 | 13 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 1 | 1 | 50.00 | 100 | 0 | 0 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 786078 | 1 | T7 | 8 | T4 | 117 | T9 | 2 | |||
auto[1] | 16458 | 1 | T37 | 15 | T40 | 750 | T62 | 455 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 802311 | 1 | T7 | 8 | T4 | 117 | T9 | 2 | |||
values[1] | 17 | 1 | T37 | 1 | T38 | 2 | T73 | 2 | |||
values[2] | 6 | 1 | T37 | 1 | T74 | 1 | T119 | 2 | |||
values[3] | 119 | 1 | T37 | 7 | T38 | 4 | T39 | 8 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 802299 | 1 | T7 | 8 | T4 | 117 | T9 | 2 | |||
values[1] | 21 | 1 | T37 | 4 | T120 | 2 | T119 | 2 | |||
values[2] | 6 | 1 | T39 | 1 | T121 | 1 | T122 | 2 | |||
values[3] | 112 | 1 | T37 | 7 | T39 | 7 | T73 | 8 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 802186 | 1 | T7 | 8 | T4 | 117 | T9 | 2 | |||
auto[TlIntgErrCmd] | 113 | 1 | T37 | 6 | T38 | 4 | T39 | 7 | |||
auto[TlIntgErrData] | 125 | 1 | T37 | 8 | T38 | 2 | T39 | 11 | |||
auto[TlIntgErrBoth] | 112 | 1 | T37 | 6 | T38 | 4 | T39 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 1 | 1 | 50.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
[auto[1]] | 0 | 0 | - | - | - | - | - | - | |||
auto[0] | 33349 | 0 | T1 | 8 | T31 | 12 | T32 | 12 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 33118 | 1 | T1 | 8 | T31 | 12 | T32 | 12 | |||
values[1] | 24 | 1 | T37 | 3 | T39 | 1 | T74 | 3 | |||
values[2] | 2 | 1 | T123 | 1 | T124 | 1 | - | - | |||
values[3] | 119 | 1 | T37 | 7 | T38 | 5 | T39 | 6 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 33117 | 1 | T1 | 8 | T31 | 12 | T32 | 12 | |||
values[1] | 24 | 1 | T37 | 3 | T39 | 1 | T74 | 2 | |||
values[2] | 6 | 1 | T39 | 1 | T125 | 1 | T120 | 2 | |||
values[3] | 114 | 1 | T37 | 7 | T38 | 4 | T39 | 9 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 32999 | 1 | T1 | 8 | T31 | 12 | T32 | 12 | |||
auto[TlIntgErrCmd] | 118 | 1 | T37 | 8 | T38 | 3 | T39 | 6 | |||
auto[TlIntgErrData] | 119 | 1 | T37 | 4 | T38 | 3 | T39 | 9 | |||
auto[TlIntgErrBoth] | 113 | 1 | T37 | 8 | T38 | 4 | T39 | 5 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |