Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	230738	1		T7	7		T4	81		T8	6
full_word	571798	1		T7	1		T4	36		T9	2

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	802186	1		T7	8		T4	117		T9	2
auto[TlIntgErrCmd]	113	1		T37	6		T38	4		T39	7
auto[TlIntgErrData]	125	1		T37	8		T38	2		T39	11
auto[TlIntgErrBoth]	112	1		T37	6		T38	4		T39	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	472488	1		T4	39		T5	48		T6	9
auto[1]	330048	1		T7	8		T4	78		T9	2

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	188143	1		T4	21		T5	27		T6	4
auto[TlIntgErrNone]	partial	auto[1]	42278	1		T7	7		T4	60		T8	6
auto[TlIntgErrNone]	full_word	auto[0]	284196	1		T4	18		T5	21		T6	5
auto[TlIntgErrNone]	full_word	auto[1]	287569	1		T7	1		T4	18		T9	2
auto[TlIntgErrCmd]	partial	auto[0]	42	1		T37	6		T38	3		T39	2
auto[TlIntgErrCmd]	partial	auto[1]	62	1		T38	1		T39	4		T73	2
auto[TlIntgErrCmd]	full_word	auto[0]	3	1		T39	1		T74	1		T126	1
auto[TlIntgErrCmd]	full_word	auto[1]	6	1		T120	1		T127	1		T126	1
auto[TlIntgErrData]	partial	auto[0]	57	1		T37	6		T38	1		T39	6
auto[TlIntgErrData]	partial	auto[1]	52	1		T37	2		T38	1		T39	3
auto[TlIntgErrData]	full_word	auto[0]	11	1		T39	1		T73	1		T74	1
auto[TlIntgErrData]	full_word	auto[1]	5	1		T39	1		T73	1		T128	2
auto[TlIntgErrBoth]	partial	auto[0]	33	1		T37	2		T38	2		T39	1
auto[TlIntgErrBoth]	partial	auto[1]	71	1		T37	3		T38	2		T39	1
auto[TlIntgErrBoth]	full_word	auto[0]	3	1		T37	1		T125	1		T119	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1		T74	1		T121	1		T129	1