Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	195130	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	570292	1		T7	1		T4	36		T9	2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	470477	1		T4	39		T5	48		T6	9
values[0x0]	145099	1		T7	8		T4	35		T9	1
values[0x1]	149846	1		T4	43		T9	1		T8	4

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	149504	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	615918	1		T7	1		T4	50		T9	2

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2914	1		T6	4		T43	5		T37	44
valid_sources[0x01]	2408	1		T43	3		T37	18		T44	1
valid_sources[0x02]	2982	1		T4	6		T5	1		T18	1
valid_sources[0x03]	2635	1		T4	7		T5	1		T22	9
valid_sources[0x04]	3046	1		T5	3		T18	1		T132	4
valid_sources[0x05]	3574	1		T8	2		T5	2		T22	1
valid_sources[0x06]	4270	1		T5	1		T19	1		T77	6
valid_sources[0x07]	2993	1		T5	1		T6	3		T43	9
valid_sources[0x08]	3592	1		T76	1		T43	9		T40	1
valid_sources[0x09]	2946	1		T21	3		T133	1		T43	5
valid_sources[0x0a]	2957	1		T18	1		T134	1		T43	4
valid_sources[0x0b]	3188	1		T5	1		T61	42		T43	1
valid_sources[0x0c]	2676	1		T4	13		T21	2		T18	1
valid_sources[0x0d]	3715	1		T8	1		T19	3		T43	4
valid_sources[0x0e]	3381	1		T5	1		T43	2		T37	24
valid_sources[0x0f]	2841	1		T4	6		T9	1		T5	1
valid_sources[0x10]	2833	1		T5	3		T43	7		T37	44
valid_sources[0x11]	3235	1		T4	2		T21	20		T76	1
valid_sources[0x12]	3044	1		T5	2		T18	1		T37	20
valid_sources[0x13]	3407	1		T5	1		T18	1		T132	1
valid_sources[0x14]	2882	1		T8	1		T43	3		T37	88
valid_sources[0x15]	2619	1		T5	2		T18	2		T43	5
valid_sources[0x16]	3052	1		T18	1		T43	4		T37	48
valid_sources[0x17]	3052	1		T5	3		T43	3		T37	3
valid_sources[0x18]	2639	1		T7	2		T5	2		T77	1
valid_sources[0x19]	3158	1		T18	1		T37	39		T40	1
valid_sources[0x1a]	2954	1		T4	4		T5	1		T135	1
valid_sources[0x1b]	3261	1		T5	1		T37	22		T40	3
valid_sources[0x1c]	2659	1		T75	1		T43	7		T37	63
valid_sources[0x1d]	3371	1		T5	2		T21	8		T75	1
valid_sources[0x1e]	3112	1		T75	1		T18	2		T43	4
valid_sources[0x1f]	2944	1		T5	2		T6	2		T43	6
valid_sources[0x20]	2762	1		T5	2		T21	2		T75	1
valid_sources[0x21]	2546	1		T4	2		T6	5		T18	1
valid_sources[0x22]	2845	1		T5	1		T21	3		T28	1
valid_sources[0x23]	2791	1		T5	1		T18	1		T132	2
valid_sources[0x24]	2461	1		T77	1		T43	3		T37	19
valid_sources[0x25]	3388	1		T5	1		T77	4		T43	3
valid_sources[0x26]	2769	1		T7	1		T43	6		T37	41
valid_sources[0x27]	2511	1		T5	3		T43	7		T37	12
valid_sources[0x28]	3905	1		T4	4		T18	1		T77	1
valid_sources[0x29]	2442	1		T43	6		T37	49		T40	1
valid_sources[0x2a]	2714	1		T5	3		T43	1		T37	55
valid_sources[0x2b]	2905	1		T17	1		T134	3		T43	2
valid_sources[0x2c]	3069	1		T18	2		T19	1		T77	2
valid_sources[0x2d]	3243	1		T5	1		T17	1		T18	2
valid_sources[0x2e]	2865	1		T5	2		T18	1		T133	1
valid_sources[0x2f]	3397	1		T5	1		T21	3		T134	1
valid_sources[0x30]	2381	1		T5	1		T18	2		T43	1
valid_sources[0x31]	2992	1		T135	1		T43	4		T37	48
valid_sources[0x32]	2759	1		T22	1		T43	1		T37	57
valid_sources[0x33]	2265	1		T4	2		T43	6		T37	48
valid_sources[0x34]	3020	1		T5	1		T43	3		T37	14
valid_sources[0x35]	2880	1		T43	2		T37	69		T40	1
valid_sources[0x36]	3287	1		T5	1		T21	2		T18	1
valid_sources[0x37]	2323	1		T5	1		T13	1		T77	3
valid_sources[0x38]	3035	1		T75	1		T13	1		T43	2
valid_sources[0x39]	2815	1		T5	1		T6	2		T132	2
valid_sources[0x3a]	3403	1		T4	1		T5	4		T13	1
valid_sources[0x3b]	3026	1		T75	2		T18	2		T43	4
valid_sources[0x3c]	2859	1		T4	1		T5	1		T18	4
valid_sources[0x3d]	2871	1		T136	2		T37	41		T44	2
valid_sources[0x3e]	2967	1		T5	1		T18	1		T132	2
valid_sources[0x3f]	2778	1		T18	1		T43	2		T37	24
valid_sources[0x40]	2715	1		T22	2		T75	1		T135	2
valid_sources[0x41]	2711	1		T5	1		T18	1		T43	2
valid_sources[0x42]	2697	1		T132	1		T43	3		T37	44
valid_sources[0x43]	2828	1		T5	3		T22	2		T43	1
valid_sources[0x44]	2540	1		T4	3		T5	2		T77	1
valid_sources[0x45]	2624	1		T43	3		T37	36		T44	3
valid_sources[0x46]	3071	1		T5	1		T13	3		T43	1
valid_sources[0x47]	3121	1		T43	7		T37	64		T40	1
valid_sources[0x48]	3769	1		T9	1		T5	3		T21	4
valid_sources[0x49]	2784	1		T5	1		T135	1		T43	2
valid_sources[0x4a]	2799	1		T5	1		T22	13		T136	1
valid_sources[0x4b]	2534	1		T22	1		T18	4		T133	1
valid_sources[0x4c]	3226	1		T21	4		T28	1		T43	5
valid_sources[0x4d]	2974	1		T5	3		T21	2		T135	2
valid_sources[0x4e]	3288	1		T13	1		T18	2		T135	1
valid_sources[0x4f]	2685	1		T5	2		T13	1		T18	3
valid_sources[0x50]	2363	1		T4	1		T5	1		T22	1
valid_sources[0x51]	2800	1		T43	2		T37	50		T44	3
valid_sources[0x52]	2911	1		T7	1		T43	1		T37	51
valid_sources[0x53]	3838	1		T43	4		T37	58		T40	1
valid_sources[0x54]	2965	1		T18	2		T43	3		T37	35
valid_sources[0x55]	3732	1		T4	1		T5	1		T18	1
valid_sources[0x56]	2798	1		T8	3		T5	3		T18	1
valid_sources[0x57]	3255	1		T8	3		T5	1		T43	4
valid_sources[0x58]	2655	1		T22	3		T18	1		T43	2
valid_sources[0x59]	2798	1		T5	1		T43	1		T37	47
valid_sources[0x5a]	2977	1		T5	1		T43	4		T37	41
valid_sources[0x5b]	3330	1		T134	1		T43	1		T37	56
valid_sources[0x5c]	2709	1		T5	1		T22	10		T13	3
valid_sources[0x5d]	2620	1		T5	1		T21	4		T18	2
valid_sources[0x5e]	3251	1		T43	1		T37	54		T40	1
valid_sources[0x5f]	2852	1		T5	1		T22	1		T136	1
valid_sources[0x60]	3179	1		T21	5		T132	2		T43	7
valid_sources[0x61]	2868	1		T5	1		T43	6		T37	42
valid_sources[0x62]	2643	1		T4	1		T5	1		T43	2
valid_sources[0x63]	3127	1		T18	2		T43	2		T37	23
valid_sources[0x64]	2836	1		T17	1		T135	1		T43	2
valid_sources[0x65]	3424	1		T5	1		T77	3		T132	1
valid_sources[0x66]	3080	1		T21	3		T17	2		T18	1
valid_sources[0x67]	3405	1		T21	5		T43	5		T37	34
valid_sources[0x68]	2729	1		T5	2		T43	3		T37	72
valid_sources[0x69]	3616	1		T5	1		T133	1		T43	3
valid_sources[0x6a]	2993	1		T43	9		T37	64		T40	1
valid_sources[0x6b]	3198	1		T5	1		T18	1		T43	1
valid_sources[0x6c]	4226	1		T5	1		T16	1		T13	3
valid_sources[0x6d]	3447	1		T4	3		T43	4		T37	69
valid_sources[0x6e]	3022	1		T43	2		T37	47		T44	2
valid_sources[0x6f]	2921	1		T5	2		T17	2		T43	4
valid_sources[0x70]	2371	1		T5	1		T21	2		T13	1
valid_sources[0x71]	2974	1		T5	1		T18	1		T132	1
valid_sources[0x72]	2334	1		T5	1		T18	1		T43	4
valid_sources[0x73]	2995	1		T5	1		T43	1		T37	36
valid_sources[0x74]	3191	1		T5	1		T17	1		T75	2
valid_sources[0x75]	3400	1		T43	2		T37	17		T44	4
valid_sources[0x76]	3030	1		T5	1		T43	3		T37	27
valid_sources[0x77]	2592	1		T21	6		T43	2		T37	68
valid_sources[0x78]	2838	1		T5	1		T43	1		T37	19
valid_sources[0x79]	3407	1		T5	1		T43	3		T37	50
valid_sources[0x7a]	2858	1		T137	23		T134	3		T43	9
valid_sources[0x7b]	2647	1		T5	1		T43	4		T37	40
valid_sources[0x7c]	2930	1		T5	1		T135	1		T132	1
valid_sources[0x7d]	3240	1		T135	1		T43	6		T37	47
valid_sources[0x7e]	2881	1		T4	3		T5	1		T18	1
valid_sources[0x7f]	3264	1		T17	3		T135	1		T43	4
valid_sources[0x80]	2546	1		T5	1		T22	1		T132	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

284020

1

T4

18

T5

21

T6

5

values[0x0]

all_enables

biggest_size

143133

1

T7

1

T4

10

T9

1

values[0x1]

all_enables

biggest_size

143139

1

T4

8

T9

1

T8

1

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2160	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	20962	1		T1	2		T31	3		T32	2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	6582	1		T43	2		T37	23		T40	133
values[0x0]	8190	1		T1	3		T31	5		T32	5
values[0x1]	8350	1		T1	5		T31	7		T32	7

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1632	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	21490	1		T1	3		T31	4		T32	3

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	75	1		T40	1		T62	2		T44	1
valid_sources[0x01]	67	1		T40	2		T62	3		T41	1
valid_sources[0x02]	68	1		T138	1		T40	1		T62	2
valid_sources[0x03]	103	1		T139	1		T37	1		T40	2
valid_sources[0x04]	278	1		T140	1		T40	1		T62	2
valid_sources[0x05]	93	1		T50	12		T37	1		T40	3
valid_sources[0x06]	54	1		T141	3		T142	3		T40	1
valid_sources[0x07]	42	1		T49	1		T40	1		T62	2
valid_sources[0x08]	71	1		T143	1		T40	7		T62	3
valid_sources[0x09]	158	1		T40	1		T62	4		T44	1
valid_sources[0x0a]	77	1		T144	2		T40	1		T62	2
valid_sources[0x0b]	117	1		T145	1		T44	1		T41	1
valid_sources[0x0c]	100	1		T146	1		T37	1		T40	2
valid_sources[0x0d]	49	1		T37	2		T62	1		T42	1
valid_sources[0x0e]	94	1		T147	1		T148	2		T40	2
valid_sources[0x0f]	99	1		T149	2		T37	1		T62	4
valid_sources[0x10]	48	1		T139	1		T40	3		T62	1
valid_sources[0x11]	62	1		T149	2		T37	2		T40	1
valid_sources[0x12]	111	1		T49	1		T138	1		T37	2
valid_sources[0x13]	50	1		T62	3		T44	2		T41	3
valid_sources[0x14]	145	1		T40	2		T62	3		T44	1
valid_sources[0x15]	90	1		T40	1		T62	3		T44	1
valid_sources[0x16]	55	1		T37	1		T40	1		T41	2
valid_sources[0x17]	72	1		T146	1		T40	3		T62	1
valid_sources[0x18]	65	1		T48	3		T147	1		T40	2
valid_sources[0x19]	99	1		T150	1		T37	1		T40	1
valid_sources[0x1a]	80	1		T138	1		T151	2		T62	2
valid_sources[0x1b]	187	1		T40	2		T62	1		T44	2
valid_sources[0x1c]	58	1		T152	1		T147	3		T153	2
valid_sources[0x1d]	76	1		T141	1		T37	1		T40	2
valid_sources[0x1e]	66	1		T46	1		T154	1		T146	1
valid_sources[0x1f]	79	1		T40	2		T62	1		T44	1
valid_sources[0x20]	57	1		T40	3		T62	1		T44	5
valid_sources[0x21]	68	1		T48	1		T40	1		T62	1
valid_sources[0x22]	122	1		T153	3		T62	3		T41	1
valid_sources[0x23]	82	1		T49	2		T40	5		T62	1
valid_sources[0x24]	180	1		T62	3		T44	1		T41	4
valid_sources[0x25]	107	1		T155	6		T40	1		T44	3
valid_sources[0x26]	95	1		T31	12		T156	2		T157	1
valid_sources[0x27]	67	1		T40	4		T62	1		T41	1
valid_sources[0x28]	359	1		T40	3		T44	1		T41	2
valid_sources[0x29]	59	1		T40	2		T62	1		T42	2
valid_sources[0x2a]	90	1		T40	2		T62	5		T44	1
valid_sources[0x2b]	74	1		T40	1		T62	2		T41	4
valid_sources[0x2c]	71	1		T158	1		T40	3		T62	3
valid_sources[0x2d]	70	1		T40	4		T62	4		T41	2
valid_sources[0x2e]	91	1		T40	3		T62	4		T44	1
valid_sources[0x2f]	120	1		T40	4		T62	3		T44	1
valid_sources[0x30]	153	1		T43	2		T37	1		T40	6
valid_sources[0x31]	65	1		T62	2		T52	1		T42	1
valid_sources[0x32]	95	1		T159	1		T40	5		T62	4
valid_sources[0x33]	43	1		T40	1		T62	1		T44	3
valid_sources[0x34]	79	1		T142	4		T37	2		T40	4
valid_sources[0x35]	135	1		T40	3		T62	1		T44	2
valid_sources[0x36]	93	1		T48	1		T154	2		T40	1
valid_sources[0x37]	97	1		T40	6		T62	1		T44	1
valid_sources[0x38]	53	1		T141	1		T40	2		T62	2
valid_sources[0x39]	71	1		T152	1		T44	3		T41	3
valid_sources[0x3a]	48	1		T145	4		T144	3		T37	1
valid_sources[0x3b]	151	1		T49	3		T40	1		T44	1
valid_sources[0x3c]	85	1		T62	2		T44	1		T41	1
valid_sources[0x3d]	52	1		T37	1		T40	1		T62	2
valid_sources[0x3e]	89	1		T40	3		T62	2		T44	1
valid_sources[0x3f]	108	1		T156	1		T40	7		T62	1
valid_sources[0x40]	102	1		T142	1		T40	2		T62	2
valid_sources[0x41]	156	1		T145	1		T150	1		T40	2
valid_sources[0x42]	74	1		T160	7		T40	2		T62	2
valid_sources[0x43]	84	1		T40	2		T62	4		T41	2
valid_sources[0x44]	75	1		T161	2		T37	1		T40	1
valid_sources[0x45]	386	1		T46	1		T40	1		T62	4
valid_sources[0x46]	67	1		T62	3		T41	2		T42	2
valid_sources[0x47]	61	1		T40	4		T62	1		T44	2
valid_sources[0x48]	64	1		T143	4		T150	1		T40	1
valid_sources[0x49]	181	1		T139	1		T37	1		T62	1
valid_sources[0x4a]	123	1		T40	5		T62	3		T44	1
valid_sources[0x4b]	100	1		T162	5		T40	4		T62	1
valid_sources[0x4c]	84	1		T40	3		T62	4		T44	2
valid_sources[0x4d]	76	1		T163	1		T146	1		T40	3
valid_sources[0x4e]	61	1		T1	1		T40	4		T62	2
valid_sources[0x4f]	80	1		T47	2		T146	1		T140	4
valid_sources[0x50]	109	1		T157	1		T40	2		T44	1
valid_sources[0x51]	71	1		T150	1		T40	2		T62	3
valid_sources[0x52]	120	1		T40	1		T62	4		T44	3
valid_sources[0x53]	66	1		T40	1		T62	1		T44	1
valid_sources[0x54]	100	1		T150	3		T40	3		T62	2
valid_sources[0x55]	108	1		T141	1		T147	1		T37	2
valid_sources[0x56]	74	1		T40	1		T62	1		T44	2
valid_sources[0x57]	79	1		T163	1		T40	1		T62	4
valid_sources[0x58]	86	1		T162	1		T44	2		T41	2
valid_sources[0x59]	86	1		T40	2		T62	2		T44	2
valid_sources[0x5a]	115	1		T146	1		T40	3		T62	2
valid_sources[0x5b]	68	1		T40	1		T62	2		T41	4
valid_sources[0x5c]	84	1		T145	1		T164	2		T165	9
valid_sources[0x5d]	83	1		T62	2		T44	2		T41	3
valid_sources[0x5e]	62	1		T40	2		T62	1		T44	2
valid_sources[0x5f]	73	1		T159	2		T40	3		T62	2
valid_sources[0x60]	78	1		T37	1		T40	1		T62	1
valid_sources[0x61]	83	1		T37	1		T40	2		T62	2
valid_sources[0x62]	75	1		T40	1		T62	1		T41	5
valid_sources[0x63]	83	1		T32	12		T151	1		T37	1
valid_sources[0x64]	63	1		T48	2		T40	2		T62	1
valid_sources[0x65]	109	1		T48	2		T145	1		T166	10
valid_sources[0x66]	66	1		T146	1		T40	3		T44	3
valid_sources[0x67]	68	1		T46	1		T145	2		T143	2
valid_sources[0x68]	48	1		T40	1		T62	2		T44	2
valid_sources[0x69]	101	1		T40	3		T62	5		T41	2
valid_sources[0x6a]	70	1		T147	4		T40	4		T62	1
valid_sources[0x6b]	113	1		T37	1		T40	1		T41	1
valid_sources[0x6c]	77	1		T167	16		T168	2		T37	1
valid_sources[0x6d]	54	1		T40	4		T44	2		T41	8
valid_sources[0x6e]	202	1		T40	3		T44	2		T41	5
valid_sources[0x6f]	114	1		T40	1		T62	5		T44	1
valid_sources[0x70]	49	1		T40	4		T44	1		T41	6
valid_sources[0x71]	128	1		T46	1		T144	1		T165	6
valid_sources[0x72]	101	1		T45	2		T40	5		T62	2
valid_sources[0x73]	83	1		T44	1		T41	5		T42	1
valid_sources[0x74]	116	1		T33	2		T154	1		T40	1
valid_sources[0x75]	61	1		T40	3		T62	2		T44	1
valid_sources[0x76]	59	1		T62	1		T44	2		T72	4
valid_sources[0x77]	63	1		T40	2		T62	1		T44	1
valid_sources[0x78]	55	1		T151	1		T40	1		T62	3
valid_sources[0x79]	113	1		T37	1		T40	4		T41	1
valid_sources[0x7a]	75	1		T143	1		T40	7		T62	2
valid_sources[0x7b]	118	1		T40	2		T44	1		T41	1
valid_sources[0x7c]	95	1		T154	1		T62	2		T41	1
valid_sources[0x7d]	99	1		T169	1		T154	1		T37	1
valid_sources[0x7e]	89	1		T40	6		T62	2		T44	1
valid_sources[0x7f]	90	1		T40	1		T62	2		T41	1
valid_sources[0x80]	52	1		T145	1		T40	2		T62	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

5601

1

T37

2

T40

133

T62

102

values[0x0]

all_enables

biggest_size

7720

1

T1

1

T31

1

T32

1

values[0x1]

all_enables

biggest_size

7641

1

T1

1

T31

2

T32

1