49a27e136c| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | rv_dm_smoke | 1.580s | 534.560us | 2 | 2 | 100.00 |
| V1 | jtag_dtm_csr_hw_reset | rv_dm_jtag_dtm_csr_hw_reset | 0.880s | 99.942us | 5 | 5 | 100.00 |
| V1 | jtag_dtm_csr_rw | rv_dm_jtag_dtm_csr_rw | 0.830s | 60.803us | 20 | 20 | 100.00 |
| V1 | jtag_dtm_csr_bit_bash | rv_dm_jtag_dtm_csr_bit_bash | 11.160s | 3.355ms | 5 | 5 | 100.00 |
| V1 | jtag_dtm_csr_aliasing | rv_dm_jtag_dtm_csr_aliasing | 1.010s | 132.670us | 5 | 5 | 100.00 |
| V1 | jtag_dmi_csr_hw_reset | rv_dm_jtag_dmi_csr_hw_reset | 5.820s | 1.710ms | 5 | 5 | 100.00 |
| V1 | jtag_dmi_csr_rw | rv_dm_jtag_dmi_csr_rw | 3.620s | 1.680ms | 20 | 20 | 100.00 |
| V1 | jtag_dmi_csr_bit_bash | rv_dm_jtag_dmi_csr_bit_bash | 1.234m | 44.737ms | 5 | 5 | 100.00 |
| V1 | jtag_dmi_csr_aliasing | rv_dm_jtag_dmi_csr_aliasing | 1.123m | 21.698ms | 5 | 5 | 100.00 |
| V1 | jtag_dmi_cmderr_busy | rv_dm_cmderr_busy | 5.630s | 1.575ms | 1 | 2 | 50.00 |
| V1 | jtag_dmi_cmderr_not_supported | rv_dm_cmderr_not_supported | 3.770s | 4.471ms | 2 | 2 | 100.00 |
| V1 | cmderr_exception | rv_dm_cmderr_exception | 1.420s | 712.635us | 2 | 2 | 100.00 |
| V1 | mem_tl_access_resuming | rv_dm_mem_tl_access_resuming | 1.700s | 990.720us | 2 | 2 | 100.00 |
| V1 | mem_tl_access_halted | rv_dm_mem_tl_access_halted | 1.200s | 781.837us | 2 | 2 | 100.00 |
| V1 | cmderr_halt_resume | rv_dm_cmderr_halt_resume | 1.600s | 344.326us | 2 | 2 | 100.00 |
| V1 | dataaddr_rw_access | rv_dm_dataaddr_rw_access | 0.740s | 51.307us | 2 | 2 | 100.00 |
| V1 | halt_resume | rv_dm_halt_resume_whereto | 1.220s | 151.948us | 2 | 2 | 100.00 |
| V1 | progbuf_busy | rv_dm_progbuf_busy | 0.970s | 497.639us | 2 | 2 | 100.00 |
| V1 | abstractcmd_status | abstractcmd_status | 0 | 0 | -- | ||
| V1 | csr_hw_reset | rv_dm_csr_hw_reset | 2.470s | 635.943us | 5 | 5 | 100.00 |
| V1 | csr_rw | rv_dm_csr_rw | 2.450s | 343.280us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | rv_dm_csr_bit_bash | 1.280m | 26.848ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | rv_dm_csr_aliasing | 1.333m | 27.321ms | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | rv_dm_csr_mem_rw_with_rand_reset | 9.050s | 3.380ms | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rv_dm_csr_aliasing | 1.333m | 27.321ms | 5 | 5 | 100.00 |
| rv_dm_csr_rw | 2.450s | 343.280us | 20 | 20 | 100.00 | ||
| V1 | mem_walk | rv_dm_mem_walk | 0.650s | 27.113us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | rv_dm_mem_partial_access | 0.660s | 52.987us | 5 | 5 | 100.00 |
| V1 | TOTAL | 154 | 155 | 99.35 | |||
| V2 | idcode | rv_dm_smoke | 1.580s | 534.560us | 2 | 2 | 100.00 |
| V2 | jtag_dtm_hard_reset | rv_dm_jtag_dtm_hard_reset | 1.400s | 266.452us | 2 | 2 | 100.00 |
| V2 | jtag_dtm_idle_hint | rv_dm_jtag_dtm_idle_hint | 0.770s | 58.427us | 2 | 2 | 100.00 |
| V2 | jtag_dmi_failed_op | jtag_dmi_failed_op | 0 | 0 | -- | ||
| V2 | jtag_dmi_dm_inactive | rv_dm_jtag_dmi_dm_inactive | 0.940s | 159.388us | 2 | 2 | 100.00 |
| V2 | sba | rv_dm_sba_tl_access | 32.520s | 10.975ms | 19 | 20 | 95.00 |
| rv_dm_delayed_resp_sba_tl_access | 27.470s | 8.343ms | 19 | 20 | 95.00 | ||
| V2 | bad_sba | rv_dm_bad_sba_tl_access | 49.380s | 50.000ms | 18 | 20 | 90.00 |
| V2 | sba_autoincrement | rv_dm_autoincr_sba_tl_access | 2.530m | 50.000ms | 7 | 20 | 35.00 |
| V2 | jtag_dmi_debug_disabled | rv_dm_jtag_dmi_debug_disabled | 0.640s | 49.593us | 0 | 2 | 0.00 |
| V2 | sba_debug_disabled | sba_debug_disabled | 0 | 0 | -- | ||
| V2 | ndmreset_req | rv_dm_ndmreset_req | 1.380s | 218.507us | 2 | 2 | 100.00 |
| V2 | hart_unavail | rv_dm_hart_unavail | 0.840s | 164.653us | 5 | 5 | 100.00 |
| V2 | tap_ctrl_transitions | rv_dm_tap_fsm | 3.450s | 3.563ms | 1 | 1 | 100.00 |
| rv_dm_tap_fsm_rand_reset | 35.540s | 10.561ms | 15 | 40 | 37.50 | ||
| V2 | stress_all | rv_dm_stress_all | 14.120s | 4.326ms | 8 | 50 | 16.00 |
| V2 | alert_test | rv_dm_alert_test | 0.740s | 29.702us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | rv_dm_tl_errors | 6.410s | 1.830ms | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | rv_dm_tl_errors | 6.410s | 1.830ms | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | rv_dm_csr_aliasing | 1.333m | 27.321ms | 5 | 5 | 100.00 |
| rv_dm_csr_hw_reset | 2.470s | 635.943us | 5 | 5 | 100.00 | ||
| rv_dm_csr_rw | 2.450s | 343.280us | 20 | 20 | 100.00 | ||
| rv_dm_same_csr_outstanding | 7.800s | 1.280ms | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | rv_dm_csr_aliasing | 1.333m | 27.321ms | 5 | 5 | 100.00 |
| rv_dm_csr_hw_reset | 2.470s | 635.943us | 5 | 5 | 100.00 | ||
| rv_dm_csr_rw | 2.450s | 343.280us | 20 | 20 | 100.00 | ||
| rv_dm_same_csr_outstanding | 7.800s | 1.280ms | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 190 | 276 | 68.84 | |||
| V2S | tl_intg_err | rv_dm_sec_cm | 1.190s | 113.120us | 5 | 5 | 100.00 |
| rv_dm_tl_intg_err | 22.160s | 14.733ms | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | sec_cm_bus_integrity | 0 | 0 | -- | ||
| V2S | sec_cm_lc_hw_debug_en_intersig_mubi | sec_cm_lc_hw_debug_en_intersig_mubi | 0 | 0 | -- | ||
| V2S | sec_cm_dm_en_ctrl_lc_gated | sec_cm_dm_en_ctrl_lc_gated | 0 | 0 | -- | ||
| V2S | sec_cm_sba_tl_lc_gate_fsm_sparse | sec_cm_sba_tl_lc_gate_fsm_sparse | 0 | 0 | -- | ||
| V2S | sec_cm_mem_tl_lc_gate_fsm_sparse | sec_cm_mem_tl_lc_gate_fsm_sparse | 0 | 0 | -- | ||
| V2S | sec_cm_exec_ctrl_mubi | sec_cm_exec_ctrl_mubi | 0 | 0 | -- | ||
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | rv_dm_stress_all_with_rand_reset | 8.200s | 5.871ms | 0 | 50 | 0.00 |
| V3 | TOTAL | 0 | 50 | 0.00 | |||
| Unmapped tests | rv_dm_abstractcmd_status | 0.660s | 24.406us | 0 | 2 | 0.00 | |
| TOTAL | 369 | 508 | 72.64 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| N.A. | 1 | 1 | 0 | 0.00 |
| V1 | 26 | 25 | 24 | 92.31 |
| V2 | 18 | 16 | 9 | 50.00 |
| V2S | 8 | 2 | 2 | 25.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 87.47 | 92.73 | 78.99 | 89.36 | 75.64 | 82.48 | 97.75 | 95.34 |
UVM_ERROR (jtag_dmi_monitor.sv:105) m_jtag_dmi_monitor [m_jtag_dmi_monitor] Non-ok response seen with no previous DMI request. has 64 failures:
Test rv_dm_sba_tl_access has 1 failures.
0.rv_dm_sba_tl_access.26490416395121624357757783838983873213936500493790673020601856257333585488219
Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_sba_tl_access/latest/run.log
UVM_ERROR @ 15784488 ps: (jtag_dmi_monitor.sv:105) uvm_test_top.env.m_jtag_dmi_monitor [uvm_test_top.env.m_jtag_dmi_monitor] Non-ok response seen with no previous DMI request.
UVM_INFO @ 15784488 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_dm_cmderr_busy has 1 failures.
0.rv_dm_cmderr_busy.7282745075378096387465216250119619363277895763040194459063369355310923339405
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_cmderr_busy/latest/run.log
UVM_ERROR @ 55582245 ps: (jtag_dmi_monitor.sv:105) uvm_test_top.env.m_jtag_dmi_monitor [uvm_test_top.env.m_jtag_dmi_monitor] Non-ok response seen with no previous DMI request.
UVM_INFO @ 55582245 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_dm_stress_all has 26 failures.
0.rv_dm_stress_all.2800428850815157357485141906012289222494082371493432029702064582957793745893
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 16494616 ps: (jtag_dmi_monitor.sv:105) uvm_test_top.env.m_jtag_dmi_monitor [uvm_test_top.env.m_jtag_dmi_monitor] Non-ok response seen with no previous DMI request.
UVM_INFO @ 16494616 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rv_dm_stress_all.11104428972921402260027529950144933857288692685169426320717544250613555041678
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 10599484 ps: (jtag_dmi_monitor.sv:105) uvm_test_top.env.m_jtag_dmi_monitor [uvm_test_top.env.m_jtag_dmi_monitor] Non-ok response seen with no previous DMI request.
UVM_INFO @ 10599484 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 24 more failures.
Test rv_dm_stress_all_with_rand_reset has 33 failures.
0.rv_dm_stress_all_with_rand_reset.7840515941671402505235281565632409201243705683032495398889923607913325834968
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 6888576 ps: (jtag_dmi_monitor.sv:105) uvm_test_top.env.m_jtag_dmi_monitor [uvm_test_top.env.m_jtag_dmi_monitor] Non-ok response seen with no previous DMI request.
UVM_INFO @ 6888576 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rv_dm_stress_all_with_rand_reset.56434940591924954012710639324577715180439454750102201775150806332083188959904
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 13509582 ps: (jtag_dmi_monitor.sv:105) uvm_test_top.env.m_jtag_dmi_monitor [uvm_test_top.env.m_jtag_dmi_monitor] Non-ok response seen with no previous DMI request.
UVM_INFO @ 13509582 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 31 more failures.
Test rv_dm_jtag_dmi_debug_disabled has 1 failures.
1.rv_dm_jtag_dmi_debug_disabled.89503121017605060232809973969578876721554521241524827746351040140825078154467
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_jtag_dmi_debug_disabled/latest/run.log
UVM_ERROR @ 49593213 ps: (jtag_dmi_monitor.sv:105) uvm_test_top.env.m_jtag_dmi_monitor [uvm_test_top.env.m_jtag_dmi_monitor] Non-ok response seen with no previous DMI request.
UVM_INFO @ 49593213 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more tests.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 13 failures:
Test rv_dm_autoincr_sba_tl_access has 11 failures.
0.rv_dm_autoincr_sba_tl_access.55023226571362040076975286375057780962632783820418187132358023114799589475948
Line 449, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_autoincr_sba_tl_access/latest/run.log
UVM_FATAL @ 50000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 50000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 50000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.rv_dm_autoincr_sba_tl_access.20903924036041141785570069465545421358028648594760278559524925122438607053292
Line 437, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/2.rv_dm_autoincr_sba_tl_access/latest/run.log
UVM_FATAL @ 50000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 50000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 50000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 9 more failures.
Test rv_dm_bad_sba_tl_access has 1 failures.
8.rv_dm_bad_sba_tl_access.58813397617245220584251195680563960151547194555093957748878598273971417703144
Line 314, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/8.rv_dm_bad_sba_tl_access/latest/run.log
UVM_FATAL @ 50000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 50000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 50000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_dm_tap_fsm_rand_reset has 1 failures.
20.rv_dm_tap_fsm_rand_reset.97658526554856940923246706157939861583483512824327533807652745124078950755464
Line 385, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/20.rv_dm_tap_fsm_rand_reset/latest/run.log
UVM_FATAL @ 50000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 50000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 50000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_smoke_vseq.sv:40) [seq] Check failed cfg.rv_dm_vif.cb.ndmreset_req == data (* [*] vs * [*]) has 10 failures:
0.rv_dm_tap_fsm_rand_reset.40904433714475602932372288011351180452277256597512526467953182467923883799942
Line 357, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_tap_fsm_rand_reset/latest/run.log
UVM_ERROR @ 35697859662 ps: (rv_dm_smoke_vseq.sv:40) [uvm_test_top.env.virtual_sequencer.rv_dm_tap_fsm_vseq.seq] Check failed cfg.rv_dm_vif.cb.ndmreset_req == data (0 [0x0] vs 1 [0x1])
UVM_INFO @ 35697859662 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.rv_dm_tap_fsm_rand_reset.7716901137932924438689814183044082203307011012933546533503180693061704835609
Line 275, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/5.rv_dm_tap_fsm_rand_reset/latest/run.log
UVM_ERROR @ 2496667249 ps: (rv_dm_smoke_vseq.sv:40) [uvm_test_top.env.virtual_sequencer.rv_dm_tap_fsm_vseq.seq] Check failed cfg.rv_dm_vif.cb.ndmreset_req == data (0 [0x0] vs 1 [0x1])
UVM_INFO @ 2496667249 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 8 more failures.
UVM_ERROR (rv_dm_scoreboard.sv:98) [scoreboard] Check failed item.dout & mask == selected_dtm_csr.get_mirrored_value() & mask (* [*] vs * [*]) has 9 failures:
2.rv_dm_stress_all_with_rand_reset.39589822467847993551029073509847787402519699991201274842736168056792908669117
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/2.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 171855459 ps: (rv_dm_scoreboard.sv:98) [uvm_test_top.env.scoreboard] Check failed item.dout & mask == selected_dtm_csr.get_mirrored_value() & mask (17 [0x11] vs 4209 [0x1071])
UVM_INFO @ 171855459 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
6.rv_dm_stress_all_with_rand_reset.26571106405285908247740633740995227536403662338589505062999088155630548523440
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/6.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 22421189 ps: (rv_dm_scoreboard.sv:98) [uvm_test_top.env.scoreboard] Check failed item.dout & mask == selected_dtm_csr.get_mirrored_value() & mask (0 [0x0] vs 4209 [0x1071])
UVM_INFO @ 22421189 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
10.rv_dm_stress_all.73439327260407619826382316361693607284404437365169638218980953560385944223751
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/10.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 8742004 ps: (rv_dm_scoreboard.sv:98) [uvm_test_top.env.scoreboard] Check failed item.dout & mask == selected_dtm_csr.get_mirrored_value() & mask (4294964223 [0xfffff3ff] vs 4209 [0x1071])
UVM_INFO @ 8742004 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
35.rv_dm_stress_all.99378111256108018513447141872453831537102666630899183684833924129667541797758
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/35.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 2057626753 ps: (rv_dm_scoreboard.sv:98) [uvm_test_top.env.scoreboard] Check failed item.dout & mask == selected_dtm_csr.get_mirrored_value() & mask (17 [0x11] vs 4209 [0x1071])
UVM_INFO @ 2057626753 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR (rv_dm_smoke_vseq.sv:32) [seq] Check failed cfg.rv_dm_vif.cb.debug_req == data (* [*] vs * [*]) has 7 failures:
3.rv_dm_tap_fsm_rand_reset.12831235363259227490315019363860576997287018755847825948147047807665445566599
Line 348, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/3.rv_dm_tap_fsm_rand_reset/latest/run.log
UVM_ERROR @ 14037468515 ps: (rv_dm_smoke_vseq.sv:32) [uvm_test_top.env.virtual_sequencer.rv_dm_tap_fsm_vseq.seq] Check failed cfg.rv_dm_vif.cb.debug_req == data (0 [0x0] vs 1 [0x1])
UVM_INFO @ 14037468515 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
11.rv_dm_tap_fsm_rand_reset.34455807138621772528360418982438248497502249802577916793112298273796909050451
Line 288, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/11.rv_dm_tap_fsm_rand_reset/latest/run.log
UVM_ERROR @ 3458906108 ps: (rv_dm_smoke_vseq.sv:32) [uvm_test_top.env.virtual_sequencer.rv_dm_tap_fsm_vseq.seq] Check failed cfg.rv_dm_vif.cb.debug_req == data (0 [0x0] vs 1 [0x1])
UVM_INFO @ 3458906108 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 5 more failures.
UVM_ERROR (csr_utils_pkg.sv:243) [csr_utils] Check failed status == UVM_IS_OK (* [*] vs * [*]) trying to write csr jtag_dmi_ral.dmcontrol has 6 failures:
9.rv_dm_stress_all.37643743749965432186304461007085876650474931140238355136232850902212373128006
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/9.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 5881091 ps: (csr_utils_pkg.sv:243) [csr_utils] Check failed status == UVM_IS_OK (1 [0x1] vs 0 [0x0]) trying to write csr jtag_dmi_ral.dmcontrol
UVM_INFO @ 5881091 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
22.rv_dm_stress_all.28029736326542341643231443286723958290503033098705453057695601630787953300961
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/22.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 9000936 ps: (csr_utils_pkg.sv:243) [csr_utils] Check failed status == UVM_IS_OK (1 [0x1] vs 0 [0x0]) trying to write csr jtag_dmi_ral.dmcontrol
UVM_INFO @ 9000936 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
29.rv_dm_stress_all_with_rand_reset.3796979584344203260530080387883366267621874328302698518181938947017953497093
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/29.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 5932612 ps: (csr_utils_pkg.sv:243) [csr_utils] Check failed status == UVM_IS_OK (1 [0x1] vs 0 [0x0]) trying to write csr jtag_dmi_ral.dmcontrol
UVM_INFO @ 5932612 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
31.rv_dm_stress_all_with_rand_reset.103833360424055587933985164642374967245887388919906016367488924525338773092810
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/31.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 20666321 ps: (csr_utils_pkg.sv:243) [csr_utils] Check failed status == UVM_IS_OK (1 [0x1] vs 0 [0x0]) trying to write csr jtag_dmi_ral.dmcontrol
UVM_INFO @ 20666321 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_FATAL (csr_utils_pkg.sv:374) [csr_utils::csr_rd] Timeout waiting to csr_rd jtag_dtm_ral.idcode (addr=*) has 4 failures:
10.rv_dm_tap_fsm_rand_reset.107081026585353602531904843326696865175466800931283696233435483754260855966684
Line 272, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/10.rv_dm_tap_fsm_rand_reset/latest/run.log
UVM_FATAL @ 3870094855 ps: (csr_utils_pkg.sv:374) [csr_utils::csr_rd] Timeout waiting to csr_rd jtag_dtm_ral.idcode (addr=0x1)
UVM_INFO @ 3870094855 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
37.rv_dm_tap_fsm_rand_reset.55824436226940505308964210072504045394651395515093999474255609791639096020872
Line 311, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/37.rv_dm_tap_fsm_rand_reset/latest/run.log
UVM_FATAL @ 6064789539 ps: (csr_utils_pkg.sv:374) [csr_utils::csr_rd] Timeout waiting to csr_rd jtag_dtm_ral.idcode (addr=0x1)
UVM_INFO @ 6064789539 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_ERROR (rv_dm_jtag_dmi_debug_disabled_vseq.sv:25) [rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (* [*] vs * [*]) has 3 failures:
Test rv_dm_jtag_dmi_debug_disabled has 1 failures.
0.rv_dm_jtag_dmi_debug_disabled.6182113843674059305528607272461776331637842605449861844037780756826183955840
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_jtag_dmi_debug_disabled/latest/run.log
UVM_ERROR @ 14789626 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:25) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (0 [0x0] vs 2066503749 [0x7b2c5845])
UVM_INFO @ 14789626 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_dm_stress_all has 2 failures.
4.rv_dm_stress_all.52148517094699202896177465887962514606477661743827210371055060491956116147235
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/4.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 1570242783 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:25) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (0 [0x0] vs 1765627513 [0x693d5679])
UVM_INFO @ 1570242783 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
32.rv_dm_stress_all.70374806894430159033781919416436878534374803613435948510865268336082361213765
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/32.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 2163167938 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:25) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (0 [0x0] vs 3747004550 [0xdf56c086])
UVM_INFO @ 2163167938 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_scoreboard.sv:361) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: rv_dm_mem_reg_block.dataaddr_* has 3 failures:
11.rv_dm_stress_all_with_rand_reset.106459149425773182649777454941365713548674013217262713703283705410792353296712
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/11.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 205827987 ps: (rv_dm_scoreboard.sv:361) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1484011778 [0x58743902] vs 1477720322 [0x58143902]) reg name: rv_dm_mem_reg_block.dataaddr_0
UVM_INFO @ 205827987 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
18.rv_dm_stress_all_with_rand_reset.112143948999279892860521150264887801389379717338990364206875171997851312499621
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/18.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 306890005 ps: (rv_dm_scoreboard.sv:361) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2450588752 [0x92110450] vs 2467412099 [0x9311b883]) reg name: rv_dm_mem_reg_block.dataaddr_1
UVM_INFO @ 306890005 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR (jtag_dmi_monitor.sv:48) m_jtag_dmi_monitor [m_jtag_dmi_monitor] Bad packet: item: (jtag_item@5095) { ir_len: * dr_len: * ir: * dr: 'hxxxxxxxxxxxxxxxx dout: 'hxxxxxxxxxxxxxxxx bus_op: BusOpWrite skip_reselected_ir: * ir_pause_count: * dr_pause_count: * } has 3 failures:
Test rv_dm_delayed_resp_sba_tl_access has 1 failures.
12.rv_dm_delayed_resp_sba_tl_access.19358259474275897319002171712840189984214233966102184850504043830003074432664
Line 258, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/12.rv_dm_delayed_resp_sba_tl_access/latest/run.log
UVM_ERROR @ 1079256 ps: (jtag_dmi_monitor.sv:48) uvm_test_top.env.m_jtag_dmi_monitor [uvm_test_top.env.m_jtag_dmi_monitor] Bad packet: item: (jtag_item@5095) { ir_len: 'h0 dr_len: 'h0 ir: 'h0 dr: 'hxxxxxxxxxxxxxxxx dout: 'hxxxxxxxxxxxxxxxx bus_op: BusOpWrite skip_reselected_ir: 'h0 ir_pause_count: 'h0 dr_pause_count: 'h0 }
. ir_len & dr_len are both zero, or non-zero.
UVM_INFO @ 1079256 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_dm_stress_all has 2 failures.
13.rv_dm_stress_all.80957180252879758106540882329873722954133940649867024757831638047088369571877
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/13.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 2730473 ps: (jtag_dmi_monitor.sv:48) uvm_test_top.env.m_jtag_dmi_monitor [uvm_test_top.env.m_jtag_dmi_monitor] Bad packet: item: (jtag_item@5095) { ir_len: 'h0 dr_len: 'h0 ir: 'h0 dr: 'hxxxxxxxxxxxxxxxx dout: 'hxxxxxxxxxxxxxxxx bus_op: BusOpWrite skip_reselected_ir: 'h0 ir_pause_count: 'h0 dr_pause_count: 'h0 }
. ir_len & dr_len are both zero, or non-zero.
UVM_INFO @ 2730473 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
49.rv_dm_stress_all.103852370049094857244947472694412035283114943903271287281464787677171642764817
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/49.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 785528 ps: (jtag_dmi_monitor.sv:48) uvm_test_top.env.m_jtag_dmi_monitor [uvm_test_top.env.m_jtag_dmi_monitor] Bad packet: item: (jtag_item@5095) { ir_len: 'h0 dr_len: 'h0 ir: 'h0 dr: 'hxxxxxxxxxxxxxxxx dout: 'hxxxxxxxxxxxxxxxx bus_op: BusOpWrite skip_reselected_ir: 'h0 ir_pause_count: 'h0 dr_pause_count: 'h0 }
. ir_len & dr_len are both zero, or non-zero.
UVM_INFO @ 785528 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed Error-[NOA] Null object access has 2 failures:
0.rv_dm_abstractcmd_status.9722594847326752290911589096950894405942946696971898778014561896799228633583
Line 252, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_abstractcmd_status/latest/run.log
Error-[NOA] Null object access
../src/lowrisc_dv_dv_base_reg_0/dv_base_reg_pkg.sv, 73
The object at dereference depth 0 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
1.rv_dm_abstractcmd_status.94649865068201514289473176435656532096165606892801345545761152119864368573243
Line 252, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_abstractcmd_status/latest/run.log
Error-[NOA] Null object access
../src/lowrisc_dv_dv_base_reg_0/dv_base_reg_pkg.sv, 73
The object at dereference depth 0 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
UVM_ERROR (rv_dm_smoke_vseq.sv:59) [seq] Check failed cfg.rv_dm_vif.cb.dmactive == data (* [*] vs * [*]) has 2 failures:
8.rv_dm_tap_fsm_rand_reset.22377326675061053486564533454779819269431634457391526146159324212339741031266
Line 297, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/8.rv_dm_tap_fsm_rand_reset/latest/run.log
UVM_ERROR @ 3622695863 ps: (rv_dm_smoke_vseq.sv:59) [uvm_test_top.env.virtual_sequencer.rv_dm_tap_fsm_vseq.seq] Check failed cfg.rv_dm_vif.cb.dmactive == data (0 [0x0] vs 1 [0x1])
UVM_INFO @ 3622695863 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
17.rv_dm_tap_fsm_rand_reset.100303564100766452599051896854245188132393609594117296826289401161554721038998
Line 375, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/17.rv_dm_tap_fsm_rand_reset/latest/run.log
UVM_ERROR @ 9845337965 ps: (rv_dm_smoke_vseq.sv:59) [uvm_test_top.env.virtual_sequencer.rv_dm_tap_fsm_vseq.seq] Check failed cfg.rv_dm_vif.cb.dmactive == data (0 [0x0] vs 1 [0x1])
UVM_INFO @ 9845337965 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_base_vseq.sv:167) [rv_dm_cmderr_not_supported_vseq] Check failed cmderr == get_field_val(jtag_dmi_ral.abstractcs.cmderr,rdata) (* [*] vs * [*]) has 2 failures:
11.rv_dm_stress_all.98302237177667560021423536244674438654628149699535329839679043820602174534211
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/11.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 373729632 ps: (rv_dm_base_vseq.sv:167) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_not_supported_vseq] Check failed cmderr == get_field_val(jtag_dmi_ral.abstractcs.cmderr,rdata) (2 [0x2] vs 0 [0x0])
UVM_INFO @ 373729632 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
21.rv_dm_stress_all.27478656292413637115914013078858101588022863113982393006226581127265056609373
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/21.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 1526710164 ps: (rv_dm_base_vseq.sv:167) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_not_supported_vseq] Check failed cmderr == get_field_val(jtag_dmi_ral.abstractcs.cmderr,rdata) (2 [0x2] vs 1 [0x1])
UVM_INFO @ 1526710164 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:216) [csr_utils::csr_wr] Timeout waiting to csr_wr rv_dm_mem_reg_block.halted (addr=*) has 2 failures:
23.rv_dm_stress_all.33698057523126770842591251924274530501242914360715757548750217552041738166506
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/23.rv_dm_stress_all/latest/run.log
UVM_FATAL @ 2450474921 ps: (csr_utils_pkg.sv:216) [csr_utils::csr_wr] Timeout waiting to csr_wr rv_dm_mem_reg_block.halted (addr=0x47ccf100)
UVM_INFO @ 2450474921 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
24.rv_dm_stress_all.21349245419912758204518839876385086485563954843982569509657147167664914200839
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/24.rv_dm_stress_all/latest/run.log
UVM_FATAL @ 2723770296 ps: (csr_utils_pkg.sv:216) [csr_utils::csr_wr] Timeout waiting to csr_wr rv_dm_mem_reg_block.halted (addr=0xe489c100)
UVM_INFO @ 2723770296 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (jtag_rv_debugger.sv:1108) [debugger] Check failed is_busy == * (* [*] vs * [*]) has 1 failures:
1.rv_dm_autoincr_sba_tl_access.53275367209803988714457907712375055021157432155687041411578385743325167788578
Line 281, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_autoincr_sba_tl_access/latest/run.log
UVM_ERROR @ 472403853 ps: (jtag_rv_debugger.sv:1108) [debugger] Check failed is_busy == 0 (1 [0x1] vs 0 [0x0])
UVM_INFO @ 472403853 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_halt_resume_whereto_vseq.sv:27) [rv_dm_halt_resume_whereto_vseq] Check failed * == get_field_val(jtag_dmi_ral.abstractcs.busy,rdata) (* [*] vs * [*]) has 1 failures:
14.rv_dm_stress_all.90076958709177734100830736645347030266692619171969938861254874235825321061806
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/14.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 49815633 ps: (rv_dm_halt_resume_whereto_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.rv_dm_halt_resume_whereto_vseq] Check failed 1 == get_field_val(jtag_dmi_ral.abstractcs.busy,rdata) (1 [0x1] vs 0 [0x0])
UVM_INFO @ 49815633 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_mem_tl_access_resuming_vseq.sv:42) [rv_dm_mem_tl_access_resuming_vseq] Check failed * == get_field_val(jtag_dmi_ral.dmstatus.anyrunning, rdata) (* [*] vs * [*]) has 1 failures:
14.rv_dm_stress_all_with_rand_reset.47309315077493439713314004501727476534465334338370133178553067747800700150743
Line 255, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/14.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 34037789 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:42) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed 1 == get_field_val(jtag_dmi_ral.dmstatus.anyrunning, rdata) (1 [0x1] vs 0 [0x0])
UVM_INFO @ 34037789 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_base_vseq.sv:167) [rv_dm_cmderr_busy_vseq] Check failed cmderr == get_field_val(jtag_dmi_ral.abstractcs.cmderr,rdata) (* [*] vs * [*]) has 1 failures:
22.rv_dm_stress_all_with_rand_reset.25728923703537132655764476584072698447254535781715501248460020487887614139584
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/22.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 149737841 ps: (rv_dm_base_vseq.sv:167) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_busy_vseq] Check failed cmderr == get_field_val(jtag_dmi_ral.abstractcs.cmderr,rdata) (1 [0x1] vs 3 [0x3])
UVM_INFO @ 149737841 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_hart_unavail_vseq.sv:24) [rv_dm_hart_unavail_vseq] Check failed cfg.rv_dm_vif.unavailable == get_field_val(jtag_dmi_ral.dmstatus.anyunavail, data) (* [*] vs * [*]) has 1 failures:
26.rv_dm_stress_all_with_rand_reset.34250866707541293801564310428767157317647475454245990530518804776722071382418
Line 255, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/26.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 117612171 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed cfg.rv_dm_vif.unavailable == get_field_val(jtag_dmi_ral.dmstatus.anyunavail, data) (1 [0x1] vs 0 [0x0])
UVM_INFO @ 117612171 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_halt_resume_whereto_vseq.sv:33) [rv_dm_halt_resume_whereto_vseq] Check failed * == get_field_val(jtag_dmi_ral.abstractcs.busy,rdata) (* [*] vs * [*]) has 1 failures:
27.rv_dm_stress_all_with_rand_reset.42766943233893266594888517376594819815092366507233898463618228379685101386678
Line 255, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/27.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 24125429 ps: (rv_dm_halt_resume_whereto_vseq.sv:33) [uvm_test_top.env.virtual_sequencer.rv_dm_halt_resume_whereto_vseq] Check failed 1 == get_field_val(jtag_dmi_ral.abstractcs.busy,rdata) (1 [0x1] vs 0 [0x0])
UVM_INFO @ 24125429 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'rv_dm_tap_fsm_vseq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 1 failures:
35.rv_dm_tap_fsm_rand_reset.27763945050080110173258054333765205148860008526767702994720395788308214427821
Line 277, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/35.rv_dm_tap_fsm_rand_reset/latest/run.log
UVM_ERROR @ 13136143721 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_jtag_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_jtag_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.rv_dm_tap_fsm_vseq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
UVM_INFO @ 13136143721 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:774) [rv_dm_common_vseq] Check failed (!has_outstanding_access()) Waited too long to issue a reset with no outstanding accesses. has 1 failures:
35.rv_dm_stress_all_with_rand_reset.38855660845542932967743751160898691168420815902117303304657440307367211702502
Line 254, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/35.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1229091965 ps: (cip_base_vseq.sv:774) [uvm_test_top.env.virtual_sequencer.rv_dm_common_vseq] Check failed (!has_outstanding_access()) Waited too long to issue a reset with no outstanding accesses.
UVM_INFO @ 1229091965 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_ndmreset_req_vseq.sv:54) [rv_dm_ndmreset_req_vseq] Check failed rdata == * (* [*] vs * [*]) has 1 failures:
46.rv_dm_stress_all.63607892985091449979929568327014991653907719665363512345076226442649377439379
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/46.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 3230065025 ps: (rv_dm_ndmreset_req_vseq.sv:54) [uvm_test_top.env.virtual_sequencer.rv_dm_ndmreset_req_vseq] Check failed rdata == 'h58710590 (0 [0x0] vs 1483802000 [0x58710590])
UVM_INFO @ 3230065025 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---