e0c4026501| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | rv_dm_smoke | 1.190s | 192.067us | 2 | 2 | 100.00 |
| V1 | jtag_dtm_csr_hw_reset | rv_dm_jtag_dtm_csr_hw_reset | 0.870s | 95.940us | 5 | 5 | 100.00 |
| V1 | jtag_dtm_csr_rw | rv_dm_jtag_dtm_csr_rw | 0.880s | 94.162us | 20 | 20 | 100.00 |
| V1 | jtag_dtm_csr_bit_bash | rv_dm_jtag_dtm_csr_bit_bash | 9.100s | 4.353ms | 5 | 5 | 100.00 |
| V1 | jtag_dtm_csr_aliasing | rv_dm_jtag_dtm_csr_aliasing | 0.970s | 128.714us | 5 | 5 | 100.00 |
| V1 | jtag_dmi_csr_hw_reset | rv_dm_jtag_dmi_csr_hw_reset | 2.900s | 1.226ms | 5 | 5 | 100.00 |
| V1 | jtag_dmi_csr_rw | rv_dm_jtag_dmi_csr_rw | 3.190s | 869.921us | 19 | 20 | 95.00 |
| V1 | jtag_dmi_csr_bit_bash | rv_dm_jtag_dmi_csr_bit_bash | 1.409m | 50.000ms | 4 | 5 | 80.00 |
| V1 | jtag_dmi_csr_aliasing | rv_dm_jtag_dmi_csr_aliasing | 29.950s | 9.273ms | 5 | 5 | 100.00 |
| V1 | jtag_dmi_cmderr_busy | rv_dm_cmderr_busy | 2.920s | 616.121us | 1 | 2 | 50.00 |
| V1 | jtag_dmi_cmderr_not_supported | rv_dm_cmderr_not_supported | 4.290s | 1.274ms | 2 | 2 | 100.00 |
| V1 | cmderr_exception | rv_dm_cmderr_exception | 1.770s | 546.903us | 2 | 2 | 100.00 |
| V1 | mem_tl_access_resuming | rv_dm_mem_tl_access_resuming | 0.700s | 120.160us | 2 | 2 | 100.00 |
| V1 | mem_tl_access_halted | rv_dm_mem_tl_access_halted | 0.820s | 62.560us | 2 | 2 | 100.00 |
| V1 | cmderr_halt_resume | rv_dm_cmderr_halt_resume | 1.060s | 130.924us | 2 | 2 | 100.00 |
| V1 | dataaddr_rw_access | rv_dm_dataaddr_rw_access | 0.820s | 85.438us | 2 | 2 | 100.00 |
| V1 | halt_resume | rv_dm_halt_resume_whereto | 1.170s | 128.451us | 2 | 2 | 100.00 |
| V1 | progbuf_busy | rv_dm_progbuf_busy | 1.040s | 90.492us | 2 | 2 | 100.00 |
| V1 | abstractcmd_status | abstractcmd_status | 0 | 0 | -- | ||
| V1 | progbuf_read_write_execute | progbuf_read_write_execute | 0 | 0 | -- | ||
| V1 | progbuf_exception | progbuf_exception | 0 | 0 | -- | ||
| V1 | rom_read_access | rom_read_access | 0 | 0 | -- | ||
| V1 | csr_hw_reset | rv_dm_csr_hw_reset | 2.550s | 2.062ms | 5 | 5 | 100.00 |
| V1 | csr_rw | rv_dm_csr_rw | 2.440s | 241.753us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | rv_dm_csr_bit_bash | 1.166m | 19.385ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | rv_dm_csr_aliasing | 1.232m | 7.248ms | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | rv_dm_csr_mem_rw_with_rand_reset | 10.370s | 4.276ms | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rv_dm_csr_aliasing | 1.232m | 7.248ms | 5 | 5 | 100.00 |
| rv_dm_csr_rw | 2.440s | 241.753us | 20 | 20 | 100.00 | ||
| V1 | mem_walk | rv_dm_mem_walk | 0.670s | 27.295us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | rv_dm_mem_partial_access | 0.680s | 19.333us | 5 | 5 | 100.00 |
| V1 | TOTAL | 152 | 155 | 98.06 | |||
| V2 | idcode | rv_dm_smoke | 1.190s | 192.067us | 2 | 2 | 100.00 |
| V2 | jtag_dtm_hard_reset | rv_dm_jtag_dtm_hard_reset | 3.540s | 950.941us | 2 | 2 | 100.00 |
| V2 | jtag_dtm_idle_hint | rv_dm_jtag_dtm_idle_hint | 0.710s | 61.235us | 2 | 2 | 100.00 |
| V2 | jtag_dmi_failed_op | jtag_dmi_failed_op | 0 | 0 | -- | ||
| V2 | jtag_dmi_dm_inactive | rv_dm_jtag_dmi_dm_inactive | 0.910s | 79.488us | 2 | 2 | 100.00 |
| V2 | sba | rv_dm_sba_tl_access | 58.920s | 17.560ms | 19 | 20 | 95.00 |
| rv_dm_delayed_resp_sba_tl_access | 27.480s | 7.811ms | 20 | 20 | 100.00 | ||
| V2 | bad_sba | rv_dm_bad_sba_tl_access | 1.055m | 50.000ms | 18 | 20 | 90.00 |
| V2 | sba_autoincrement | rv_dm_autoincr_sba_tl_access | 3.004m | 50.000ms | 9 | 20 | 45.00 |
| V2 | jtag_dmi_debug_disabled | rv_dm_jtag_dmi_debug_disabled | 0.970s | 222.374us | 1 | 2 | 50.00 |
| V2 | sba_debug_disabled | sba_debug_disabled | 0 | 0 | -- | ||
| V2 | ndmreset_req | rv_dm_ndmreset_req | 1.650s | 613.362us | 2 | 2 | 100.00 |
| V2 | hart_unavail | rv_dm_hart_unavail | 0.800s | 89.626us | 4 | 5 | 80.00 |
| V2 | tap_ctrl_transitions | rv_dm_tap_fsm | 3.380s | 2.465ms | 1 | 1 | 100.00 |
| rv_dm_tap_fsm_rand_reset | 32.620s | 9.317ms | 10 | 40 | 25.00 | ||
| V2 | stress_all | rv_dm_stress_all | 10.860s | 3.474ms | 5 | 50 | 10.00 |
| V2 | alert_test | rv_dm_alert_test | 0.780s | 17.129us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | rv_dm_tl_errors | 5.360s | 96.776us | 19 | 20 | 95.00 |
| V2 | tl_d_illegal_access | rv_dm_tl_errors | 5.360s | 96.776us | 19 | 20 | 95.00 |
| V2 | tl_d_outstanding_access | rv_dm_csr_aliasing | 1.232m | 7.248ms | 5 | 5 | 100.00 |
| rv_dm_csr_hw_reset | 2.550s | 2.062ms | 5 | 5 | 100.00 | ||
| rv_dm_csr_rw | 2.440s | 241.753us | 20 | 20 | 100.00 | ||
| rv_dm_same_csr_outstanding | 7.860s | 1.835ms | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | rv_dm_csr_aliasing | 1.232m | 7.248ms | 5 | 5 | 100.00 |
| rv_dm_csr_hw_reset | 2.550s | 2.062ms | 5 | 5 | 100.00 | ||
| rv_dm_csr_rw | 2.440s | 241.753us | 20 | 20 | 100.00 | ||
| rv_dm_same_csr_outstanding | 7.860s | 1.835ms | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 184 | 276 | 66.67 | |||
| V2S | tl_intg_err | rv_dm_sec_cm | 1.320s | 341.135us | 5 | 5 | 100.00 |
| rv_dm_tl_intg_err | 19.920s | 1.103ms | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | sec_cm_bus_integrity | 0 | 0 | -- | ||
| V2S | sec_cm_lc_hw_debug_en_intersig_mubi | sec_cm_lc_hw_debug_en_intersig_mubi | 0 | 0 | -- | ||
| V2S | sec_cm_dm_en_ctrl_lc_gated | sec_cm_dm_en_ctrl_lc_gated | 0 | 0 | -- | ||
| V2S | sec_cm_sba_tl_lc_gate_fsm_sparse | sec_cm_sba_tl_lc_gate_fsm_sparse | 0 | 0 | -- | ||
| V2S | sec_cm_mem_tl_lc_gate_fsm_sparse | sec_cm_mem_tl_lc_gate_fsm_sparse | 0 | 0 | -- | ||
| V2S | sec_cm_exec_ctrl_mubi | sec_cm_exec_ctrl_mubi | 0 | 0 | -- | ||
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | rv_dm_stress_all_with_rand_reset | 53.020s | 52.587ms | 0 | 50 | 0.00 |
| V3 | TOTAL | 0 | 50 | 0.00 | |||
| Unmapped tests | rv_dm_abstractcmd_status | 0.760s | 7.312us | 0 | 2 | 0.00 | |
| rv_dm_rom_read_access | 0.790s | 19.667us | 2 | 2 | 100.00 | ||
| TOTAL | 363 | 510 | 71.18 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| N.A. | 2 | 2 | 1 | 50.00 |
| V1 | 29 | 25 | 22 | 75.86 |
| V2 | 18 | 16 | 8 | 44.44 |
| V2S | 8 | 2 | 2 | 25.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 87.77 | 92.87 | 79.06 | 89.36 | 76.92 | 83.07 | 97.75 | 95.34 |
UVM_ERROR (jtag_dmi_monitor.sv:105) m_jtag_dmi_monitor [m_jtag_dmi_monitor] Non-ok response seen with no previous DMI request. has 61 failures:
Test rv_dm_cmderr_busy has 1 failures.
0.rv_dm_cmderr_busy.86673332733541473465752336908260704347770374325108821359561459569596539515969
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_cmderr_busy/latest/run.log
UVM_ERROR @ 297591458 ps: (jtag_dmi_monitor.sv:105) uvm_test_top.env.m_jtag_dmi_monitor [uvm_test_top.env.m_jtag_dmi_monitor] Non-ok response seen with no previous DMI request.
UVM_INFO @ 297591458 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_dm_stress_all has 28 failures.
0.rv_dm_stress_all.103647924339566253041429260979163642421050589138420272031679495396414453658164
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 429005550 ps: (jtag_dmi_monitor.sv:105) uvm_test_top.env.m_jtag_dmi_monitor [uvm_test_top.env.m_jtag_dmi_monitor] Non-ok response seen with no previous DMI request.
UVM_INFO @ 429005550 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rv_dm_stress_all.97736653759439449908076266073120505854244801302575630149548595379855507804345
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 16518090 ps: (jtag_dmi_monitor.sv:105) uvm_test_top.env.m_jtag_dmi_monitor [uvm_test_top.env.m_jtag_dmi_monitor] Non-ok response seen with no previous DMI request.
UVM_INFO @ 16518090 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 26 more failures.
Test rv_dm_stress_all_with_rand_reset has 29 failures.
0.rv_dm_stress_all_with_rand_reset.14057919869508449733478343794151153490996279876945845295664537467323393614222
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 17940079 ps: (jtag_dmi_monitor.sv:105) uvm_test_top.env.m_jtag_dmi_monitor [uvm_test_top.env.m_jtag_dmi_monitor] Non-ok response seen with no previous DMI request.
UVM_INFO @ 17940079 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.rv_dm_stress_all_with_rand_reset.109997006548171914748277724374654138877997936726347338087690136423726405022727
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/2.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 24100272 ps: (jtag_dmi_monitor.sv:105) uvm_test_top.env.m_jtag_dmi_monitor [uvm_test_top.env.m_jtag_dmi_monitor] Non-ok response seen with no previous DMI request.
UVM_INFO @ 24100272 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 27 more failures.
Test rv_dm_jtag_dmi_debug_disabled has 1 failures.
1.rv_dm_jtag_dmi_debug_disabled.45364057841807797447913732879783380225470992619741651837117549341236462687535
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_jtag_dmi_debug_disabled/latest/run.log
UVM_ERROR @ 11456892 ps: (jtag_dmi_monitor.sv:105) uvm_test_top.env.m_jtag_dmi_monitor [uvm_test_top.env.m_jtag_dmi_monitor] Non-ok response seen with no previous DMI request.
UVM_INFO @ 11456892 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_dm_autoincr_sba_tl_access has 1 failures.
8.rv_dm_autoincr_sba_tl_access.28825662748738898695044413222725767458043934737899205491833419822379467211538
Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/8.rv_dm_autoincr_sba_tl_access/latest/run.log
UVM_ERROR @ 13188192 ps: (jtag_dmi_monitor.sv:105) uvm_test_top.env.m_jtag_dmi_monitor [uvm_test_top.env.m_jtag_dmi_monitor] Non-ok response seen with no previous DMI request.
UVM_INFO @ 13188192 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more tests.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 13 failures:
Test rv_dm_jtag_dmi_csr_bit_bash has 1 failures.
0.rv_dm_jtag_dmi_csr_bit_bash.96622573042025407698058263993827682911629909418885279980276460463794958486267
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_jtag_dmi_csr_bit_bash/latest/run.log
UVM_FATAL @ 50000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 50000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 50000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_dm_autoincr_sba_tl_access has 10 failures.
1.rv_dm_autoincr_sba_tl_access.74514191645737505937107067072032986254909635375012651510678652708141408449355
Line 305, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_autoincr_sba_tl_access/latest/run.log
UVM_FATAL @ 50000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 50000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 50000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.rv_dm_autoincr_sba_tl_access.15024121321674813832457695279335228307858272159972169568027668759275520238281
Line 548, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/2.rv_dm_autoincr_sba_tl_access/latest/run.log
UVM_FATAL @ 50000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 50000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 50000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 8 more failures.
Test rv_dm_bad_sba_tl_access has 2 failures.
6.rv_dm_bad_sba_tl_access.65623494471176978937734842638113973903692017546760166267462788280862572686509
Line 287, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/6.rv_dm_bad_sba_tl_access/latest/run.log
UVM_FATAL @ 50000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 50000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 50000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
11.rv_dm_bad_sba_tl_access.74846524768605368398625595323830308169700728212637015415421094087714723069700
Line 284, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/11.rv_dm_bad_sba_tl_access/latest/run.log
UVM_FATAL @ 50000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 50000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 50000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_scoreboard.sv:98) [scoreboard] Check failed item.dout & mask == selected_dtm_csr.get_mirrored_value() & mask (* [*] vs * [*]) has 11 failures:
1.rv_dm_stress_all_with_rand_reset.12488222960323151254438944277673635764160623751751096160800988877173794787856
Line 254, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 378001315 ps: (rv_dm_scoreboard.sv:98) [uvm_test_top.env.scoreboard] Check failed item.dout & mask == selected_dtm_csr.get_mirrored_value() & mask (17 [0x11] vs 4209 [0x1071])
UVM_INFO @ 378001315 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
6.rv_dm_stress_all_with_rand_reset.111953054335324106174063926534174603411872154128378762341100179087561029934884
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/6.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 236319866 ps: (rv_dm_scoreboard.sv:98) [uvm_test_top.env.scoreboard] Check failed item.dout & mask == selected_dtm_csr.get_mirrored_value() & mask (17 [0x11] vs 4209 [0x1071])
UVM_INFO @ 236319866 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
12.rv_dm_stress_all.8341348789502365005089461838244178942439035241787499505913214740545801259773
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/12.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 1014278294 ps: (rv_dm_scoreboard.sv:98) [uvm_test_top.env.scoreboard] Check failed item.dout & mask == selected_dtm_csr.get_mirrored_value() & mask (17 [0x11] vs 4209 [0x1071])
UVM_INFO @ 1014278294 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
19.rv_dm_stress_all.36597601839880713083067982237439918045628788700266117966661274706450916416198
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/19.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 56843943 ps: (rv_dm_scoreboard.sv:98) [uvm_test_top.env.scoreboard] Check failed item.dout & mask == selected_dtm_csr.get_mirrored_value() & mask (17 [0x11] vs 4209 [0x1071])
UVM_INFO @ 56843943 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
UVM_ERROR (rv_dm_smoke_vseq.sv:40) [seq] Check failed cfg.rv_dm_vif.cb.ndmreset_req == data (* [*] vs * [*]) has 9 failures:
2.rv_dm_tap_fsm_rand_reset.111817194158790788188897172815365267562812324104820095466720226183097626659969
Line 259, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/2.rv_dm_tap_fsm_rand_reset/latest/run.log
UVM_ERROR @ 2479213400 ps: (rv_dm_smoke_vseq.sv:40) [uvm_test_top.env.virtual_sequencer.rv_dm_tap_fsm_vseq.seq] Check failed cfg.rv_dm_vif.cb.ndmreset_req == data (0 [0x0] vs 1 [0x1])
UVM_INFO @ 2479213400 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.rv_dm_tap_fsm_rand_reset.13789194247511040815070299027756805377538142098738216757700301440532595936461
Line 336, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/3.rv_dm_tap_fsm_rand_reset/latest/run.log
UVM_ERROR @ 5871869266 ps: (rv_dm_smoke_vseq.sv:40) [uvm_test_top.env.virtual_sequencer.rv_dm_tap_fsm_vseq.seq] Check failed cfg.rv_dm_vif.cb.ndmreset_req == data (0 [0x0] vs 1 [0x1])
UVM_INFO @ 5871869266 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 7 more failures.
UVM_ERROR (rv_dm_smoke_vseq.sv:32) [seq] Check failed cfg.rv_dm_vif.cb.debug_req == data (* [*] vs * [*]) has 8 failures:
7.rv_dm_tap_fsm_rand_reset.73506823511937220103523117418100464187612630634549435617615077311208438995345
Line 288, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/7.rv_dm_tap_fsm_rand_reset/latest/run.log
UVM_ERROR @ 3202485558 ps: (rv_dm_smoke_vseq.sv:32) [uvm_test_top.env.virtual_sequencer.rv_dm_tap_fsm_vseq.seq] Check failed cfg.rv_dm_vif.cb.debug_req == data (0 [0x0] vs 1 [0x1])
UVM_INFO @ 3202485558 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
8.rv_dm_tap_fsm_rand_reset.86819682854097726235586650483149603652756198963504764545437135064162949888001
Line 311, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/8.rv_dm_tap_fsm_rand_reset/latest/run.log
UVM_ERROR @ 10030453433 ps: (rv_dm_smoke_vseq.sv:32) [uvm_test_top.env.virtual_sequencer.rv_dm_tap_fsm_vseq.seq] Check failed cfg.rv_dm_vif.cb.debug_req == data (0 [0x0] vs 1 [0x1])
UVM_INFO @ 10030453433 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 6 more failures.
UVM_ERROR (rv_dm_base_vseq.sv:167) [rv_dm_cmderr_not_supported_vseq] Check failed cmderr == get_field_val(jtag_dmi_ral.abstractcs.cmderr,rdata) (* [*] vs * [*]) has 6 failures:
4.rv_dm_stress_all.58699495307627650437677760460998143512692352089454478267777998241010129588634
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/4.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 1335070717 ps: (rv_dm_base_vseq.sv:167) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_not_supported_vseq] Check failed cmderr == get_field_val(jtag_dmi_ral.abstractcs.cmderr,rdata) (2 [0x2] vs 1 [0x1])
UVM_INFO @ 1335070717 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
9.rv_dm_stress_all.52171947823870557341713536237439966776264906978736552271721487345579691606526
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/9.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 974765960 ps: (rv_dm_base_vseq.sv:167) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_not_supported_vseq] Check failed cmderr == get_field_val(jtag_dmi_ral.abstractcs.cmderr,rdata) (2 [0x2] vs 1 [0x1])
UVM_INFO @ 974765960 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
4.rv_dm_stress_all_with_rand_reset.40092110227974824170818715721203506716969655114681937525648115383486997480311
Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/4.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1868380049 ps: (rv_dm_base_vseq.sv:167) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_not_supported_vseq] Check failed cmderr == get_field_val(jtag_dmi_ral.abstractcs.cmderr,rdata) (2 [0x2] vs 3 [0x3])
UVM_INFO @ 1868380049 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
41.rv_dm_stress_all_with_rand_reset.93095868649008971701880493548452547389209224729278096052020497599190957840654
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/41.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 413288645 ps: (rv_dm_base_vseq.sv:167) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_not_supported_vseq] Check failed cmderr == get_field_val(jtag_dmi_ral.abstractcs.cmderr,rdata) (2 [0x2] vs 3 [0x3])
UVM_INFO @ 413288645 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_scoreboard.sv:363) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: rv_dm_mem_reg_block.dataaddr_* has 5 failures:
3.rv_dm_stress_all_with_rand_reset.72705948843015685880688381445712196732998403428052353644268596607008694407215
Line 254, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/3.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 759716512 ps: (rv_dm_scoreboard.sv:363) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2450588752 [0x92110450] vs 2450638835 [0x9211c7f3]) reg name: rv_dm_mem_reg_block.dataaddr_1
UVM_INFO @ 759716512 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
26.rv_dm_stress_all_with_rand_reset.7033241066051484248898919134970236311746789690163802908308881235367987812646
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/26.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 100281365 ps: (rv_dm_scoreboard.sv:363) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2450588752 [0x92110450] vs 3843132928 [0xe5118e00]) reg name: rv_dm_mem_reg_block.dataaddr_1
UVM_INFO @ 100281365 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
UVM_ERROR (rv_dm_scoreboard.sv:83) [scoreboard] Check failed rwdata == * (* [*] vs * [*]) has 4 failures:
14.rv_dm_stress_all.11089380003695063247318184999679576307260896987468828503068384301727407927448
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/14.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 84947804 ps: (rv_dm_scoreboard.sv:83) [uvm_test_top.env.scoreboard] Check failed rwdata == 0 (1 [0x1] vs 0 [0x0])
UVM_INFO @ 84947804 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
17.rv_dm_stress_all.79413106078555208471645586178329690707853689288635457802675855867717422505563
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/17.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 2858871759 ps: (rv_dm_scoreboard.sv:83) [uvm_test_top.env.scoreboard] Check failed rwdata == 0 (1 [0x1] vs 0 [0x0])
UVM_INFO @ 2858871759 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_ERROR (rv_dm_smoke_vseq.sv:59) [seq] Check failed cfg.rv_dm_vif.cb.dmactive == data (* [*] vs * [*]) has 3 failures:
0.rv_dm_tap_fsm_rand_reset.1891084516073351389934362459758559706531158478231414978502703356961810138657
Line 368, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_tap_fsm_rand_reset/latest/run.log
UVM_ERROR @ 18573878477 ps: (rv_dm_smoke_vseq.sv:59) [uvm_test_top.env.virtual_sequencer.rv_dm_tap_fsm_vseq.seq] Check failed cfg.rv_dm_vif.cb.dmactive == data (0 [0x0] vs 1 [0x1])
UVM_INFO @ 18573878477 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
29.rv_dm_tap_fsm_rand_reset.89993120455292818675445887948782284137973781237098070908371056936363346104355
Line 293, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/29.rv_dm_tap_fsm_rand_reset/latest/run.log
UVM_ERROR @ 5971508203 ps: (rv_dm_smoke_vseq.sv:59) [uvm_test_top.env.virtual_sequencer.rv_dm_tap_fsm_vseq.seq] Check failed cfg.rv_dm_vif.cb.dmactive == data (0 [0x0] vs 1 [0x1])
UVM_INFO @ 5971508203 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR (jtag_dmi_monitor.sv:48) m_jtag_dmi_monitor [m_jtag_dmi_monitor] Bad packet: item: (jtag_item@5095) { ir_len: * dr_len: * ir: * dr: 'hxxxxxxxxxxxxxxxx dout: 'hxxxxxxxxxxxxxxxx bus_op: BusOpWrite skip_reselected_ir: * ir_pause_count: * dr_pause_count: * } has 3 failures:
Test rv_dm_tl_errors has 1 failures.
0.rv_dm_tl_errors.11042971512505177657295854914650071278714555123172225678465432768513990093304
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_tl_errors/latest/run.log
UVM_ERROR @ 2609049 ps: (jtag_dmi_monitor.sv:48) uvm_test_top.env.m_jtag_dmi_monitor [uvm_test_top.env.m_jtag_dmi_monitor] Bad packet: item: (jtag_item@5095) { ir_len: 'h0 dr_len: 'h0 ir: 'h0 dr: 'hxxxxxxxxxxxxxxxx dout: 'hxxxxxxxxxxxxxxxx bus_op: BusOpWrite skip_reselected_ir: 'h0 ir_pause_count: 'h0 dr_pause_count: 'h0 }
. ir_len & dr_len are both zero, or non-zero.
UVM_INFO @ 2609049 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_dm_hart_unavail has 1 failures.
1.rv_dm_hart_unavail.18724832958937600626195020630035711760815312361561403656219979772441447153584
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_hart_unavail/latest/run.log
UVM_ERROR @ 1311667 ps: (jtag_dmi_monitor.sv:48) uvm_test_top.env.m_jtag_dmi_monitor [uvm_test_top.env.m_jtag_dmi_monitor] Bad packet: item: (jtag_item@5095) { ir_len: 'h0 dr_len: 'h0 ir: 'h0 dr: 'hxxxxxxxxxxxxxxxx dout: 'hxxxxxxxxxxxxxxxx bus_op: BusOpWrite skip_reselected_ir: 'h0 ir_pause_count: 'h0 dr_pause_count: 'h0 }
. ir_len & dr_len are both zero, or non-zero.
UVM_INFO @ 1311667 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_dm_stress_all_with_rand_reset has 1 failures.
44.rv_dm_stress_all_with_rand_reset.10131361385001545705524648623755228726806843413143528893568168647868092836326
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/44.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 3117126 ps: (jtag_dmi_monitor.sv:48) uvm_test_top.env.m_jtag_dmi_monitor [uvm_test_top.env.m_jtag_dmi_monitor] Bad packet: item: (jtag_item@5095) { ir_len: 'h0 dr_len: 'h0 ir: 'h0 dr: 'hxxxxxxxxxxxxxxxx dout: 'hxxxxxxxxxxxxxxxx bus_op: BusOpWrite skip_reselected_ir: 'h0 ir_pause_count: 'h0 dr_pause_count: 'h0 }
. ir_len & dr_len are both zero, or non-zero.
UVM_INFO @ 3117126 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'rv_dm_tap_fsm_vseq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 3 failures:
4.rv_dm_tap_fsm_rand_reset.45226335838614319055448257697375232758442439334581391539103979467864984636789
Line 341, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/4.rv_dm_tap_fsm_rand_reset/latest/run.log
UVM_ERROR @ 12304964973 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_jtag_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_jtag_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.rv_dm_tap_fsm_vseq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
UVM_INFO @ 12304964973 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
11.rv_dm_tap_fsm_rand_reset.50658197292991483693220217978832722012406943190707673846257137399819154966721
Line 330, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/11.rv_dm_tap_fsm_rand_reset/latest/run.log
UVM_ERROR @ 25778519095 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_jtag_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_jtag_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.rv_dm_tap_fsm_vseq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
UVM_INFO @ 25778519095 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR (rv_dm_smoke_vseq.sv:48) [seq] Check failed cfg.rv_dm_vif.unavailable == get_field_val(jtag_dmi_ral.dmstatus.anyunavail, data) (* [*] vs * [*]) has 3 failures:
9.rv_dm_tap_fsm_rand_reset.18773252678253112015636578994428595128262450496276237977195259298917192016526
Line 256, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/9.rv_dm_tap_fsm_rand_reset/latest/run.log
UVM_ERROR @ 33010356 ps: (rv_dm_smoke_vseq.sv:48) [uvm_test_top.env.virtual_sequencer.rv_dm_tap_fsm_vseq.seq] Check failed cfg.rv_dm_vif.unavailable == get_field_val(jtag_dmi_ral.dmstatus.anyunavail, data) (1 [0x1] vs 0 [0x0])
UVM_INFO @ 33010356 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
17.rv_dm_tap_fsm_rand_reset.9573184830383138400540784069116931640889662716954705333331745002902414451949
Line 272, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/17.rv_dm_tap_fsm_rand_reset/latest/run.log
UVM_ERROR @ 2537048354 ps: (rv_dm_smoke_vseq.sv:48) [uvm_test_top.env.virtual_sequencer.rv_dm_tap_fsm_vseq.seq] Check failed cfg.rv_dm_vif.unavailable == get_field_val(jtag_dmi_ral.dmstatus.anyunavail, data) (1 [0x1] vs 0 [0x0])
UVM_INFO @ 2537048354 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_FATAL (csr_utils_pkg.sv:374) [csr_utils::csr_rd] Timeout waiting to csr_rd jtag_dtm_ral.idcode (addr=*) has 3 failures:
28.rv_dm_tap_fsm_rand_reset.70197951044408107292301811117962425332219374865655308077518486687147781422365
Line 336, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/28.rv_dm_tap_fsm_rand_reset/latest/run.log
UVM_FATAL @ 11449689904 ps: (csr_utils_pkg.sv:374) [csr_utils::csr_rd] Timeout waiting to csr_rd jtag_dtm_ral.idcode (addr=0x1)
UVM_INFO @ 11449689904 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
37.rv_dm_tap_fsm_rand_reset.90093057950768979393264142515243980870612148199852593906713994189851000123487
Line 272, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/37.rv_dm_tap_fsm_rand_reset/latest/run.log
UVM_FATAL @ 5595513990 ps: (csr_utils_pkg.sv:374) [csr_utils::csr_rd] Timeout waiting to csr_rd jtag_dtm_ral.idcode (addr=0x1)
UVM_INFO @ 5595513990 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Exit reason: Error: User command failed Error-[NOA] Null object access has 2 failures:
0.rv_dm_abstractcmd_status.49034563786536246041708908667567494571476709250026769240057639850971273053488
Line 252, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_abstractcmd_status/latest/run.log
Error-[NOA] Null object access
../src/lowrisc_dv_dv_base_reg_0/dv_base_reg_pkg.sv, 73
The object at dereference depth 0 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
1.rv_dm_abstractcmd_status.86105068598739639775811906682365587353907450714500116004747445032041115576005
Line 252, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_abstractcmd_status/latest/run.log
Error-[NOA] Null object access
../src/lowrisc_dv_dv_base_reg_0/dv_base_reg_pkg.sv, 73
The object at dereference depth 0 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
UVM_ERROR (rv_dm_jtag_dtm_hard_reset_vseq.sv:27) [rv_dm_jtag_dtm_hard_reset_vseq] Check failed wdata == rdata* (* [*] vs * [*]) has 2 failures:
5.rv_dm_stress_all_with_rand_reset.71752909858631679665873391713434937780795793461995533845278571246879558679556
Line 286, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/5.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 52586904485 ps: (rv_dm_jtag_dtm_hard_reset_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dtm_hard_reset_vseq] Check failed wdata == rdata1 (3 [0x3] vs 0 [0x0])
UVM_INFO @ 52586904485 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
33.rv_dm_stress_all_with_rand_reset.94805735710254739222697886107629165897571879364966359852975560162546439301757
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/33.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 560160717 ps: (rv_dm_jtag_dtm_hard_reset_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dtm_hard_reset_vseq] Check failed wdata == rdata1 (5 [0x5] vs 22533 [0x5805])
UVM_INFO @ 560160717 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_base_vseq.sv:167) [rv_dm_cmderr_busy_vseq] Check failed cmderr == get_field_val(jtag_dmi_ral.abstractcs.cmderr,rdata) (* [*] vs * [*]) has 2 failures:
8.rv_dm_stress_all_with_rand_reset.83448607924957294857606672968828833571171758204804432582491491139264440159509
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/8.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 301458052 ps: (rv_dm_base_vseq.sv:167) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_busy_vseq] Check failed cmderr == get_field_val(jtag_dmi_ral.abstractcs.cmderr,rdata) (1 [0x1] vs 3 [0x3])
UVM_INFO @ 301458052 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
39.rv_dm_stress_all_with_rand_reset.28715861980524797973615970909802471285256903286674943825112999522595430171595
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/39.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 95141503 ps: (rv_dm_base_vseq.sv:167) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_busy_vseq] Check failed cmderr == get_field_val(jtag_dmi_ral.abstractcs.cmderr,rdata) (1 [0x1] vs 3 [0x3])
UVM_INFO @ 95141503 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_halt_resume_whereto_vseq.sv:27) [rv_dm_halt_resume_whereto_vseq] Check failed * == get_field_val(jtag_dmi_ral.abstractcs.busy,rdata) (* [*] vs * [*]) has 2 failures:
31.rv_dm_stress_all.86201801028197037309367756674434970174975523064610715845363800486049967304230
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/31.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 12626484 ps: (rv_dm_halt_resume_whereto_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.rv_dm_halt_resume_whereto_vseq] Check failed 1 == get_field_val(jtag_dmi_ral.abstractcs.busy,rdata) (1 [0x1] vs 0 [0x0])
UVM_INFO @ 12626484 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
40.rv_dm_stress_all.618916061698127590587399891864652624387603723365366288505495964861900195726
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/40.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 3860314989 ps: (rv_dm_halt_resume_whereto_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.rv_dm_halt_resume_whereto_vseq] Check failed 1 == get_field_val(jtag_dmi_ral.abstractcs.busy,rdata) (1 [0x1] vs 0 [0x0])
UVM_INFO @ 3860314989 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:462) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: jtag_dmi_ral.progbuf_* reset value: * has 1 failures:
4.rv_dm_jtag_dmi_csr_rw.76707159569723284964016768840841222113764986893473874595159518958541877178829
Line 252, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/4.rv_dm_jtag_dmi_csr_rw/latest/run.log
UVM_ERROR @ 101526411 ps: (csr_utils_pkg.sv:462) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 3635903482 [0xd8b77bfa]) Regname: jtag_dmi_ral.progbuf_3 reset value: 0x0
UVM_INFO @ 101526411 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_halt_resume_whereto_vseq.sv:33) [rv_dm_halt_resume_whereto_vseq] Check failed * == get_field_val(jtag_dmi_ral.abstractcs.busy,rdata) (* [*] vs * [*]) has 1 failures:
17.rv_dm_stress_all_with_rand_reset.111077609966826917652565478933402475862940579802383060565165494572941033143438
Line 254, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/17.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 384539004 ps: (rv_dm_halt_resume_whereto_vseq.sv:33) [uvm_test_top.env.virtual_sequencer.rv_dm_halt_resume_whereto_vseq] Check failed 1 == get_field_val(jtag_dmi_ral.abstractcs.busy,rdata) (1 [0x1] vs 0 [0x0])
UVM_INFO @ 384539004 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 1 failures:
18.rv_dm_tap_fsm_rand_reset.107682376649562765606284664211925656967880573579033047202457413636447567738228
Line 265, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/18.rv_dm_tap_fsm_rand_reset/latest/run.log
UVM_ERROR @ 2304812591 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_jtag_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_jtag_agent.sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
UVM_INFO @ 2304812591 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_mem_tl_access_resuming_vseq.sv:41) [rv_dm_mem_tl_access_resuming_vseq] Check failed * == get_field_val(jtag_dmi_ral.dmstatus.anyrunning, rdata) (* [*] vs * [*]) has 1 failures:
25.rv_dm_stress_all_with_rand_reset.24986342911589117813727903021727228703761012016378163336937690542465928089990
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/25.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 280187800 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:41) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed 1 == get_field_val(jtag_dmi_ral.dmstatus.anyrunning, rdata) (1 [0x1] vs 0 [0x0])
UVM_INFO @ 280187800 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_jtag_dmi_dm_inactive_vseq.sv:33) [rv_dm_jtag_dmi_dm_inactive_vseq] Check failed rdata == jtag_dmi_ral.abstractdata[*].get_reset() (* [*] vs * [*]) has 1 failures:
29.rv_dm_stress_all.46215339053538479279794359646199054753087284045372384371460348095222817827745
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/29.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 3341736105 ps: (rv_dm_jtag_dmi_dm_inactive_vseq.sv:33) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_dm_inactive_vseq] Check failed rdata == jtag_dmi_ral.abstractdata[0].get_reset() (2958143569 [0xb051b051] vs 0 [0x0])
UVM_INFO @ 3341736105 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:216) [csr_utils::csr_wr] Timeout waiting to csr_wr rv_dm_mem_reg_block.halted (addr=*) has 1 failures:
42.rv_dm_stress_all.48706406752337216645146717309360178985704330262639885996895706509958254344803
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/42.rv_dm_stress_all/latest/run.log
UVM_FATAL @ 5440819377 ps: (csr_utils_pkg.sv:216) [csr_utils::csr_wr] Timeout waiting to csr_wr rv_dm_mem_reg_block.halted (addr=0xc2230100)
UVM_INFO @ 5440819377 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_halt_resume_whereto_vseq.sv:42) [rv_dm_halt_resume_whereto_vseq] Check failed * == get_field_val(jtag_dmi_ral.abstractcs.busy,rdata) (* [*] vs * [*]) has 1 failures:
47.rv_dm_stress_all_with_rand_reset.70307598879888074175932027220168974973030537810721613567912749715140670074975
Line 256, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/47.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 523150190 ps: (rv_dm_halt_resume_whereto_vseq.sv:42) [uvm_test_top.env.virtual_sequencer.rv_dm_halt_resume_whereto_vseq] Check failed 1 == get_field_val(jtag_dmi_ral.abstractcs.busy,rdata) (1 [0x1] vs 0 [0x0])
UVM_INFO @ 523150190 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---