SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_lc_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_pm_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_tlul_lc_gate_sba.u_err_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_tlul_lc_gate_rom.u_err_en_sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
88.73 | 100.00 | 75.86 | 91.55 | 87.50 | dut |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
88.73 | 100.00 | 75.86 | 91.55 | 87.50 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
68.13 | 86.27 | 72.22 | 57.14 | 75.00 | 50.00 | u_tlul_lc_gate_sba |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
81.44 | 96.08 | 77.78 | 100.00 | 83.33 | 50.00 | u_tlul_lc_gate_rom |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 6 | 6 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 5 | 5 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 3 | 3 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 4 | 4 | 100.00 | 4 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 4 | 4 | 100.00 | 4 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 660 | 660 | 0 | 0 |
OutputsKnown_A | 106845076 | 106629604 | 0 | 0 |
gen_flops.OutputDelay_A | 53422538 | 53309990 | 0 | 990 |
gen_no_flops.OutputDelay_A | 53422538 | 53314802 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 660 | 660 | 0 | 0 |
T1 | 4 | 4 | 0 | 0 |
T2 | 4 | 4 | 0 | 0 |
T3 | 4 | 4 | 0 | 0 |
T9 | 4 | 4 | 0 | 0 |
T23 | 4 | 4 | 0 | 0 |
T24 | 4 | 4 | 0 | 0 |
T36 | 4 | 4 | 0 | 0 |
T37 | 4 | 4 | 0 | 0 |
T38 | 4 | 4 | 0 | 0 |
T39 | 4 | 4 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 106845076 | 106629604 | 0 | 0 |
T1 | 594672 | 593120 | 0 | 0 |
T2 | 1168360 | 1166568 | 0 | 0 |
T3 | 1128784 | 1128580 | 0 | 0 |
T9 | 454460 | 454160 | 0 | 0 |
T23 | 1190632 | 1190600 | 0 | 0 |
T24 | 26080 | 25780 | 0 | 0 |
T36 | 742252 | 741964 | 0 | 0 |
T37 | 560624 | 557944 | 0 | 0 |
T38 | 746964 | 742184 | 0 | 0 |
T39 | 5628 | 5428 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 53422538 | 53309990 | 0 | 990 |
T1 | 297336 | 296524 | 0 | 6 |
T2 | 584180 | 583242 | 0 | 6 |
T3 | 564392 | 564284 | 0 | 6 |
T9 | 227230 | 227074 | 0 | 6 |
T23 | 595316 | 595298 | 0 | 6 |
T24 | 13040 | 12884 | 0 | 6 |
T36 | 371126 | 370976 | 0 | 6 |
T37 | 280312 | 278918 | 0 | 6 |
T38 | 373482 | 370984 | 0 | 6 |
T39 | 2814 | 2708 | 0 | 6 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 53422538 | 53314802 | 0 | 0 |
T1 | 297336 | 296560 | 0 | 0 |
T2 | 584180 | 583284 | 0 | 0 |
T3 | 564392 | 564290 | 0 | 0 |
T9 | 227230 | 227080 | 0 | 0 |
T23 | 595316 | 595300 | 0 | 0 |
T24 | 13040 | 12890 | 0 | 0 |
T36 | 371126 | 370982 | 0 | 0 |
T37 | 280312 | 278972 | 0 | 0 |
T38 | 373482 | 371092 | 0 | 0 |
T39 | 2814 | 2714 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 6 | 6 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 5 | 5 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 165 | 165 | 0 | 0 |
OutputsKnown_A | 26711269 | 26657401 | 0 | 0 |
gen_flops.OutputDelay_A | 26711269 | 26654995 | 0 | 495 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 165 | 165 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T23 | 1 | 1 | 0 | 0 |
T24 | 1 | 1 | 0 | 0 |
T36 | 1 | 1 | 0 | 0 |
T37 | 1 | 1 | 0 | 0 |
T38 | 1 | 1 | 0 | 0 |
T39 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 26711269 | 26657401 | 0 | 0 |
T1 | 148668 | 148280 | 0 | 0 |
T2 | 292090 | 291642 | 0 | 0 |
T3 | 282196 | 282145 | 0 | 0 |
T9 | 113615 | 113540 | 0 | 0 |
T23 | 297658 | 297650 | 0 | 0 |
T24 | 6520 | 6445 | 0 | 0 |
T36 | 185563 | 185491 | 0 | 0 |
T37 | 140156 | 139486 | 0 | 0 |
T38 | 186741 | 185546 | 0 | 0 |
T39 | 1407 | 1357 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 26711269 | 26654995 | 0 | 495 |
T1 | 148668 | 148262 | 0 | 3 |
T2 | 292090 | 291621 | 0 | 3 |
T3 | 282196 | 282142 | 0 | 3 |
T9 | 113615 | 113537 | 0 | 3 |
T23 | 297658 | 297649 | 0 | 3 |
T24 | 6520 | 6442 | 0 | 3 |
T36 | 185563 | 185488 | 0 | 3 |
T37 | 140156 | 139459 | 0 | 3 |
T38 | 186741 | 185492 | 0 | 3 |
T39 | 1407 | 1354 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 3 | 3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 165 | 165 | 0 | 0 |
OutputsKnown_A | 26711269 | 26657401 | 0 | 0 |
gen_flops.OutputDelay_A | 26711269 | 26654995 | 0 | 495 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 165 | 165 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T23 | 1 | 1 | 0 | 0 |
T24 | 1 | 1 | 0 | 0 |
T36 | 1 | 1 | 0 | 0 |
T37 | 1 | 1 | 0 | 0 |
T38 | 1 | 1 | 0 | 0 |
T39 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 26711269 | 26657401 | 0 | 0 |
T1 | 148668 | 148280 | 0 | 0 |
T2 | 292090 | 291642 | 0 | 0 |
T3 | 282196 | 282145 | 0 | 0 |
T9 | 113615 | 113540 | 0 | 0 |
T23 | 297658 | 297650 | 0 | 0 |
T24 | 6520 | 6445 | 0 | 0 |
T36 | 185563 | 185491 | 0 | 0 |
T37 | 140156 | 139486 | 0 | 0 |
T38 | 186741 | 185546 | 0 | 0 |
T39 | 1407 | 1357 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 26711269 | 26654995 | 0 | 495 |
T1 | 148668 | 148262 | 0 | 3 |
T2 | 292090 | 291621 | 0 | 3 |
T3 | 282196 | 282142 | 0 | 3 |
T9 | 113615 | 113537 | 0 | 3 |
T23 | 297658 | 297649 | 0 | 3 |
T24 | 6520 | 6442 | 0 | 3 |
T36 | 185563 | 185488 | 0 | 3 |
T37 | 140156 | 139459 | 0 | 3 |
T38 | 186741 | 185492 | 0 | 3 |
T39 | 1407 | 1354 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 165 | 165 | 0 | 0 |
OutputsKnown_A | 26711269 | 26657401 | 0 | 0 |
gen_no_flops.OutputDelay_A | 26711269 | 26657401 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 165 | 165 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T23 | 1 | 1 | 0 | 0 |
T24 | 1 | 1 | 0 | 0 |
T36 | 1 | 1 | 0 | 0 |
T37 | 1 | 1 | 0 | 0 |
T38 | 1 | 1 | 0 | 0 |
T39 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 26711269 | 26657401 | 0 | 0 |
T1 | 148668 | 148280 | 0 | 0 |
T2 | 292090 | 291642 | 0 | 0 |
T3 | 282196 | 282145 | 0 | 0 |
T9 | 113615 | 113540 | 0 | 0 |
T23 | 297658 | 297650 | 0 | 0 |
T24 | 6520 | 6445 | 0 | 0 |
T36 | 185563 | 185491 | 0 | 0 |
T37 | 140156 | 139486 | 0 | 0 |
T38 | 186741 | 185546 | 0 | 0 |
T39 | 1407 | 1357 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 26711269 | 26657401 | 0 | 0 |
T1 | 148668 | 148280 | 0 | 0 |
T2 | 292090 | 291642 | 0 | 0 |
T3 | 282196 | 282145 | 0 | 0 |
T9 | 113615 | 113540 | 0 | 0 |
T23 | 297658 | 297650 | 0 | 0 |
T24 | 6520 | 6445 | 0 | 0 |
T36 | 185563 | 185491 | 0 | 0 |
T37 | 140156 | 139486 | 0 | 0 |
T38 | 186741 | 185546 | 0 | 0 |
T39 | 1407 | 1357 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 165 | 165 | 0 | 0 |
OutputsKnown_A | 26711269 | 26657401 | 0 | 0 |
gen_no_flops.OutputDelay_A | 26711269 | 26657401 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 165 | 165 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T23 | 1 | 1 | 0 | 0 |
T24 | 1 | 1 | 0 | 0 |
T36 | 1 | 1 | 0 | 0 |
T37 | 1 | 1 | 0 | 0 |
T38 | 1 | 1 | 0 | 0 |
T39 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 26711269 | 26657401 | 0 | 0 |
T1 | 148668 | 148280 | 0 | 0 |
T2 | 292090 | 291642 | 0 | 0 |
T3 | 282196 | 282145 | 0 | 0 |
T9 | 113615 | 113540 | 0 | 0 |
T23 | 297658 | 297650 | 0 | 0 |
T24 | 6520 | 6445 | 0 | 0 |
T36 | 185563 | 185491 | 0 | 0 |
T37 | 140156 | 139486 | 0 | 0 |
T38 | 186741 | 185546 | 0 | 0 |
T39 | 1407 | 1357 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 26711269 | 26657401 | 0 | 0 |
T1 | 148668 | 148280 | 0 | 0 |
T2 | 292090 | 291642 | 0 | 0 |
T3 | 282196 | 282145 | 0 | 0 |
T9 | 113615 | 113540 | 0 | 0 |
T23 | 297658 | 297650 | 0 | 0 |
T24 | 6520 | 6445 | 0 | 0 |
T36 | 185563 | 185491 | 0 | 0 |
T37 | 140156 | 139486 | 0 | 0 |
T38 | 186741 | 185546 | 0 | 0 |
T39 | 1407 | 1357 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |