Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : rv_dm
SCORELINECONDTOGGLEFSMBRANCHASSERT
88.73 100.00 75.86 91.55 87.50

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_rv_dm_0.1/rtl/rv_dm.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut 88.73 100.00 75.86 91.55 87.50



Module Instance : tb.dut

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
88.73 100.00 75.86 91.55 87.50


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
86.50 92.87 79.06 89.36 76.92 83.07 97.75


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
tb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
dap 86.20 98.68 92.76 70.00 94.57 75.00
gen_alert_tx[0].u_prim_alert_sender 83.33 83.33
i_tlul_adapter_reg 93.27 99.00 80.90 93.33 93.10 100.00
rv_dm_regs_csr_assert 0.00 0.00
tl_adapter_host_sba 95.14 100.00 100.00 75.71 100.00 100.00
tlul_assert_device_mem 95.24 100.00 85.71 100.00
tlul_assert_device_regs 94.54 100.00 85.71 97.90
tlul_assert_host_sba 94.30 100.00 85.71 97.18
u_dm_top 84.72 86.73 64.48 100.00 72.40 100.00
u_lc_en_sync 100.00 100.00 100.00 100.00
u_pm_en_sync 100.00 100.00 100.00 100.00
u_prim_clock_mux2 100.00 100.00 100.00 100.00
u_prim_rst_n_mux2 100.00 100.00 100.00 100.00
u_reg_regs 94.73 93.50 93.58 93.49 93.10 100.00
u_tlul_lc_gate_rom 83.22 93.94 57.50 100.00 77.14 87.50
u_tlul_lc_gate_sba 72.24 90.15 55.00 57.14 71.43 87.50


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : rv_dm
Line No.TotalCoveredPercent
TOTAL1515100.00
CONT_ASSIGN10911100.00
CONT_ASSIGN11011100.00
CONT_ASSIGN11511100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN14111100.00
CONT_ASSIGN20611100.00
CONT_ASSIGN20711100.00
CONT_ASSIGN21111100.00
CONT_ASSIGN29411100.00
CONT_ASSIGN30011100.00
CONT_ASSIGN30211100.00
CONT_ASSIGN30811100.00
CONT_ASSIGN30911100.00
CONT_ASSIGN38411100.00
CONT_ASSIGN41211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rv_dm_0.1/rtl/rv_dm.sv' or '../src/lowrisc_ip_rv_dm_0.1/rtl/rv_dm.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
109 1 1
110 1 1
115 1 1
118 1 1
141 1 1
206 1 1
207 1 1
211 1 1
294 1 1
300 1 1
302 1 1
308 1 1
309 1 1
384 1 1
412 1 1


Cond Coverage for Module : rv_dm
TotalCoveredPercent
Conditions292275.86
Logical292275.86
Non-Logical00
Event00

 LINE       115
 EXPRESSION (regs_intg_error | rom_intg_error | sba_gate_intg_error | rom_gate_intg_error)
             -------1-------   -------2------   ---------3---------   ---------4---------
-1--2--3--4-StatusTests
0000CoveredT1,T2,T3
0001Not Covered
0010Not Covered
0100Not Covered
1000CoveredT44,T45,T46

 LINE       118
 SUB-EXPRESSION (regs_reg2hw.alert_test.q & regs_reg2hw.alert_test.qe)
                 ------------1-----------   ------------2------------
-1--2-StatusTests
01CoveredT39,T42,T43
10CoveredT3,T24,T39
11CoveredT39,T42,T43

 LINE       207
 EXPRESSION (ndmreset_req_qual & reset_req_en)
             --------1--------   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT9,T21,T28

 LINE       302
 EXPRESSION (debug_req & debug_req_en)
             ----1----   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT7,T21,T8

 LINE       337
 EXPRESSION (dmi_req_ready & dmi_en)
             ------1------   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT16,T63,T5
11CoveredT1,T2,T3

 LINE       337
 EXPRESSION (dmi_rsp_valid & dmi_en)
             ------1------   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       412
 EXPRESSION (device_we || device_re)
             ----1----    ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT9,T6,T30
10CoveredT9,T7,T4

 LINE       428
 EXPRESSION (dmi_req_valid & dmi_en)
             ------1------   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       428
 EXPRESSION (dmi_rsp_ready & dmi_en)
             ------1------   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT16,T63,T5
11CoveredT1,T2,T3

Toggle Coverage for Module : rv_dm
TotalCoveredPercent
Totals 94 75 79.79
Total Bits 1112 1018 91.55
Total Bits 0->1 556 509 91.55
Total Bits 1->0 556 509 91.55

Ports 94 75 79.79
Port Bits 1112 1018 91.55
Port Bits 0->1 556 509 91.55
Port Bits 1->0 556 509 91.55

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T2,T37 Yes T1,T2,T3 INPUT
lc_hw_debug_en_i[3:0] Yes Yes T16,T41,T20 Yes T16,T5,T25 INPUT
pinmux_hw_debug_en_i[3:0] Yes Yes T16,T41,T20 Yes T16,T5,T25 INPUT
scanmode_i[0] No No Yes T5,T19,T71 INPUT
scanmode_i[2:1] No Yes T5,T19,T71 No INPUT
scanmode_i[3] No No Yes T5,T19,T71 INPUT
scan_rst_ni Yes Yes T1,T2,T37 Yes T1,T2,T3 INPUT
ndmreset_req_o Yes Yes T9,T21,T28 Yes T9,T21,T28 OUTPUT
dmactive_o Yes Yes T1,T2,T37 Yes T1,T2,T3 OUTPUT
debug_req_o Yes Yes T21,T28,T5 Yes T7,T21,T8 OUTPUT
unavailable_i Yes Yes T9,T11,T21 Yes T9,T21,T22 INPUT
regs_tl_d_i.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
regs_tl_d_i.a_user.data_intg[6:0] Yes Yes T39,T61,T42 Yes T3,T39,T61 INPUT
regs_tl_d_i.a_user.cmd_intg[6:0] Yes Yes T39,T61,T42 Yes T3,T24,T39 INPUT
regs_tl_d_i.a_user.instr_type[3:0] Yes Yes T24,T39,T61 Yes T39,T61,T64 INPUT
regs_tl_d_i.a_user.rsvd[4:0] Yes Yes T3,T39,T61 Yes T39,T61,T55 INPUT
regs_tl_d_i.a_data[31:0] Yes Yes T39,T61,T42 Yes T3,T24,T39 INPUT
regs_tl_d_i.a_mask[3:0] Yes Yes T39,T61,T16 Yes T39,T61,T64 INPUT
regs_tl_d_i.a_address[31:0] Yes Yes T39,T61,T64 Yes T3,T24,T39 INPUT
regs_tl_d_i.a_source[7:0] Yes Yes T39,T61,T43 Yes T39,T61,T16 INPUT
regs_tl_d_i.a_size[1:0] Yes Yes T39,T61,T42 Yes T24,T39,T61 INPUT
regs_tl_d_i.a_param[2:0] Yes Yes T3,T39,T61 Yes T39,T61,T16 INPUT
regs_tl_d_i.a_opcode[2:0] Yes Yes T24,T39,T61 Yes T39,T61,T42 INPUT
regs_tl_d_i.a_valid Yes Yes T39,T42,T43 Yes T39,T42,T43 INPUT
regs_tl_d_o.a_ready Yes Yes T39,T42,T43 Yes T39,T42,T43 OUTPUT
regs_tl_d_o.d_error Yes Yes T47,T48,T49 Yes T50,T47,T72 OUTPUT
regs_tl_d_o.d_user.data_intg[6:0] No No No OUTPUT
regs_tl_d_o.d_user.rsp_intg[5:0] Yes Yes *T39,*T42,*T43 Yes T39,T42,T43 OUTPUT
regs_tl_d_o.d_user.rsp_intg[6] No No No OUTPUT
regs_tl_d_o.d_data[31:0] Yes Yes T47,T53,T48 Yes T39,T42,T43 OUTPUT
regs_tl_d_o.d_sink No No No OUTPUT
regs_tl_d_o.d_source[7:0] Yes Yes T39,T43,T56 Yes T39,T42,T43 OUTPUT
regs_tl_d_o.d_size[1:0] Yes Yes T39,T42,T43 Yes T39,T42,T43 OUTPUT
regs_tl_d_o.d_param[2:0] No No No OUTPUT
regs_tl_d_o.d_opcode[0] Yes Yes *T50,*T47,*T72 Yes T50,T47,T53 OUTPUT
regs_tl_d_o.d_opcode[2:1] No No No OUTPUT
regs_tl_d_o.d_valid Yes Yes T39,T42,T43 Yes T39,T42,T43 OUTPUT
mem_tl_d_i.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
mem_tl_d_i.a_user.data_intg[6:0] Yes Yes T9,T7,T55 Yes T9,T7,T54 INPUT
mem_tl_d_i.a_user.cmd_intg[6:0] Yes Yes T24,T9,T7 Yes T9,T7,T73 INPUT
mem_tl_d_i.a_user.instr_type[3:0] Yes Yes T7,T55,T73 Yes T7,T54,T73 INPUT
mem_tl_d_i.a_user.rsvd[4:0] Yes Yes T3,T7,T73 Yes T7,T55,T73 INPUT
mem_tl_d_i.a_data[31:0] Yes Yes T24,T9,T7 Yes T3,T9,T7 INPUT
mem_tl_d_i.a_mask[3:0] Yes Yes T9,T7,T73 Yes T24,T9,T7 INPUT
mem_tl_d_i.a_address[31:0] Yes Yes T9,T7,T73 Yes T3,T24,T9 INPUT
mem_tl_d_i.a_source[7:0] Yes Yes T7,T55,T73 Yes T3,T7,T54 INPUT
mem_tl_d_i.a_size[1:0] Yes Yes T24,T9,T7 Yes T9,T7,T55 INPUT
mem_tl_d_i.a_param[2:0] Yes Yes T3,T7,T73 Yes T54,T73,T4 INPUT
mem_tl_d_i.a_opcode[2:0] Yes Yes T9,T7,T55 Yes T3,T24,T9 INPUT
mem_tl_d_i.a_valid Yes Yes T9,T7,T4 Yes T9,T7,T4 INPUT
mem_tl_d_o.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mem_tl_d_o.d_error Yes Yes T1,T2,T3 Yes T1,T2,T37 OUTPUT
mem_tl_d_o.d_user.data_intg[6:0] Yes Yes T9,T6,T30 Yes T9,T6,T30 OUTPUT
mem_tl_d_o.d_user.rsp_intg[5:0] Yes Yes T9,*T7,*T8 Yes T9,T7,T4 OUTPUT
mem_tl_d_o.d_user.rsp_intg[6] No No No OUTPUT
mem_tl_d_o.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T37 OUTPUT
mem_tl_d_o.d_sink No No No OUTPUT
mem_tl_d_o.d_source[7:0] Yes Yes T7,T5,T6 Yes T9,T7,T4 OUTPUT
mem_tl_d_o.d_size[1:0] Yes Yes T9,T7,T4 Yes T9,T7,T4 OUTPUT
mem_tl_d_o.d_param[2:0] No No No OUTPUT
mem_tl_d_o.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T37 OUTPUT
mem_tl_d_o.d_opcode[2:1] No No No OUTPUT
mem_tl_d_o.d_valid Yes Yes T9,T7,T4 Yes T9,T7,T4 OUTPUT
sba_tl_h_o.d_ready Yes Yes T1,T2,T37 Yes T1,T2,T3 OUTPUT
sba_tl_h_o.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
sba_tl_h_o.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
sba_tl_h_o.a_user.instr_type[0] Yes Yes *T1,*T2,*T37 Yes T1,T2,T3 OUTPUT
sba_tl_h_o.a_user.instr_type[2:1] No No No OUTPUT
sba_tl_h_o.a_user.instr_type[3] Yes Yes T1,T2,T37 Yes T1,T2,T3 OUTPUT
sba_tl_h_o.a_user.rsvd[4:0] No No No OUTPUT
sba_tl_h_o.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
sba_tl_h_o.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
sba_tl_h_o.a_address[1:0] No No No OUTPUT
sba_tl_h_o.a_address[31:2] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
sba_tl_h_o.a_source[7:0] No No No OUTPUT
sba_tl_h_o.a_size[0] No No No OUTPUT
sba_tl_h_o.a_size[1] Yes Yes T1,T2,T37 Yes T1,T2,T3 OUTPUT
sba_tl_h_o.a_param[2:0] No No No OUTPUT
sba_tl_h_o.a_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
sba_tl_h_o.a_opcode[1] No No No OUTPUT
sba_tl_h_o.a_opcode[2] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
sba_tl_h_o.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
sba_tl_h_i.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
sba_tl_h_i.d_error Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
sba_tl_h_i.d_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
sba_tl_h_i.d_user.rsp_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
sba_tl_h_i.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
sba_tl_h_i.d_sink Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
sba_tl_h_i.d_source[7:0] Yes Yes T3,T36,T23 Yes T3,T36,T23 INPUT
sba_tl_h_i.d_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
sba_tl_h_i.d_param[2:0] Yes Yes T3,T36,T23 Yes T3,T36,T23 INPUT
sba_tl_h_i.d_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
sba_tl_h_i.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T39,T42,T43 Yes T39,T42,T43 INPUT
alert_rx_i[0].ping_n No No No INPUT
alert_rx_i[0].ping_p No No No INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T39,T42,T43 Yes T39,T42,T43 OUTPUT
jtag_i.tdi Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
jtag_i.trst_n Yes Yes T1,T2,T37 Yes T1,T2,T3 INPUT
jtag_i.tms Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
jtag_i.tck Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
jtag_o.tdo_oe Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
jtag_o.tdo Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT

*Tests covering at least one bit in the range

Assert Coverage for Module : rv_dm
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 16 16 100.00 14 87.50
Cover properties 0 0 0
Cover sequences 0 0 0
Total 16 16 100.00 14 87.50




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DebugReqOKnown_A 26711269 26657401 0 0
DmactiveOKnown_A 26711269 26657401 0 0
FpvSecCmRegWeOnehotCheck_A 26711269 80 0 0
FpvSecCmRomTlLcGateFsm_A 26711269 0 0 0
FpvSecCmSbaTlLcGateFsm_A 26711269 0 0 0
JtagRspOTdoKnown_A 11469420 11468880 0 0
JtagRspOTdoOeKnown_A 11469420 11468880 0 0
NdmresetOKnown_A 26711269 26657401 0 0
RvDmLcEnDebugVal_A 26711269 26657401 0 0
TlMemAReadyKnown_A 26711269 26657401 0 0
TlMemDValidKnown_A 26711269 26657401 0 0
TlRegsAReadyKnown_A 26711269 26657401 0 0
TlRegsDValidKnown_A 26711269 26657401 0 0
TlSbaAValidKnown_A 26711269 26657401 0 0
TlSbaDReadyKnown_A 26711269 26657401 0 0
paramCheckNrHarts 165 165 0 0


DebugReqOKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 26711269 26657401 0 0
T1 148668 148280 0 0
T2 292090 291642 0 0
T3 282196 282145 0 0
T9 113615 113540 0 0
T23 297658 297650 0 0
T24 6520 6445 0 0
T36 185563 185491 0 0
T37 140156 139486 0 0
T38 186741 185546 0 0
T39 1407 1357 0 0

DmactiveOKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 26711269 26657401 0 0
T1 148668 148280 0 0
T2 292090 291642 0 0
T3 282196 282145 0 0
T9 113615 113540 0 0
T23 297658 297650 0 0
T24 6520 6445 0 0
T36 185563 185491 0 0
T37 140156 139486 0 0
T38 186741 185546 0 0
T39 1407 1357 0 0

FpvSecCmRegWeOnehotCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 26711269 80 0 0
T11 1861 0 0 0
T17 4639 0 0 0
T21 21935 0 0 0
T44 10308 20 0 0
T45 0 20 0 0
T46 0 10 0 0
T56 2216 0 0 0
T57 1292 0 0 0
T58 955 0 0 0
T73 802429 0 0 0
T74 0 20 0 0
T75 0 10 0 0
T76 333185 0 0 0
T77 359566 0 0 0

FpvSecCmRomTlLcGateFsm_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 26711269 0 0 0

FpvSecCmSbaTlLcGateFsm_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 26711269 0 0 0

JtagRspOTdoKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11469420 11468880 0 0
T1 504112 504055 0 0
T2 91293 91287 0 0
T3 386762 386762 0 0
T9 10857 10857 0 0
T23 128908 128908 0 0
T24 564 564 0 0
T36 22547 22547 0 0
T37 74047 74039 0 0
T38 168724 168707 0 0
T39 107 107 0 0

JtagRspOTdoOeKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11469420 11468880 0 0
T1 504112 504055 0 0
T2 91293 91287 0 0
T3 386762 386762 0 0
T9 10857 10857 0 0
T23 128908 128908 0 0
T24 564 564 0 0
T36 22547 22547 0 0
T37 74047 74039 0 0
T38 168724 168707 0 0
T39 107 107 0 0

NdmresetOKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 26711269 26657401 0 0
T1 148668 148280 0 0
T2 292090 291642 0 0
T3 282196 282145 0 0
T9 113615 113540 0 0
T23 297658 297650 0 0
T24 6520 6445 0 0
T36 185563 185491 0 0
T37 140156 139486 0 0
T38 186741 185546 0 0
T39 1407 1357 0 0

RvDmLcEnDebugVal_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 26711269 26657401 0 0
T1 148668 148280 0 0
T2 292090 291642 0 0
T3 282196 282145 0 0
T9 113615 113540 0 0
T23 297658 297650 0 0
T24 6520 6445 0 0
T36 185563 185491 0 0
T37 140156 139486 0 0
T38 186741 185546 0 0
T39 1407 1357 0 0

TlMemAReadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 26711269 26657401 0 0
T1 148668 148280 0 0
T2 292090 291642 0 0
T3 282196 282145 0 0
T9 113615 113540 0 0
T23 297658 297650 0 0
T24 6520 6445 0 0
T36 185563 185491 0 0
T37 140156 139486 0 0
T38 186741 185546 0 0
T39 1407 1357 0 0

TlMemDValidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 26711269 26657401 0 0
T1 148668 148280 0 0
T2 292090 291642 0 0
T3 282196 282145 0 0
T9 113615 113540 0 0
T23 297658 297650 0 0
T24 6520 6445 0 0
T36 185563 185491 0 0
T37 140156 139486 0 0
T38 186741 185546 0 0
T39 1407 1357 0 0

TlRegsAReadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 26711269 26657401 0 0
T1 148668 148280 0 0
T2 292090 291642 0 0
T3 282196 282145 0 0
T9 113615 113540 0 0
T23 297658 297650 0 0
T24 6520 6445 0 0
T36 185563 185491 0 0
T37 140156 139486 0 0
T38 186741 185546 0 0
T39 1407 1357 0 0

TlRegsDValidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 26711269 26657401 0 0
T1 148668 148280 0 0
T2 292090 291642 0 0
T3 282196 282145 0 0
T9 113615 113540 0 0
T23 297658 297650 0 0
T24 6520 6445 0 0
T36 185563 185491 0 0
T37 140156 139486 0 0
T38 186741 185546 0 0
T39 1407 1357 0 0

TlSbaAValidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 26711269 26657401 0 0
T1 148668 148280 0 0
T2 292090 291642 0 0
T3 282196 282145 0 0
T9 113615 113540 0 0
T23 297658 297650 0 0
T24 6520 6445 0 0
T36 185563 185491 0 0
T37 140156 139486 0 0
T38 186741 185546 0 0
T39 1407 1357 0 0

TlSbaDReadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 26711269 26657401 0 0
T1 148668 148280 0 0
T2 292090 291642 0 0
T3 282196 282145 0 0
T9 113615 113540 0 0
T23 297658 297650 0 0
T24 6520 6445 0 0
T36 185563 185491 0 0
T37 140156 139486 0 0
T38 186741 185546 0 0
T39 1407 1357 0 0

paramCheckNrHarts
NameAttemptsReal SuccessesFailuresIncomplete
Total 165 165 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T9 1 1 0 0
T23 1 1 0 0
T24 1 1 0 0
T36 1 1 0 0
T37 1 1 0 0
T38 1 1 0 0
T39 1 1 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%