Module Definition
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Module : dmi_jtag
SCORELINECONDTOGGLEFSMBRANCHASSERT
84.72 95.45 92.45 66.67 84.31

Source File(s) :
/workspace/default/sim-vcs/../src/pulp-platform_riscv-dbg_0.1_0/pulp_riscv_dbg/src/dmi_jtag.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.dap 84.72 95.45 92.45 66.67 84.31



Module Instance : tb.dut.dap

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
84.72 95.45 92.45 66.67 84.31


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
86.20 98.68 92.76 70.00 94.57 75.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
88.73 100.00 75.86 91.55 87.50 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
i_dmi_cdc 88.09 100.00 87.27 98.41 66.67
i_dmi_jtag_tap 93.92 100.00 100.00 71.05 98.57 100.00


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : dmi_jtag
Line No.TotalCoveredPercent
TOTAL888495.45
CONT_ASSIGN6411100.00
ALWAYS7177100.00
ALWAYS9333100.00
CONT_ASSIGN12911100.00
CONT_ASSIGN13011100.00
CONT_ASSIGN13111100.00
CONT_ASSIGN13211100.00
ALWAYS140494591.84
CONT_ASSIGN25911100.00
ALWAYS2621212100.00
ALWAYS2861111100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/pulp-platform_riscv-dbg_0.1_0/pulp_riscv_dbg/src/dmi_jtag.sv' or '../src/pulp-platform_riscv-dbg_0.1_0/pulp_riscv_dbg/src/dmi_jtag.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
64 1 1
71 1 1
72 1 1
73 1 1
74 1 1
MISSING_ELSE
MISSING_ELSE
87 1 1
88 2 2
MISSING_ELSE
MISSING_ELSE
93 1 1
94 1 1
96 1 1
129 1 1
130 1 1
131 1 1
132 1 1
140 1 1
141 1 1
143 1 1
144 1 1
145 1 1
146 1 1
148 1 1
150 1 1
151 1 1
152 1 1
153 1 1
154 1 1
156 1 1
159 1 1
161 1 1
162 1 1
163 1 1
164 1 1
165 1 1
166 1 1
MISSING_ELSE
MISSING_ELSE
173 1 1
174 1 1
175 1 1
==> MISSING_ELSE
181 1 1
182 1 1
184 1 1
187 0 1
188 0 1
191 1 1
192 1 1
198 1 1
MISSING_ELSE
203 1 1
205 1 1
206 1 1
==> MISSING_ELSE
212 1 1
213 1 1
214 0 1
215 1 1
218 1 1
MISSING_ELSE
MISSING_ELSE
232 1 1
233 1 1
MISSING_ELSE
239 1 1
240 1 1
MISSING_ELSE
243 1 1
244 1 1
MISSING_ELSE
247 1 1
248 0 1
MISSING_ELSE
252 1 1
253 1 1
MISSING_ELSE
259 1 1
262 1 1
263 1 1
264 1 1
266 1 1
267 1 1
268 1 1
269 1 1
271 1 1
272 1 1
MISSING_ELSE
MISSING_ELSE
MISSING_ELSE
277 1 1
278 1 1
279 1 1
MISSING_ELSE
MISSING_ELSE
286 1 1
287 1 1
288 1 1
289 1 1
290 1 1
291 1 1
293 1 1
294 1 1
295 1 1
296 1 1
297 1 1


Cond Coverage for Module : dmi_jtag
TotalCoveredPercent
Conditions534992.45
Logical534992.45
Non-Logical00
Event00

 LINE       64
 EXPRESSION (jtag_dmi_clear || (dtmcs_select && update && dtmcs_q.dmihardreset))
             -------1------    ------------------------2-----------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT18,T6,T25
10CoveredT40,T19,T52

 LINE       64
 SUB-EXPRESSION (dtmcs_select && update && dtmcs_q.dmihardreset)
                 ------1-----    ---2--    ----------3---------
-1--2--3-StatusTests
011CoveredT18,T6,T25
101CoveredT1,T2,T3
110CoveredT1,T2,T3
111CoveredT18,T6,T25

 LINE       132
 EXPRESSION ((state_q == Write) ? DTM_WRITE : DTM_READ)
             ---------1--------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       132
 SUB-EXPRESSION (state_q == Write)
                ---------1--------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       159
 EXPRESSION (dmi_select && update && (error_q == DMINoError))
             -----1----    ---2--    -----------3-----------
-1--2--3-StatusTests
011CoveredT24,T10,T21
101CoveredT1,T2,T3
110CoveredT1,T2,T3
111CoveredT1,T2,T3

 LINE       159
 SUB-EXPRESSION (error_q == DMINoError)
                -----------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       163
 EXPRESSION (dtm_op_e'(dmi.op) == DTM_READ)
            ---------------1---------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       165
 EXPRESSION (dtm_op_e'(dmi.op) == DTM_WRITE)
            ----------------1---------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       232
 EXPRESSION (update && (state_q != Idle))
             ---1--    --------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT70

 LINE       232
 SUB-EXPRESSION (state_q != Idle)
                --------1--------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       239
 EXPRESSION (capture && (state_q inside {Read, WaitReadValid}))
             ---1---    -------------------2------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       243
 EXPRESSION (error_dmi_busy && (error_q == DMINoError))
             -------1------    -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       243
 SUB-EXPRESSION (error_q == DMINoError)
                -----------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       247
 EXPRESSION (error_dmi_op_failed && (error_q == DMINoError))
             ---------1---------    -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       247
 SUB-EXPRESSION (error_q == DMINoError)
                -----------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       252
 EXPRESSION (update && dtmcs_q.dmireset && dtmcs_select)
             ---1--    --------2-------    ------3-----
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT24,T10,T41
110CoveredT1,T2,T3
111CoveredT1,T2,T3

 LINE       268
 EXPRESSION ((error_q == DMINoError) && ((!error_dmi_busy)))
             -----------1-----------    ---------2---------
-1--2-StatusTests
01CoveredT7,T5,T12
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       268
 SUB-EXPRESSION (error_q == DMINoError)
                -----------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       271
 EXPRESSION ((error_q == DMIBusy) || error_dmi_busy)
             ----------1---------    -------2------
-1--2-StatusTests
00Not Covered
01CoveredT1,T2,T3
10CoveredT7,T5,T12

 LINE       271
 SUB-EXPRESSION (error_q == DMIBusy)
                ----------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT7,T5,T12

FSM Coverage for Module : dmi_jtag
Summary for FSM :: error_q
TotalCoveredPercent
States 3 2 66.67 (Not included in score)
Transitions 4 2 50.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: error_q
statesLine No.CoveredTests
DMIBusy 244 Covered T1,T2,T3
DMINoError 291 Covered T1,T2,T3
DMIOPFailed 248 Not Covered


transitionsLine No.CoveredTests
DMIBusy->DMINoError 291 Covered T1,T2,T3
DMINoError->DMIBusy 244 Covered T1,T2,T3
DMINoError->DMIOPFailed 248 Not Covered
DMIOPFailed->DMINoError 291 Not Covered


Summary for FSM :: state_q
TotalCoveredPercent
States 5 5 100.00 (Not included in score)
Transitions 8 6 75.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
Idle 288 Covered T1,T2,T3
Read 164 Covered T1,T2,T3
WaitReadValid 175 Covered T1,T2,T3
WaitWriteValid 206 Covered T1,T2,T3
Write 166 Covered T1,T2,T3


transitionsLine No.CoveredTests
Idle->Read 164 Covered T1,T2,T3
Idle->Write 166 Covered T1,T2,T3
Read->Idle 288 Not Covered
Read->WaitReadValid 175 Covered T1,T2,T3
WaitReadValid->Idle 288 Covered T1,T2,T3
WaitWriteValid->Idle 288 Covered T1,T2,T3
Write->Idle 288 Not Covered
Write->WaitWriteValid 206 Covered T1,T2,T3



Branch Coverage for Module : dmi_jtag
Line No.TotalCoveredPercent
Branches 51 43 84.31
TERNARY 132 2 2 100.00
IF 72 3 3 100.00
IF 87 3 3 100.00
IF 93 2 2 100.00
IF 150 30 22 73.33
IF 263 9 9 100.00
IF 286 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/pulp-platform_riscv-dbg_0.1_0/pulp_riscv_dbg/src/dmi_jtag.sv' or '../src/pulp-platform_riscv-dbg_0.1_0/pulp_riscv_dbg/src/dmi_jtag.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 132 ((state_q == Write)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 72 if (capture) -2-: 73 if (dtmcs_select)

Branches:
-1--2-StatusTests
1 1 Covered T1,T2,T3
1 0 Covered T1,T2,T3
0 - Covered T1,T2,T3


LineNo. Expression -1-: 87 if (shift) -2-: 88 if (dtmcs_select)

Branches:
-1--2-StatusTests
1 1 Covered T1,T2,T3
1 0 Covered T1,T2,T3
0 - Covered T1,T2,T3


LineNo. Expression -1-: 93 if ((!trst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 150 if (dmi_clear) -2-: 156 case (state_q) -3-: 159 if (((dmi_select && update) && (error_q == DMINoError))) -4-: 163 if ((dtm_op_e'(dmi.op) == DTM_READ)) -5-: 165 if ((dtm_op_e'(dmi.op) == DTM_WRITE)) -6-: 174 if (dmi_req_ready) -7-: 181 if (dmi_resp_valid) -8-: 182 case (dmi_resp.resp) -9-: 205 if (dmi_req_ready) -10-: 212 if (dmi_resp_valid) -11-: 213 case (dmi_resp.resp) -12-: 224 if (dmi_resp_valid) -13-: 232 if ((update && (state_q != Idle))) -14-: 239 if ((capture && (state_q inside {Read, WaitReadValid}))) -15-: 243 if ((error_dmi_busy && (error_q == DMINoError))) -16-: 247 if ((error_dmi_op_failed && (error_q == DMINoError))) -17-: 252 if (((update && dtmcs_q.dmireset) && dtmcs_select))

Branches:
-1--2--3--4--5--6--7--8--9--10--11--12--13--14--15--16--17-StatusTests
1 - - - - - - - - - - - - - - - - Covered T18,T6,T40
0 Idle 1 1 - - - - - - - - - - - - - Covered T1,T2,T3
0 Idle 1 0 1 - - - - - - - - - - - - Covered T1,T2,T3
0 Idle 1 0 0 - - - - - - - - - - - - Covered T1,T2,T3
0 Idle 0 - - - - - - - - - - - - - - Covered T1,T2,T3
0 Read - - - 1 - - - - - - - - - - - Covered T1,T2,T3
0 Read - - - 0 - - - - - - - - - - - Not Covered
0 WaitReadValid - - - - 1 DTM_SUCCESS - - - - - - - - - Covered T1,T2,T3
0 WaitReadValid - - - - 1 DTM_ERR - - - - - - - - - Not Covered
0 WaitReadValid - - - - 1 DTM_BUSY - - - - - - - - - Covered T5,T12,T13
0 WaitReadValid - - - - 1 default - - - - - - - - - Not Covered
0 WaitReadValid - - - - 0 - - - - - - - - - - Covered T1,T2,T3
0 Write - - - - - - 1 - - - - - - - - Covered T1,T2,T3
0 Write - - - - - - 0 - - - - - - - - Not Covered
0 WaitWriteValid - - - - - - - 1 DTM_ERR - - - - - - Not Covered
0 WaitWriteValid - - - - - - - 1 DTM_BUSY - - - - - - Covered T7,T5,T12
0 WaitWriteValid - - - - - - - 1 default - - - - - - Covered T1,T2,T3
0 WaitWriteValid - - - - - - - 0 - - - - - - - Covered T1,T2,T3
0 default - - - - - - - - - 1 - - - - - Not Covered
0 default - - - - - - - - - 0 - - - - - Not Covered
0 - - - - - - - - - - - 1 - - - - Covered T70
0 - - - - - - - - - - - 0 - - - - Covered T1,T2,T3
0 - - - - - - - - - - - - 1 - - - Covered T1,T2,T3
0 - - - - - - - - - - - - 0 - - - Covered T1,T2,T3
0 - - - - - - - - - - - - - 1 - - Covered T1,T2,T3
0 - - - - - - - - - - - - - 0 - - Covered T1,T2,T3
0 - - - - - - - - - - - - - - 1 - Not Covered
0 - - - - - - - - - - - - - - 0 - Covered T1,T2,T3
0 - - - - - - - - - - - - - - - 1 Covered T1,T2,T3
0 - - - - - - - - - - - - - - - 0 Covered T1,T2,T3


LineNo. Expression -1-: 263 if (dmi_clear) -2-: 266 if (capture) -3-: 267 if (dmi_select) -4-: 268 if (((error_q == DMINoError) && (!error_dmi_busy))) -5-: 271 if (((error_q == DMIBusy) || error_dmi_busy)) -6-: 277 if (shift) -7-: 278 if (dmi_select)

Branches:
-1--2--3--4--5--6--7-StatusTests
1 - - - - - - Covered T1,T2,T3
0 1 1 1 - - - Covered T1,T2,T3
0 1 1 0 1 - - Covered T1,T2,T3
0 1 1 0 0 - - Covered T1,T2,T3
0 1 0 - - - - Covered T1,T2,T3
0 0 - - - - - Covered T1,T2,T3
0 - - - - 1 1 Covered T1,T2,T3
0 - - - - 1 0 Covered T1,T2,T3
0 - - - - 0 - Covered T1,T2,T3


LineNo. Expression -1-: 286 if ((!trst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%