8d1fda3660| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | rv_dm_smoke | 2.060s | 465.203us | 2 | 2 | 100.00 |
| V1 | jtag_dtm_csr_hw_reset | rv_dm_jtag_dtm_csr_hw_reset | 0.730s | 53.801us | 5 | 5 | 100.00 |
| V1 | jtag_dtm_csr_rw | rv_dm_jtag_dtm_csr_rw | 0.850s | 68.878us | 20 | 20 | 100.00 |
| V1 | jtag_dtm_csr_bit_bash | rv_dm_jtag_dtm_csr_bit_bash | 5.450s | 2.450ms | 5 | 5 | 100.00 |
| V1 | jtag_dtm_csr_aliasing | rv_dm_jtag_dtm_csr_aliasing | 1.240s | 348.249us | 5 | 5 | 100.00 |
| V1 | jtag_dmi_csr_hw_reset | rv_dm_jtag_dmi_csr_hw_reset | 4.580s | 1.293ms | 5 | 5 | 100.00 |
| V1 | jtag_dmi_csr_rw | rv_dm_jtag_dmi_csr_rw | 5.860s | 1.732ms | 20 | 20 | 100.00 |
| V1 | jtag_dmi_csr_bit_bash | rv_dm_jtag_dmi_csr_bit_bash | 1.509m | 50.000ms | 3 | 5 | 60.00 |
| V1 | jtag_dmi_csr_aliasing | rv_dm_jtag_dmi_csr_aliasing | 23.540s | 4.911ms | 5 | 5 | 100.00 |
| V1 | jtag_dmi_cmderr_busy | rv_dm_cmderr_busy | 3.870s | 968.589us | 2 | 2 | 100.00 |
| V1 | jtag_dmi_cmderr_not_supported | rv_dm_cmderr_not_supported | 4.640s | 1.279ms | 2 | 2 | 100.00 |
| V1 | cmderr_exception | rv_dm_cmderr_exception | 0.770s | 41.058us | 1 | 2 | 50.00 |
| V1 | mem_tl_access_resuming | rv_dm_mem_tl_access_resuming | 1.510s | 497.490us | 2 | 2 | 100.00 |
| V1 | mem_tl_access_halted | rv_dm_mem_tl_access_halted | 0.720s | 79.959us | 2 | 2 | 100.00 |
| V1 | cmderr_halt_resume | rv_dm_cmderr_halt_resume | 0.870s | 161.437us | 2 | 2 | 100.00 |
| V1 | dataaddr_rw_access | rv_dm_dataaddr_rw_access | 0.760s | 48.645us | 2 | 2 | 100.00 |
| V1 | halt_resume | rv_dm_halt_resume_whereto | 1.790s | 450.945us | 2 | 2 | 100.00 |
| V1 | progbuf_busy | rv_dm_progbuf_busy | 1.070s | 555.188us | 2 | 2 | 100.00 |
| V1 | abstractcmd_status | rv_dm_abstractcmd_status | 0.680s | 19.853us | 0 | 2 | 0.00 |
| V1 | progbuf_read_write_execute | progbuf_read_write_execute | 0 | 0 | -- | ||
| V1 | progbuf_exception | progbuf_exception | 0 | 0 | -- | ||
| V1 | rom_read_access | rv_dm_rom_read_access | 0.740s | 57.278us | 2 | 2 | 100.00 |
| V1 | csr_hw_reset | rv_dm_csr_hw_reset | 2.420s | 123.328us | 5 | 5 | 100.00 |
| V1 | csr_rw | rv_dm_csr_rw | 2.410s | 102.886us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | rv_dm_csr_bit_bash | 1.131m | 10.758ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | rv_dm_csr_aliasing | 1.228m | 15.082ms | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | rv_dm_csr_mem_rw_with_rand_reset | 11.230s | 4.866ms | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rv_dm_csr_aliasing | 1.228m | 15.082ms | 5 | 5 | 100.00 |
| rv_dm_csr_rw | 2.410s | 102.886us | 20 | 20 | 100.00 | ||
| V1 | mem_walk | rv_dm_mem_walk | 0.660s | 31.036us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | rv_dm_mem_partial_access | 0.760s | 90.819us | 5 | 5 | 100.00 |
| V1 | TOTAL | 154 | 159 | 96.86 | |||
| V2 | idcode | rv_dm_smoke | 2.060s | 465.203us | 2 | 2 | 100.00 |
| V2 | jtag_dtm_hard_reset | rv_dm_jtag_dtm_hard_reset | 1.290s | 156.891us | 2 | 2 | 100.00 |
| V2 | jtag_dtm_idle_hint | rv_dm_jtag_dtm_idle_hint | 0.800s | 67.946us | 2 | 2 | 100.00 |
| V2 | jtag_dmi_failed_op | jtag_dmi_failed_op | 0 | 0 | -- | ||
| V2 | jtag_dmi_dm_inactive | rv_dm_jtag_dmi_dm_inactive | 0.780s | 185.610us | 2 | 2 | 100.00 |
| V2 | sba | rv_dm_sba_tl_access | 43.710s | 13.449ms | 19 | 20 | 95.00 |
| rv_dm_delayed_resp_sba_tl_access | 28.220s | 7.437ms | 18 | 20 | 90.00 | ||
| V2 | bad_sba | rv_dm_bad_sba_tl_access | 1.274m | 50.000ms | 17 | 20 | 85.00 |
| V2 | sba_autoincrement | rv_dm_autoincr_sba_tl_access | 2.631m | 50.000ms | 11 | 20 | 55.00 |
| V2 | jtag_dmi_debug_disabled | rv_dm_jtag_dmi_debug_disabled | 0.900s | 267.830us | 1 | 2 | 50.00 |
| V2 | sba_debug_disabled | sba_debug_disabled | 0 | 0 | -- | ||
| V2 | ndmreset_req | rv_dm_ndmreset_req | 4.180s | 1.184ms | 2 | 2 | 100.00 |
| V2 | hart_unavail | rv_dm_hart_unavail | 0.800s | 89.814us | 5 | 5 | 100.00 |
| V2 | tap_ctrl_transitions | rv_dm_tap_fsm | 4.340s | 1.359ms | 1 | 1 | 100.00 |
| rv_dm_tap_fsm_rand_reset | 43.080s | 13.822ms | 14 | 40 | 35.00 | ||
| V2 | stress_all | rv_dm_stress_all | 13.140s | 4.149ms | 9 | 50 | 18.00 |
| V2 | alert_test | rv_dm_alert_test | 0.730s | 29.478us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | rv_dm_tl_errors | 5.880s | 4.839ms | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | rv_dm_tl_errors | 5.880s | 4.839ms | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | rv_dm_csr_aliasing | 1.228m | 15.082ms | 5 | 5 | 100.00 |
| rv_dm_csr_hw_reset | 2.420s | 123.328us | 5 | 5 | 100.00 | ||
| rv_dm_csr_rw | 2.410s | 102.886us | 20 | 20 | 100.00 | ||
| rv_dm_same_csr_outstanding | 7.980s | 1.212ms | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | rv_dm_csr_aliasing | 1.228m | 15.082ms | 5 | 5 | 100.00 |
| rv_dm_csr_hw_reset | 2.420s | 123.328us | 5 | 5 | 100.00 | ||
| rv_dm_csr_rw | 2.410s | 102.886us | 20 | 20 | 100.00 | ||
| rv_dm_same_csr_outstanding | 7.980s | 1.212ms | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 193 | 276 | 69.93 | |||
| V2S | tl_intg_err | rv_dm_sec_cm | 1.330s | 158.231us | 5 | 5 | 100.00 |
| rv_dm_tl_intg_err | 20.280s | 4.236ms | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | sec_cm_bus_integrity | 0 | 0 | -- | ||
| V2S | sec_cm_lc_hw_debug_en_intersig_mubi | sec_cm_lc_hw_debug_en_intersig_mubi | 0 | 0 | -- | ||
| V2S | sec_cm_dm_en_ctrl_lc_gated | sec_cm_dm_en_ctrl_lc_gated | 0 | 0 | -- | ||
| V2S | sec_cm_sba_tl_lc_gate_fsm_sparse | sec_cm_sba_tl_lc_gate_fsm_sparse | 0 | 0 | -- | ||
| V2S | sec_cm_mem_tl_lc_gate_fsm_sparse | sec_cm_mem_tl_lc_gate_fsm_sparse | 0 | 0 | -- | ||
| V2S | sec_cm_exec_ctrl_mubi | sec_cm_exec_ctrl_mubi | 0 | 0 | -- | ||
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | rv_dm_stress_all_with_rand_reset | 1.961m | 9.085ms | 0 | 50 | 0.00 |
| V3 | TOTAL | 0 | 50 | 0.00 | |||
| TOTAL | 372 | 510 | 72.94 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 29 | 27 | 24 | 82.76 |
| V2 | 18 | 16 | 9 | 50.00 |
| V2S | 8 | 2 | 2 | 25.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 87.77 | 92.87 | 79.06 | 89.36 | 76.92 | 83.07 | 97.75 | 95.34 |
UVM_ERROR (jtag_dmi_monitor.sv:105) m_jtag_dmi_monitor [m_jtag_dmi_monitor] Non-ok response seen with no previous DMI request. has 53 failures:
Test rv_dm_cmderr_exception has 1 failures.
0.rv_dm_cmderr_exception.5869743875164794028161800681812270752396898197705262710169006005068405430784
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_cmderr_exception/latest/run.log
UVM_ERROR @ 457512647 ps: (jtag_dmi_monitor.sv:105) uvm_test_top.env.m_jtag_dmi_monitor [uvm_test_top.env.m_jtag_dmi_monitor] Non-ok response seen with no previous DMI request.
UVM_INFO @ 457512647 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_dm_jtag_dmi_debug_disabled has 1 failures.
0.rv_dm_jtag_dmi_debug_disabled.61537173389296693317397728030916246271175075561857847532866302108089383748475
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_jtag_dmi_debug_disabled/latest/run.log
UVM_ERROR @ 94690823 ps: (jtag_dmi_monitor.sv:105) uvm_test_top.env.m_jtag_dmi_monitor [uvm_test_top.env.m_jtag_dmi_monitor] Non-ok response seen with no previous DMI request.
UVM_INFO @ 94690823 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_dm_stress_all_with_rand_reset has 27 failures.
1.rv_dm_stress_all_with_rand_reset.15397889110183090430697667767077251187237345908566580966321493592360188617303
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 17637756 ps: (jtag_dmi_monitor.sv:105) uvm_test_top.env.m_jtag_dmi_monitor [uvm_test_top.env.m_jtag_dmi_monitor] Non-ok response seen with no previous DMI request.
UVM_INFO @ 17637756 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.rv_dm_stress_all_with_rand_reset.45436325966064598648181640860096572707389120714638762915042825310039076092175
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/2.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 21424956 ps: (jtag_dmi_monitor.sv:105) uvm_test_top.env.m_jtag_dmi_monitor [uvm_test_top.env.m_jtag_dmi_monitor] Non-ok response seen with no previous DMI request.
UVM_INFO @ 21424956 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 25 more failures.
Test rv_dm_stress_all has 24 failures.
6.rv_dm_stress_all.70841216935701003934801788525130393242620990369018826285660029876321233885339
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/6.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 14263039 ps: (jtag_dmi_monitor.sv:105) uvm_test_top.env.m_jtag_dmi_monitor [uvm_test_top.env.m_jtag_dmi_monitor] Non-ok response seen with no previous DMI request.
UVM_INFO @ 14263039 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
7.rv_dm_stress_all.23855737093255089985250218754859538415022021265719348078234889972691758606687
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/7.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 7515968 ps: (jtag_dmi_monitor.sv:105) uvm_test_top.env.m_jtag_dmi_monitor [uvm_test_top.env.m_jtag_dmi_monitor] Non-ok response seen with no previous DMI request.
UVM_INFO @ 7515968 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 22 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 14 failures:
Test rv_dm_jtag_dmi_csr_bit_bash has 2 failures.
0.rv_dm_jtag_dmi_csr_bit_bash.78908867896526585554141139973358330145544636522575266024415390927160408449789
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_jtag_dmi_csr_bit_bash/latest/run.log
UVM_FATAL @ 50000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 50000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 50000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.rv_dm_jtag_dmi_csr_bit_bash.50411922213191324426861314913261567815619423309452113209846206969839955522637
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/2.rv_dm_jtag_dmi_csr_bit_bash/latest/run.log
UVM_FATAL @ 50000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 50000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 50000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_dm_autoincr_sba_tl_access has 9 failures.
1.rv_dm_autoincr_sba_tl_access.85050593170100735184599800938750955118698118248696261806081507292036898736297
Line 431, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_autoincr_sba_tl_access/latest/run.log
UVM_FATAL @ 50000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 50000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 50000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
7.rv_dm_autoincr_sba_tl_access.85931013011392333197441303976470937287217939701328597055939569573108430993500
Line 410, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/7.rv_dm_autoincr_sba_tl_access/latest/run.log
UVM_FATAL @ 50000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 50000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 50000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 7 more failures.
Test rv_dm_bad_sba_tl_access has 3 failures.
4.rv_dm_bad_sba_tl_access.39938808864030093008411275795712887322793102816210510347039804023244440030626
Line 314, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/4.rv_dm_bad_sba_tl_access/latest/run.log
UVM_FATAL @ 50000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 50000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 50000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
18.rv_dm_bad_sba_tl_access.65438658094842246288629244241023879838697545013727411959084765533730218994398
Line 317, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/18.rv_dm_bad_sba_tl_access/latest/run.log
UVM_FATAL @ 50000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 50000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 50000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR (rv_dm_smoke_vseq.sv:32) [seq] Check failed cfg.rv_dm_vif.cb.debug_req == data (* [*] vs * [*]) has 10 failures:
2.rv_dm_tap_fsm_rand_reset.74592929140414988506865464877342070930102069947341156402547176633966693700995
Line 288, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/2.rv_dm_tap_fsm_rand_reset/latest/run.log
UVM_ERROR @ 1935096617 ps: (rv_dm_smoke_vseq.sv:32) [uvm_test_top.env.virtual_sequencer.rv_dm_tap_fsm_vseq.seq] Check failed cfg.rv_dm_vif.cb.debug_req == data (0 [0x0] vs 1 [0x1])
UVM_INFO @ 1935096617 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.rv_dm_tap_fsm_rand_reset.105581690943762461622785166840787059042426755754776900281848808833156738613229
Line 343, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/3.rv_dm_tap_fsm_rand_reset/latest/run.log
UVM_ERROR @ 20470434605 ps: (rv_dm_smoke_vseq.sv:32) [uvm_test_top.env.virtual_sequencer.rv_dm_tap_fsm_vseq.seq] Check failed cfg.rv_dm_vif.cb.debug_req == data (0 [0x0] vs 1 [0x1])
UVM_INFO @ 20470434605 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 8 more failures.
UVM_ERROR (rv_dm_smoke_vseq.sv:40) [seq] Check failed cfg.rv_dm_vif.cb.ndmreset_req == data (* [*] vs * [*]) has 9 failures:
0.rv_dm_tap_fsm_rand_reset.102573118315058298164069718136505974140614750678796894061261490374077576003914
Line 256, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_tap_fsm_rand_reset/latest/run.log
UVM_ERROR @ 111356814 ps: (rv_dm_smoke_vseq.sv:40) [uvm_test_top.env.virtual_sequencer.rv_dm_tap_fsm_vseq.seq] Check failed cfg.rv_dm_vif.cb.ndmreset_req == data (0 [0x0] vs 1 [0x1])
UVM_INFO @ 111356814 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rv_dm_tap_fsm_rand_reset.108649966156291325082163361637274219114604733171206104587004793360873775066029
Line 281, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_tap_fsm_rand_reset/latest/run.log
UVM_ERROR @ 12077520207 ps: (rv_dm_smoke_vseq.sv:40) [uvm_test_top.env.virtual_sequencer.rv_dm_tap_fsm_vseq.seq] Check failed cfg.rv_dm_vif.cb.ndmreset_req == data (0 [0x0] vs 1 [0x1])
UVM_INFO @ 12077520207 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 7 more failures.
UVM_ERROR (rv_dm_scoreboard.sv:98) [scoreboard] Check failed item.dout & mask == selected_dtm_csr.get_mirrored_value() & mask (* [*] vs * [*]) has 9 failures:
0.rv_dm_stress_all.34561549702838835431873702265344851879187687994769979321910888916457025269144
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 5515830 ps: (rv_dm_scoreboard.sv:98) [uvm_test_top.env.scoreboard] Check failed item.dout & mask == selected_dtm_csr.get_mirrored_value() & mask (4294964222 [0xfffff3fe] vs 4209 [0x1071])
UVM_INFO @ 5515830 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
12.rv_dm_stress_all.112561265921085995572357278528614478051465950693428270415032780890382717093666
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/12.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 105610440 ps: (rv_dm_scoreboard.sv:98) [uvm_test_top.env.scoreboard] Check failed item.dout & mask == selected_dtm_csr.get_mirrored_value() & mask (17 [0x11] vs 4209 [0x1071])
UVM_INFO @ 105610440 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
12.rv_dm_stress_all_with_rand_reset.97934344845781819325524012963334410714902965351946406185017969974242016679797
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/12.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 27923874 ps: (rv_dm_scoreboard.sv:98) [uvm_test_top.env.scoreboard] Check failed item.dout & mask == selected_dtm_csr.get_mirrored_value() & mask (17 [0x11] vs 4209 [0x1071])
UVM_INFO @ 27923874 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
14.rv_dm_stress_all_with_rand_reset.2028364167956400838599587126960192772837686435914076682668971467981745965124
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/14.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 29756565 ps: (rv_dm_scoreboard.sv:98) [uvm_test_top.env.scoreboard] Check failed item.dout & mask == selected_dtm_csr.get_mirrored_value() & mask (17 [0x11] vs 4209 [0x1071])
UVM_INFO @ 29756565 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_ERROR (csr_utils_pkg.sv:247) [csr_utils] Check failed status == UVM_IS_OK (* [*] vs * [*]) trying to write csr jtag_dmi_ral.dmcontrol has 7 failures:
3.rv_dm_stress_all.29806655111076422702478622797443165597808821902609213437944810836158303275004
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/3.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 14072555 ps: (csr_utils_pkg.sv:247) [csr_utils] Check failed status == UVM_IS_OK (1 [0x1] vs 0 [0x0]) trying to write csr jtag_dmi_ral.dmcontrol
UVM_INFO @ 14072555 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
30.rv_dm_stress_all.53612689191370190101771058836389452224178970925985647229025950316668315445017
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/30.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 7464177 ps: (csr_utils_pkg.sv:247) [csr_utils] Check failed status == UVM_IS_OK (1 [0x1] vs 0 [0x0]) trying to write csr jtag_dmi_ral.dmcontrol
UVM_INFO @ 7464177 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
3.rv_dm_stress_all_with_rand_reset.88507313716022924816190345723044513635662475679937393012980268769241746789780
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/3.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 25302734 ps: (csr_utils_pkg.sv:247) [csr_utils] Check failed status == UVM_IS_OK (1 [0x1] vs 0 [0x0]) trying to write csr jtag_dmi_ral.dmcontrol
UVM_INFO @ 25302734 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
9.rv_dm_stress_all_with_rand_reset.65697459728015060002315448939182951563286152040755855602361363613912951824251
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/9.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 9408882 ps: (csr_utils_pkg.sv:247) [csr_utils] Check failed status == UVM_IS_OK (1 [0x1] vs 0 [0x0]) trying to write csr jtag_dmi_ral.dmcontrol
UVM_INFO @ 9408882 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR (rv_dm_base_vseq.sv:167) [rv_dm_cmderr_busy_vseq] Check failed cmderr == get_field_val(jtag_dmi_ral.abstractcs.cmderr,rdata) (* [*] vs * [*]) has 4 failures:
0.rv_dm_stress_all_with_rand_reset.33243727310260463678366258613346939700507193187953009128337532375930834889412
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 210546086 ps: (rv_dm_base_vseq.sv:167) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_busy_vseq] Check failed cmderr == get_field_val(jtag_dmi_ral.abstractcs.cmderr,rdata) (1 [0x1] vs 3 [0x3])
UVM_INFO @ 210546086 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
22.rv_dm_stress_all_with_rand_reset.84416925974326852022707204208980918654241173954356573165100939980702927339157
Line 256, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/22.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 688945384 ps: (rv_dm_base_vseq.sv:167) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_busy_vseq] Check failed cmderr == get_field_val(jtag_dmi_ral.abstractcs.cmderr,rdata) (1 [0x1] vs 3 [0x3])
UVM_INFO @ 688945384 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_ERROR (jtag_dmi_monitor.sv:48) m_jtag_dmi_monitor [m_jtag_dmi_monitor] Bad packet: item: (jtag_item@5095) { ir_len: * dr_len: * ir: * dr: 'hxxxxxxxxxxxxxxxx dout: 'hxxxxxxxxxxxxxxxx bus_op: BusOpWrite skip_reselected_ir: * ir_pause_count: * dr_pause_count: * } has 3 failures:
Test rv_dm_sba_tl_access has 1 failures.
2.rv_dm_sba_tl_access.20968353593623438531761687499795216448107497929695476167708906834527238990260
Line 258, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/2.rv_dm_sba_tl_access/latest/run.log
UVM_ERROR @ 2024093 ps: (jtag_dmi_monitor.sv:48) uvm_test_top.env.m_jtag_dmi_monitor [uvm_test_top.env.m_jtag_dmi_monitor] Bad packet: item: (jtag_item@5095) { ir_len: 'h0 dr_len: 'h0 ir: 'h0 dr: 'hxxxxxxxxxxxxxxxx dout: 'hxxxxxxxxxxxxxxxx bus_op: BusOpWrite skip_reselected_ir: 'h0 ir_pause_count: 'h0 dr_pause_count: 'h0 }
. ir_len & dr_len are both zero, or non-zero.
UVM_INFO @ 2024093 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_dm_delayed_resp_sba_tl_access has 1 failures.
3.rv_dm_delayed_resp_sba_tl_access.72932081547822329838132007571694933415287329733257028707488046371928823341230
Line 258, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/3.rv_dm_delayed_resp_sba_tl_access/latest/run.log
UVM_ERROR @ 2615598 ps: (jtag_dmi_monitor.sv:48) uvm_test_top.env.m_jtag_dmi_monitor [uvm_test_top.env.m_jtag_dmi_monitor] Bad packet: item: (jtag_item@5095) { ir_len: 'h0 dr_len: 'h0 ir: 'h0 dr: 'hxxxxxxxxxxxxxxxx dout: 'hxxxxxxxxxxxxxxxx bus_op: BusOpWrite skip_reselected_ir: 'h0 ir_pause_count: 'h0 dr_pause_count: 'h0 }
. ir_len & dr_len are both zero, or non-zero.
UVM_INFO @ 2615598 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_dm_stress_all has 1 failures.
26.rv_dm_stress_all.64905417272126127471597153862033715883059430701746064520861626388235938160767
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/26.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 4313802 ps: (jtag_dmi_monitor.sv:48) uvm_test_top.env.m_jtag_dmi_monitor [uvm_test_top.env.m_jtag_dmi_monitor] Bad packet: item: (jtag_item@5095) { ir_len: 'h0 dr_len: 'h0 ir: 'h0 dr: 'hxxxxxxxxxxxxxxxx dout: 'hxxxxxxxxxxxxxxxx bus_op: BusOpWrite skip_reselected_ir: 'h0 ir_pause_count: 'h0 dr_pause_count: 'h0 }
. ir_len & dr_len are both zero, or non-zero.
UVM_INFO @ 4313802 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_base_vseq.sv:191) [rv_dm_mem_tl_access_halted_vseq] Check failed cfg.rv_dm_vif.cb.debug_req == * (* [*] vs * [*]) has 3 failures:
Test rv_dm_stress_all has 2 failures.
2.rv_dm_stress_all.68638767488435623638130566482237363055940243137681153170853975218000527000748
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/2.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 1164933129 ps: (rv_dm_base_vseq.sv:191) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_halted_vseq] Check failed cfg.rv_dm_vif.cb.debug_req == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 1164933129 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
14.rv_dm_stress_all.36394816306785602430068010100816637010252325255403115682161131964721731326681
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/14.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 656652747 ps: (rv_dm_base_vseq.sv:191) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_halted_vseq] Check failed cfg.rv_dm_vif.cb.debug_req == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 656652747 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_dm_stress_all_with_rand_reset has 1 failures.
15.rv_dm_stress_all_with_rand_reset.84937046620757372813654626882382086146296673928154722411789407835465680265459
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/15.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 9104586 ps: (rv_dm_base_vseq.sv:191) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_halted_vseq] Check failed cfg.rv_dm_vif.cb.debug_req == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 9104586 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_smoke_vseq.sv:59) [seq] Check failed cfg.rv_dm_vif.cb.dmactive == data (* [*] vs * [*]) has 3 failures:
15.rv_dm_tap_fsm_rand_reset.106138762020916762062065569372986034030349698172309732576641667526069056003273
Line 384, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/15.rv_dm_tap_fsm_rand_reset/latest/run.log
UVM_ERROR @ 48148500889 ps: (rv_dm_smoke_vseq.sv:59) [uvm_test_top.env.virtual_sequencer.rv_dm_tap_fsm_vseq.seq] Check failed cfg.rv_dm_vif.cb.dmactive == data (0 [0x0] vs 1 [0x1])
UVM_INFO @ 48148500889 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
20.rv_dm_tap_fsm_rand_reset.10455969991851604416364774935789505177242045359855495322537237145541182626105
Line 265, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/20.rv_dm_tap_fsm_rand_reset/latest/run.log
UVM_ERROR @ 1261000722 ps: (rv_dm_smoke_vseq.sv:59) [uvm_test_top.env.virtual_sequencer.rv_dm_tap_fsm_vseq.seq] Check failed cfg.rv_dm_vif.cb.dmactive == data (0 [0x0] vs 1 [0x1])
UVM_INFO @ 1261000722 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Exit reason: Error: User command failed Error-[NOA] Null object access has 2 failures:
0.rv_dm_abstractcmd_status.64510696089750584583920169587529318081605386143392561052647410645568253059498
Line 252, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_abstractcmd_status/latest/run.log
Error-[NOA] Null object access
../src/lowrisc_dv_dv_base_reg_0/dv_base_reg_pkg.sv, 73
The object at dereference depth 0 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
1.rv_dm_abstractcmd_status.62990670039548569908745797421454133312192125389704572580019984449338066037903
Line 252, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_abstractcmd_status/latest/run.log
Error-[NOA] Null object access
../src/lowrisc_dv_dv_base_reg_0/dv_base_reg_pkg.sv, 73
The object at dereference depth 0 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
UVM_FATAL (csr_utils_pkg.sv:378) [csr_utils::csr_rd] Timeout waiting to csr_rd jtag_dtm_ral.idcode (addr=*) has 2 failures:
8.rv_dm_tap_fsm_rand_reset.44351799311419006081739432017202575482645424211336527677324375455734872595718
Line 387, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/8.rv_dm_tap_fsm_rand_reset/latest/run.log
UVM_FATAL @ 13768482405 ps: (csr_utils_pkg.sv:378) [csr_utils::csr_rd] Timeout waiting to csr_rd jtag_dtm_ral.idcode (addr=0x1)
UVM_INFO @ 13768482405 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
9.rv_dm_tap_fsm_rand_reset.90772055641447757861085237867446631568449194238373741035548932195154289974892
Line 286, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/9.rv_dm_tap_fsm_rand_reset/latest/run.log
UVM_FATAL @ 4155725014 ps: (csr_utils_pkg.sv:378) [csr_utils::csr_rd] Timeout waiting to csr_rd jtag_dtm_ral.idcode (addr=0x1)
UVM_INFO @ 4155725014 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_scoreboard.sv:74) [scoreboard] Check failed item.dout == * (* [*] vs * [*]) has 2 failures:
8.rv_dm_stress_all.61572715468642414019083571621561335503512474541527656422077334943303993732797
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/8.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 394678362 ps: (rv_dm_scoreboard.sv:74) [uvm_test_top.env.scoreboard] Check failed item.dout == 0 (268435454 [0xffffffe] vs 0 [0x0])
UVM_INFO @ 394678362 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
9.rv_dm_stress_all.81663994742370751910858867267958456096995575295250062647956480369522899534925
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/9.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 1466630584 ps: (rv_dm_scoreboard.sv:74) [uvm_test_top.env.scoreboard] Check failed item.dout == 0 (1125896922732 [0x10624afa66c] vs 0 [0x0])
UVM_INFO @ 1466630584 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_ndmreset_req_vseq.sv:54) [rv_dm_ndmreset_req_vseq] Check failed rdata == * (* [*] vs * [*]) has 2 failures:
8.rv_dm_stress_all_with_rand_reset.5757026339961526784175638605957204478847731108121256215457115446637620401740
Line 255, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/8.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 99819185 ps: (rv_dm_ndmreset_req_vseq.sv:54) [uvm_test_top.env.virtual_sequencer.rv_dm_ndmreset_req_vseq] Check failed rdata == 'h58710590 (0 [0x0] vs 1483802000 [0x58710590])
UVM_INFO @ 99819185 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
37.rv_dm_stress_all_with_rand_reset.97991058047442782820233844296083947417250914144788708688335207108610078440854
Line 257, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/37.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1492679275 ps: (rv_dm_ndmreset_req_vseq.sv:54) [uvm_test_top.env.virtual_sequencer.rv_dm_ndmreset_req_vseq] Check failed rdata == 'h58710590 (2958143569 [0xb051b051] vs 1483802000 [0x58710590])
UVM_INFO @ 1492679275 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_jtag_dmi_debug_disabled_vseq.sv:25) [rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (* [*] vs * [*]) has 2 failures:
10.rv_dm_stress_all_with_rand_reset.99627252605853601339422344319880531078017581953722549260013031560051731292486
Line 257, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/10.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1525368225 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:25) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (0 [0x0] vs 378098014 [0x1689515e])
UVM_INFO @ 1525368225 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
44.rv_dm_stress_all_with_rand_reset.91141153855938264504004400613217556792896359875027481138151540596305931636620
Line 262, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/44.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 5733178808 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:25) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (2958143569 [0xb051b051] vs 1844450846 [0x6df0161e])
UVM_INFO @ 5733178808 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_base_vseq.sv:167) [rv_dm_cmderr_not_supported_vseq] Check failed cmderr == get_field_val(jtag_dmi_ral.abstractcs.cmderr,rdata) (* [*] vs * [*]) has 2 failures:
19.rv_dm_stress_all_with_rand_reset.79136256638302406896856336685219289324536832664277987415478893240514763810414
Line 256, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/19.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 242760448 ps: (rv_dm_base_vseq.sv:167) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_not_supported_vseq] Check failed cmderr == get_field_val(jtag_dmi_ral.abstractcs.cmderr,rdata) (2 [0x2] vs 3 [0x3])
UVM_INFO @ 242760448 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
33.rv_dm_stress_all_with_rand_reset.82522159832736206602665280086937007221401809739374419159233307641169174514780
Line 254, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/33.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 223983054 ps: (rv_dm_base_vseq.sv:167) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_not_supported_vseq] Check failed cmderr == get_field_val(jtag_dmi_ral.abstractcs.cmderr,rdata) (2 [0x2] vs 3 [0x3])
UVM_INFO @ 223983054 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_jtag_dtm_hard_reset_vseq.sv:27) [rv_dm_jtag_dtm_hard_reset_vseq] Check failed wdata == rdata* (* [*] vs * [*]) has 1 failures:
5.rv_dm_stress_all.62093337869180083403260749995017172206999103943008459092422540448400527116839
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/5.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 2878916218 ps: (rv_dm_jtag_dtm_hard_reset_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dtm_hard_reset_vseq] Check failed wdata == rdata1 (20 [0x14] vs 2958143569 [0xb051b051])
UVM_INFO @ 2878916218 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 1 failures:
10.rv_dm_tap_fsm_rand_reset.108555861247925145408465565285201925637863185885178641430237043071197383768244
Line 331, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/10.rv_dm_tap_fsm_rand_reset/latest/run.log
UVM_ERROR @ 17663670280 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_jtag_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_jtag_agent.sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
UVM_INFO @ 17663670280 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_sba_tl_access_vseq_lib.sv:120) [rv_dm_delayed_resp_sba_tl_access_vseq] Check failed (!req.timed_out) has 1 failures:
16.rv_dm_delayed_resp_sba_tl_access.107118919563597259439961212719666450122421222825157096275986312654546540519560
Line 262, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/16.rv_dm_delayed_resp_sba_tl_access/latest/run.log
UVM_ERROR @ 1296314981 ps: (rv_dm_sba_tl_access_vseq_lib.sv:120) [uvm_test_top.env.virtual_sequencer.rv_dm_delayed_resp_sba_tl_access_vseq] Check failed (!req.timed_out)
UVM_INFO @ 1296314981 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_mem_tl_access_resuming_vseq.sv:41) [rv_dm_mem_tl_access_resuming_vseq] Check failed * == get_field_val(jtag_dmi_ral.dmstatus.anyrunning, rdata) (* [*] vs * [*]) has 1 failures:
20.rv_dm_stress_all_with_rand_reset.78922489932458361184215763049954782750988570688460676774147621463417462897176
Line 256, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/20.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1585315479 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:41) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed 1 == get_field_val(jtag_dmi_ral.dmstatus.anyrunning, rdata) (1 [0x1] vs 0 [0x0])
UVM_INFO @ 1585315479 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_smoke_vseq.sv:32) [rv_dm_smoke_vseq] Check failed cfg.rv_dm_vif.cb.debug_req == data (* [*] vs * [*]) has 1 failures:
21.rv_dm_stress_all_with_rand_reset.65938188878249069054593285753918915435318293795200860852816543437993948499954
Line 255, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/21.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 120779754 ps: (rv_dm_smoke_vseq.sv:32) [uvm_test_top.env.virtual_sequencer.rv_dm_smoke_vseq] Check failed cfg.rv_dm_vif.cb.debug_req == data (0 [0x0] vs 1 [0x1])
UVM_INFO @ 120779754 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_smoke_vseq.sv:48) [seq] Check failed cfg.rv_dm_vif.unavailable == get_field_val(jtag_dmi_ral.dmstatus.anyunavail, data) (* [*] vs * [*]) has 1 failures:
23.rv_dm_tap_fsm_rand_reset.13158492604202073577121305447825569008908076193282540740311852833636174182158
Line 320, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/23.rv_dm_tap_fsm_rand_reset/latest/run.log
UVM_ERROR @ 5811709009 ps: (rv_dm_smoke_vseq.sv:48) [uvm_test_top.env.virtual_sequencer.rv_dm_tap_fsm_vseq.seq] Check failed cfg.rv_dm_vif.unavailable == get_field_val(jtag_dmi_ral.dmstatus.anyunavail, data) (1 [0x1] vs 0 [0x0])
UVM_INFO @ 5811709009 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_halt_resume_whereto_vseq.sv:27) [rv_dm_halt_resume_whereto_vseq] Check failed * == get_field_val(jtag_dmi_ral.abstractcs.busy,rdata) (* [*] vs * [*]) has 1 failures:
24.rv_dm_stress_all_with_rand_reset.44774632036567546905186308156316439322699447175946004020953821979490740120048
Line 255, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/24.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 41354720 ps: (rv_dm_halt_resume_whereto_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.rv_dm_halt_resume_whereto_vseq] Check failed 1 == get_field_val(jtag_dmi_ral.abstractcs.busy,rdata) (1 [0x1] vs 0 [0x0])
UVM_INFO @ 41354720 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_halt_resume_whereto_vseq.sv:44) [rv_dm_halt_resume_whereto_vseq] Check failed * == tl_mem_ral.flags[*].get_mirrored_value() (* [*] vs * [*]) has 1 failures:
28.rv_dm_stress_all_with_rand_reset.75967269201387578024579594338739234624473985501688137699655515441218311122158
Line 255, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/28.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 199106801 ps: (rv_dm_halt_resume_whereto_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.rv_dm_halt_resume_whereto_vseq] Check failed 2 == tl_mem_ral.flags[0].get_mirrored_value() (2 [0x2] vs 0 [0x0])
UVM_INFO @ 199106801 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:371) [csr_utils::csr_rd] Check failed status == UVM_IS_OK (* [*] vs * [*]) trying to read csr/field jtag_dmi_ral.abstractdata_* has 1 failures:
31.rv_dm_stress_all.35674839014967420893855665271114032578378990468710836234223279681146931192968
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/31.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 1263616569 ps: (csr_utils_pkg.sv:371) [csr_utils::csr_rd] Check failed status == UVM_IS_OK (1 [0x1] vs 0 [0x0]) trying to read csr/field jtag_dmi_ral.abstractdata_0
UVM_INFO @ 1263616569 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_jtag_dmi_dm_inactive_vseq.sv:33) [rv_dm_jtag_dmi_dm_inactive_vseq] Check failed rdata == jtag_dmi_ral.abstractdata[*].get_reset() (* [*] vs * [*]) has 1 failures:
35.rv_dm_stress_all.1096602673094465344126096553989318943904444171641446525556671104736660790376
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/35.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 3073456657 ps: (rv_dm_jtag_dmi_dm_inactive_vseq.sv:33) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_dm_inactive_vseq] Check failed rdata == jtag_dmi_ral.abstractdata[0].get_reset() (2958143569 [0xb051b051] vs 0 [0x0])
UVM_INFO @ 3073456657 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_scoreboard.sv:363) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: rv_dm_mem_reg_block.dataaddr_* has 1 failures:
35.rv_dm_stress_all_with_rand_reset.24697882041885273904972484522440568977089699270597663067475526456970492704171
Line 254, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/35.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 436715293 ps: (rv_dm_scoreboard.sv:363) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1484011778 [0x58743902] vs 1489370626 [0x58c5fe02]) reg name: rv_dm_mem_reg_block.dataaddr_0
UVM_INFO @ 436715293 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---