Unified Coverage Report :: Module :: rv_dm_regs_csr_assert_fpv

Module : rv_dm_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_dm_csr_assert_0/rv_dm_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_dm_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_dm_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
77.03	90.91	61.70	87.88		57.14	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_dm_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	41594776	11087	0	0
late_debug_enable_rd_A	41594776	3253	0	0
late_debug_enable_regwen_rd_A	41594776	2778	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	41594776	11087	0	0
T32	101976	228	0	0
T33	51717	7	0	0
T34	7884	13	0	0
T35	8601	704	0	0
T36	11759	47	0	0
T66	114206	6	0	0
T73	11748	46	0	0
T74	50864	3	0	0
T75	39947	21	0	0
T76	6292	22	0	0

late_debug_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	41594776	3253	0	0
T36	11759	67	0	0
T75	39947	17	0	0
T76	6292	15	0	0
T77	135191	13	0	0
T82	54521	85	0	0
T83	38096	25	0	0
T85	20367	11	0	0
T86	8193	10	0	0
T92	14773	181	0	0
T121	201567	31	0	0

late_debug_enable_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	41594776	2778	0	0
T36	11759	34	0	0
T75	39947	23	0	0
T76	6292	15	0	0
T77	135191	21	0	0
T82	54521	9	0	0
T83	38096	39	0	0
T85	20367	18	0	0
T86	8193	8	0	0
T92	14773	158	0	0
T122	6939	40	0	0