Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : rv_dm
SCORELINECONDTOGGLEFSMBRANCHASSERT
77.03 90.91 61.70 87.88 57.14 87.50

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_rv_dm_0.1/rtl/rv_dm.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut 77.03 90.91 61.70 87.88 57.14 87.50



Module Instance : tb.dut

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
77.03 90.91 61.70 87.88 57.14 87.50


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
86.89 94.44 80.19 87.69 76.92 83.66 98.42


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
tb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
dap 85.90 98.36 92.11 70.00 94.02 75.00
gen_alert_tx[0].u_prim_alert_sender 83.33 83.33
i_tlul_adapter_reg 93.27 99.00 80.90 93.33 93.10 100.00
rv_dm_regs_csr_assert 100.00 100.00
tl_adapter_host_sba 95.14 100.00 100.00 75.71 100.00 100.00
tlul_assert_device_mem 95.24 100.00 85.71 100.00
tlul_assert_device_regs 95.12 100.00 85.71 99.65
tlul_assert_host_sba 94.30 100.00 85.71 97.18
u_dm_top 85.03 86.63 66.32 100.00 72.20 100.00
u_lc_en_sync_copies 100.00 100.00 100.00
u_pm_en_sync 100.00 100.00 100.00 100.00
u_prim_clock_mux2 100.00 100.00 100.00 100.00
u_prim_flop_2sync_lc_rst_assert 100.00 100.00 100.00
u_prim_flop_2sync_lc_rst_sync 100.00 100.00 100.00
u_prim_lc_sync_lc_dft_en 100.00 100.00 100.00 100.00
u_prim_lc_sync_lc_hw_debug_en 100.00 100.00 100.00 100.00
u_prim_mubi32_sync_late_debug_enable 100.00 100.00 100.00
u_prim_mubi8_sync_otp_dis_rv_dm_late_debug 100.00 100.00 100.00 100.00
u_prim_rst_n_mux2 100.00 100.00 100.00 100.00
u_reg_regs 98.19 98.69 98.71 93.55 100.00 100.00
u_tlul_lc_gate_rom 83.22 93.94 57.50 100.00 77.14 87.50
u_tlul_lc_gate_sba 72.24 90.15 55.00 57.14 71.43 87.50


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : rv_dm
Line No.TotalCoveredPercent
TOTAL333090.91
CONT_ASSIGN12211100.00
CONT_ASSIGN12311100.00
CONT_ASSIGN12811100.00
CONT_ASSIGN13111100.00
CONT_ASSIGN15411100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23711100.00
CONT_ASSIGN23911100.00
CONT_ASSIGN23911100.00
CONT_ASSIGN23911100.00
CONT_ASSIGN23911100.00
CONT_ASSIGN27811100.00
CONT_ASSIGN28811100.00
CONT_ASSIGN28911100.00
ALWAYS32011872.73
CONT_ASSIGN34511100.00
CONT_ASSIGN43211100.00
CONT_ASSIGN43811100.00
CONT_ASSIGN44011100.00
CONT_ASSIGN44611100.00
CONT_ASSIGN44711100.00
CONT_ASSIGN52311100.00
CONT_ASSIGN55111100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rv_dm_0.1/rtl/rv_dm.sv' or '../src/lowrisc_ip_rv_dm_0.1/rtl/rv_dm.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
122 1 1
123 1 1
128 1 1
131 1 1
154 1 1
236 1 1
237 1 1
239 4 4
278 1 1
288 1 1
289 1 1
320 1 1
321 1 1
322 1 1
325 1 1
326 1 1
327 1 1
328 0 1
MISSING_ELSE
331 1 1
332 0 1
333 1 1
334 0 1
MISSING_ELSE
345 1 1
432 1 1
438 1 1
440 1 1
446 1 1
447 1 1
523 1 1
551 1 1


Cond Coverage for Module : rv_dm
TotalCoveredPercent
Conditions472961.70
Logical472961.70
Non-Logical00
Event00

 LINE       128
 EXPRESSION (regs_intg_error | rom_intg_error | sba_gate_intg_error | rom_gate_intg_error)
             -------1-------   -------2------   ---------3---------   ---------4---------
-1--2--3--4-StatusTests
0000CoveredT1,T2,T3
0001Not Covered
0010Not Covered
0100Not Covered
1000CoveredT21,T22,T23

 LINE       131
 SUB-EXPRESSION (regs_reg2hw.alert_test.q & regs_reg2hw.alert_test.qe)
                 ------------1-----------   ------------2------------
-1--2-StatusTests
01CoveredT1,T24,T25
10CoveredT1,T4,T24
11CoveredT1,T24,T25

 LINE       289
 EXPRESSION (ndmreset_req_qual & reset_req_en)
             --------1--------   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT4,T5,T6

 LINE       325
 EXPRESSION (ndmreset_req && ((!ndmreset_pending_q)))
             ------1-----    -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T5,T6
11CoveredT4,T5,T6

 LINE       327
 EXPRESSION (ndmreset_ack && ndmreset_pending_q)
             ------1-----    ---------2--------
-1--2-StatusTests
01CoveredT4,T5,T6
10Not Covered
11Not Covered

 LINE       331
 EXPRESSION (ndmreset_pending_q && lc_rst_asserted)
             ---------1--------    -------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T5,T6
11Not Covered

 LINE       333
 EXPRESSION (ndmreset_ack && lc_rst_pending_q)
             ------1-----    --------2-------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       345
 EXPRESSION (ndmreset_pending_q && lc_rst_pending_q && ((!ndmreset_req)) && ((!lc_rst_asserted)) && reset_req_en)
             ---------1--------    --------2-------    --------3--------    ----------4---------    ------5-----
-1--2--3--4--5-StatusTests
01111Not Covered
10111CoveredT4,T5,T6
11011Not Covered
11101Not Covered
11110Not Covered
11111Not Covered

 LINE       440
 EXPRESSION (debug_req & debug_req_en)
             ----1----   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT2,T4,T5

 LINE       476
 EXPRESSION (dmi_req_ready & dmi_en)
             ------1------   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T6,T26
11CoveredT1,T2,T3

 LINE       476
 EXPRESSION (dmi_rsp_valid & dmi_en)
             ------1------   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       551
 EXPRESSION (device_we || device_re)
             ----1----    ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T5,T6
10CoveredT2,T4,T5

 LINE       567
 EXPRESSION (dmi_req_valid & dmi_en)
             ------1------   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       567
 EXPRESSION (dmi_rsp_ready & dmi_en)
             ------1------   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T6,T26
11CoveredT1,T2,T3

Toggle Coverage for Module : rv_dm
TotalCoveredPercent
Totals 98 79 80.61
Total Bits 1188 1044 87.88
Total Bits 0->1 594 522 87.88
Total Bits 1->0 594 522 87.88

Ports 98 79 80.61
Port Bits 1188 1044 87.88
Port Bits 0->1 594 522 87.88
Port Bits 1->0 594 522 87.88

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
clk_lc_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
rst_lc_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
next_dm_addr_i[31:0] No No No INPUT
lc_hw_debug_en_i[3:0] Yes Yes T26,T27,T15 Yes T5,T26,T27 INPUT
lc_dft_en_i[3:0] Yes Yes T26,T27,T15 Yes T5,T26,T27 INPUT
pinmux_hw_debug_en_i[3:0] Yes Yes T26,T27,T15 Yes T5,T26,T27 INPUT
otp_dis_rv_dm_late_debug_i[7:0] Unreachable Unreachable Unreachable INPUT
scanmode_i[0] No No Yes T4,T6,T28 INPUT
scanmode_i[2:1] No Yes T4,T6,T28 No INPUT
scanmode_i[3] No No Yes T4,T6,T28 INPUT
scan_rst_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
ndmreset_req_o Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
dmactive_o Yes Yes T4,T5,T6 Yes T1,T2,T3 OUTPUT
debug_req_o Yes Yes T4,T5,T6 Yes T2,T4,T5 OUTPUT
unavailable_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
regs_tl_d_i.d_ready Yes Yes T1,T3,T4 Yes T1,T2,T3 INPUT
regs_tl_d_i.a_user.data_intg[6:0] Yes Yes T1,T4,T24 Yes T1,T24,T25 INPUT
regs_tl_d_i.a_user.cmd_intg[6:0] Yes Yes T1,T4,T24 Yes T1,T24,T29 INPUT
regs_tl_d_i.a_user.instr_type[3:0] Yes Yes T4,T24,T29 Yes T24,T29,T30 INPUT
regs_tl_d_i.a_user.rsvd[4:0] Yes Yes T4,T24,T31 Yes T4,T24,T29 INPUT
regs_tl_d_i.a_data[31:0] Yes Yes T1,T4,T24 Yes T1,T24,T25 INPUT
regs_tl_d_i.a_mask[3:0] Yes Yes T24,T29,T30 Yes T4,T24,T29 INPUT
regs_tl_d_i.a_address[31:0] Yes Yes T4,T24,T31 Yes T4,T24,T29 INPUT
regs_tl_d_i.a_source[7:0] Yes Yes T1,T4,T24 Yes T1,T4,T24 INPUT
regs_tl_d_i.a_size[1:0] Yes Yes T1,T4,T24 Yes T1,T4,T24 INPUT
regs_tl_d_i.a_param[2:0] Yes Yes T4,T24,T29 Yes T4,T24,T29 INPUT
regs_tl_d_i.a_opcode[2:0] Yes Yes T1,T4,T24 Yes T1,T24,T25 INPUT
regs_tl_d_i.a_valid Yes Yes T1,T24,T25 Yes T1,T24,T25 INPUT
regs_tl_d_o.a_ready Yes Yes T1,T24,T25 Yes T1,T24,T25 OUTPUT
regs_tl_d_o.d_error Yes Yes T32,T33,T34 Yes T32,T33,T35 OUTPUT
regs_tl_d_o.d_user.data_intg[6:0] Yes Yes T32,T33,T36 Yes T32,T33,T34 OUTPUT
regs_tl_d_o.d_user.rsp_intg[5:0] Yes Yes *T1,*T24,*T25 Yes T1,T24,T25 OUTPUT
regs_tl_d_o.d_user.rsp_intg[6] No No No OUTPUT
regs_tl_d_o.d_data[31:0] Yes Yes T32,T33,T34 Yes T1,T24,T25 OUTPUT
regs_tl_d_o.d_sink No No No OUTPUT
regs_tl_d_o.d_source[7:0] Yes Yes T1,T29,T30 Yes T1,T24,T25 OUTPUT
regs_tl_d_o.d_size[1:0] Yes Yes T1,T24,T25 Yes T1,T24,T25 OUTPUT
regs_tl_d_o.d_param[2:0] No No No OUTPUT
regs_tl_d_o.d_opcode[0] Yes Yes *T32,*T33,*T35 Yes T32,T33,T35 OUTPUT
regs_tl_d_o.d_opcode[2:1] No No No OUTPUT
regs_tl_d_o.d_valid Yes Yes T1,T24,T25 Yes T1,T24,T25 OUTPUT
mem_tl_d_i.d_ready Yes Yes T1,T3,T4 Yes T1,T2,T3 INPUT
mem_tl_d_i.a_user.data_intg[6:0] Yes Yes T2,T4,T5 Yes T2,T4,T5 INPUT
mem_tl_d_i.a_user.cmd_intg[6:0] Yes Yes T2,T4,T5 Yes T2,T4,T5 INPUT
mem_tl_d_i.a_user.instr_type[3:0] Yes Yes T4,T12,T37 Yes T4,T12,T38 INPUT
mem_tl_d_i.a_user.rsvd[4:0] Yes Yes T4,T37,T39 Yes T4,T12,T38 INPUT
mem_tl_d_i.a_data[31:0] Yes Yes T2,T4,T5 Yes T2,T4,T5 INPUT
mem_tl_d_i.a_mask[3:0] Yes Yes T2,T4,T5 Yes T2,T4,T5 INPUT
mem_tl_d_i.a_address[31:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
mem_tl_d_i.a_source[7:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
mem_tl_d_i.a_size[1:0] Yes Yes T2,T4,T5 Yes T2,T4,T5 INPUT
mem_tl_d_i.a_param[2:0] Yes Yes T4,T12,T39 Yes T4,T9,T38 INPUT
mem_tl_d_i.a_opcode[2:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
mem_tl_d_i.a_valid Yes Yes T2,T4,T5 Yes T2,T4,T5 INPUT
mem_tl_d_o.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mem_tl_d_o.d_error Yes Yes T1,T2,T3 Yes T4,T5,T6 OUTPUT
mem_tl_d_o.d_user.data_intg[6:0] Yes Yes T2,T5,T6 Yes T2,T5,T6 OUTPUT
mem_tl_d_o.d_user.rsp_intg[5:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
mem_tl_d_o.d_user.rsp_intg[6] No No No OUTPUT
mem_tl_d_o.d_data[31:0] Yes Yes T1,T2,T3 Yes T2,T4,T5 OUTPUT
mem_tl_d_o.d_sink No No No OUTPUT
mem_tl_d_o.d_source[7:0] Yes Yes T4,T5,T6 Yes T2,T4,T5 OUTPUT
mem_tl_d_o.d_size[1:0] Yes Yes T2,T4,T5 Yes T2,T4,T5 OUTPUT
mem_tl_d_o.d_param[2:0] No No No OUTPUT
mem_tl_d_o.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T2,T4,T5 OUTPUT
mem_tl_d_o.d_opcode[2:1] No No No OUTPUT
mem_tl_d_o.d_valid Yes Yes T2,T4,T5 Yes T2,T4,T5 OUTPUT
sba_tl_h_o.d_ready Yes Yes T4,T5,T6 Yes T1,T2,T3 OUTPUT
sba_tl_h_o.a_user.data_intg[6:0] Yes Yes T3,T9,T10 Yes T3,T9,T10 OUTPUT
sba_tl_h_o.a_user.cmd_intg[6:0] Yes Yes T3,T4,T5 Yes T1,T2,T3 OUTPUT
sba_tl_h_o.a_user.instr_type[0] Yes Yes *T4,*T5,*T6 Yes T1,T2,T3 OUTPUT
sba_tl_h_o.a_user.instr_type[2:1] No No No OUTPUT
sba_tl_h_o.a_user.instr_type[3] Yes Yes T4,T5,T6 Yes T1,T2,T3 OUTPUT
sba_tl_h_o.a_user.rsvd[4:0] No No No OUTPUT
sba_tl_h_o.a_data[31:0] Yes Yes T3,T9,T10 Yes T3,T9,T10 OUTPUT
sba_tl_h_o.a_mask[3:0] Yes Yes T3,T4,T5 Yes T1,T2,T3 OUTPUT
sba_tl_h_o.a_address[1:0] No No No OUTPUT
sba_tl_h_o.a_address[31:2] Yes Yes T3,T9,T10 Yes T3,T9,T10 OUTPUT
sba_tl_h_o.a_source[7:0] No No No OUTPUT
sba_tl_h_o.a_size[0] No No No OUTPUT
sba_tl_h_o.a_size[1] Yes Yes T4,T5,T6 Yes T1,T2,T3 OUTPUT
sba_tl_h_o.a_param[2:0] No No No OUTPUT
sba_tl_h_o.a_opcode[0] Yes Yes *T3,*T9,*T10 Yes T3,T9,T10 OUTPUT
sba_tl_h_o.a_opcode[1] No No No OUTPUT
sba_tl_h_o.a_opcode[2] Yes Yes T3,T4,T5 Yes T1,T2,T3 OUTPUT
sba_tl_h_o.a_valid Yes Yes T3,T9,T10 Yes T3,T9,T10 OUTPUT
sba_tl_h_i.a_ready Yes Yes T1,T3,T4 Yes T1,T2,T3 INPUT
sba_tl_h_i.d_error Yes Yes T3,T16,T9 Yes T3,T9,T10 INPUT
sba_tl_h_i.d_user.data_intg[6:0] Yes Yes T3,T4,T9 Yes T3,T4,T9 INPUT
sba_tl_h_i.d_user.rsp_intg[6:0] Yes Yes T3,T4,T9 Yes T3,T9,T10 INPUT
sba_tl_h_i.d_data[31:0] Yes Yes T3,T4,T16 Yes T3,T9,T10 INPUT
sba_tl_h_i.d_sink Yes Yes T3,T4,T9 Yes T3,T4,T16 INPUT
sba_tl_h_i.d_source[7:0] Yes Yes T3,T4,T16 Yes T3,T4,T9 INPUT
sba_tl_h_i.d_size[1:0] Yes Yes T3,T4,T9 Yes T3,T4,T9 INPUT
sba_tl_h_i.d_param[2:0] Yes Yes T3,T4,T9 Yes T3,T4,T9 INPUT
sba_tl_h_i.d_opcode[2:0] Yes Yes T3,T9,T10 Yes T3,T4,T9 INPUT
sba_tl_h_i.d_valid Yes Yes T3,T9,T10 Yes T3,T9,T10 INPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T1,T24,T25 Yes T1,T24,T25 INPUT
alert_rx_i[0].ping_n No No No INPUT
alert_rx_i[0].ping_p No No No INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T1,T24,T25 Yes T1,T24,T25 OUTPUT
jtag_i.tdi Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
jtag_i.trst_n Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
jtag_i.tms Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
jtag_i.tck Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
jtag_o.tdo_oe Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
jtag_o.tdo Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT

*Tests covering at least one bit in the range

Branch Coverage for Module : rv_dm
Line No.TotalCoveredPercent
Branches 7 4 57.14
IF 320 7 4 57.14

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_rv_dm_0.1/rtl/rv_dm.sv' or '../src/lowrisc_ip_rv_dm_0.1/rtl/rv_dm.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 320 if ((!rst_ni)) -2-: 325 if ((ndmreset_req && (!ndmreset_pending_q))) -3-: 327 if ((ndmreset_ack && ndmreset_pending_q)) -4-: 331 if ((ndmreset_pending_q && lc_rst_asserted)) -5-: 333 if ((ndmreset_ack && lc_rst_pending_q))

Branches:
-1--2--3--4--5-StatusTests
1 - - - - Covered T1,T2,T3
0 1 - - - Covered T4,T5,T6
0 0 1 - - Not Covered
0 0 0 - - Covered T1,T2,T3
0 - - 1 - Not Covered
0 - - 0 1 Not Covered
0 - - 0 0 Covered T1,T2,T3


Assert Coverage for Module : rv_dm
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 16 16 100.00 14 87.50
Cover properties 0 0 0
Cover sequences 0 0 0
Total 16 16 100.00 14 87.50




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DebugReqOKnown_A 20805007 20760942 0 0
DmactiveOKnown_A 20805007 20760942 0 0
FpvSecCmRegWeOnehotCheck_A 20805007 80 0 0
FpvSecCmRomTlLcGateFsm_A 20805007 0 0 0
FpvSecCmSbaTlLcGateFsm_A 20805007 0 0 0
JtagRspOTdoKnown_A 9795129 9794730 0 0
JtagRspOTdoOeKnown_A 9795129 9794730 0 0
NdmresetOKnown_A 20805007 20760942 0 0
RvDmLcEnDebugVal_A 20805007 20760942 0 0
TlMemAReadyKnown_A 20805007 20760942 0 0
TlMemDValidKnown_A 20805007 20760942 0 0
TlRegsAReadyKnown_A 20805007 20760942 0 0
TlRegsDValidKnown_A 20805007 20760942 0 0
TlSbaAValidKnown_A 20805007 20760942 0 0
TlSbaDReadyKnown_A 20805007 20760942 0 0
paramCheckNrHarts 167 167 0 0


DebugReqOKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 20805007 20760942 0 0
T1 2255 2174 0 0
T2 4849 4789 0 0
T3 67774 67723 0 0
T4 48186 47893 0 0
T5 129682 129454 0 0
T6 124519 124347 0 0
T16 9283 9195 0 0
T24 1987 1926 0 0
T40 5063 4993 0 0
T41 2389 2323 0 0

DmactiveOKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 20805007 20760942 0 0
T1 2255 2174 0 0
T2 4849 4789 0 0
T3 67774 67723 0 0
T4 48186 47893 0 0
T5 129682 129454 0 0
T6 124519 124347 0 0
T16 9283 9195 0 0
T24 1987 1926 0 0
T40 5063 4993 0 0
T41 2389 2323 0 0

FpvSecCmRegWeOnehotCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 20805007 80 0 0
T7 187301 0 0 0
T11 384293 0 0 0
T12 282093 0 0 0
T13 646533 0 0 0
T21 5145 10 0 0
T22 0 20 0 0
T23 0 10 0 0
T30 1568 0 0 0
T42 0 20 0 0
T43 0 20 0 0
T44 1223 0 0 0
T45 1230 0 0 0
T46 219975 0 0 0
T47 515038 0 0 0

FpvSecCmRomTlLcGateFsm_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 20805007 0 0 0

FpvSecCmSbaTlLcGateFsm_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 20805007 0 0 0

JtagRspOTdoKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9795129 9794730 0 0
T1 117 117 0 0
T2 1068 1068 0 0
T3 87091 87091 0 0
T4 13257 13256 0 0
T5 47185 47184 0 0
T6 47046 47045 0 0
T16 2046 2046 0 0
T24 107 107 0 0
T40 1550 1550 0 0
T41 654 654 0 0

JtagRspOTdoOeKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9795129 9794730 0 0
T1 117 117 0 0
T2 1068 1068 0 0
T3 87091 87091 0 0
T4 13257 13256 0 0
T5 47185 47184 0 0
T6 47046 47045 0 0
T16 2046 2046 0 0
T24 107 107 0 0
T40 1550 1550 0 0
T41 654 654 0 0

NdmresetOKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 20805007 20760942 0 0
T1 2255 2174 0 0
T2 4849 4789 0 0
T3 67774 67723 0 0
T4 48186 47893 0 0
T5 129682 129454 0 0
T6 124519 124347 0 0
T16 9283 9195 0 0
T24 1987 1926 0 0
T40 5063 4993 0 0
T41 2389 2323 0 0

RvDmLcEnDebugVal_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 20805007 20760942 0 0
T1 2255 2174 0 0
T2 4849 4789 0 0
T3 67774 67723 0 0
T4 48186 47893 0 0
T5 129682 129454 0 0
T6 124519 124347 0 0
T16 9283 9195 0 0
T24 1987 1926 0 0
T40 5063 4993 0 0
T41 2389 2323 0 0

TlMemAReadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 20805007 20760942 0 0
T1 2255 2174 0 0
T2 4849 4789 0 0
T3 67774 67723 0 0
T4 48186 47893 0 0
T5 129682 129454 0 0
T6 124519 124347 0 0
T16 9283 9195 0 0
T24 1987 1926 0 0
T40 5063 4993 0 0
T41 2389 2323 0 0

TlMemDValidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 20805007 20760942 0 0
T1 2255 2174 0 0
T2 4849 4789 0 0
T3 67774 67723 0 0
T4 48186 47893 0 0
T5 129682 129454 0 0
T6 124519 124347 0 0
T16 9283 9195 0 0
T24 1987 1926 0 0
T40 5063 4993 0 0
T41 2389 2323 0 0

TlRegsAReadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 20805007 20760942 0 0
T1 2255 2174 0 0
T2 4849 4789 0 0
T3 67774 67723 0 0
T4 48186 47893 0 0
T5 129682 129454 0 0
T6 124519 124347 0 0
T16 9283 9195 0 0
T24 1987 1926 0 0
T40 5063 4993 0 0
T41 2389 2323 0 0

TlRegsDValidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 20805007 20760942 0 0
T1 2255 2174 0 0
T2 4849 4789 0 0
T3 67774 67723 0 0
T4 48186 47893 0 0
T5 129682 129454 0 0
T6 124519 124347 0 0
T16 9283 9195 0 0
T24 1987 1926 0 0
T40 5063 4993 0 0
T41 2389 2323 0 0

TlSbaAValidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 20805007 20760942 0 0
T1 2255 2174 0 0
T2 4849 4789 0 0
T3 67774 67723 0 0
T4 48186 47893 0 0
T5 129682 129454 0 0
T6 124519 124347 0 0
T16 9283 9195 0 0
T24 1987 1926 0 0
T40 5063 4993 0 0
T41 2389 2323 0 0

TlSbaDReadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 20805007 20760942 0 0
T1 2255 2174 0 0
T2 4849 4789 0 0
T3 67774 67723 0 0
T4 48186 47893 0 0
T5 129682 129454 0 0
T6 124519 124347 0 0
T16 9283 9195 0 0
T24 1987 1926 0 0
T40 5063 4993 0 0
T41 2389 2323 0 0

paramCheckNrHarts
NameAttemptsReal SuccessesFailuresIncomplete
Total 167 167 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T16 1 1 0 0
T24 1 1 0 0
T40 1 1 0 0
T41 1 1 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%