SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_prim_mubi32_sync_late_debug_enable | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
77.03 | 90.91 | 61.70 | 87.88 | 57.14 | 87.50 | dut |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 5 | 5 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 4 | 4 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 167 | 167 | 0 | 0 |
OutputsKnown_A | 20805007 | 20760942 | 0 | 0 |
gen_no_flops.OutputDelay_A | 20805007 | 20760942 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 167 | 167 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T24 | 1 | 1 | 0 | 0 |
T40 | 1 | 1 | 0 | 0 |
T41 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 20805007 | 20760942 | 0 | 0 |
T1 | 2255 | 2174 | 0 | 0 |
T2 | 4849 | 4789 | 0 | 0 |
T3 | 67774 | 67723 | 0 | 0 |
T4 | 48186 | 47893 | 0 | 0 |
T5 | 129682 | 129454 | 0 | 0 |
T6 | 124519 | 124347 | 0 | 0 |
T16 | 9283 | 9195 | 0 | 0 |
T24 | 1987 | 1926 | 0 | 0 |
T40 | 5063 | 4993 | 0 | 0 |
T41 | 2389 | 2323 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 20805007 | 20760942 | 0 | 0 |
T1 | 2255 | 2174 | 0 | 0 |
T2 | 4849 | 4789 | 0 | 0 |
T3 | 67774 | 67723 | 0 | 0 |
T4 | 48186 | 47893 | 0 | 0 |
T5 | 129682 | 129454 | 0 | 0 |
T6 | 124519 | 124347 | 0 | 0 |
T16 | 9283 | 9195 | 0 | 0 |
T24 | 1987 | 1926 | 0 | 0 |
T40 | 5063 | 4993 | 0 | 0 |
T41 | 2389 | 2323 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |