SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_prim_lc_sync_lc_hw_debug_en | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_prim_lc_sync_lc_dft_en | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_lc_en_sync_copies | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_pm_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_tlul_lc_gate_sba.u_err_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_tlul_lc_gate_rom.u_err_en_sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
77.03 | 90.91 | 61.70 | 87.88 | 57.14 | 87.50 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
77.03 | 90.91 | 61.70 | 87.88 | 57.14 | 87.50 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
77.03 | 90.91 | 61.70 | 87.88 | 57.14 | 87.50 | dut |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
77.03 | 90.91 | 61.70 | 87.88 | 57.14 | 87.50 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
68.13 | 86.27 | 72.22 | 57.14 | 75.00 | 50.00 | u_tlul_lc_gate_sba |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
81.44 | 96.08 | 77.78 | 100.00 | 83.33 | 50.00 | u_tlul_lc_gate_rom |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 6 | 6 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 5 | 5 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 3 | 3 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 4 | 4 | 100.00 | 4 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 4 | 4 | 100.00 | 4 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1002 | 1002 | 0 | 0 |
OutputsKnown_A | 124830042 | 124565652 | 0 | 0 |
gen_flops.OutputDelay_A | 62415021 | 62276904 | 0 | 1503 |
gen_no_flops.OutputDelay_A | 62415021 | 62282826 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1002 | 1002 | 0 | 0 |
T1 | 6 | 6 | 0 | 0 |
T2 | 6 | 6 | 0 | 0 |
T3 | 6 | 6 | 0 | 0 |
T4 | 6 | 6 | 0 | 0 |
T5 | 6 | 6 | 0 | 0 |
T6 | 6 | 6 | 0 | 0 |
T16 | 6 | 6 | 0 | 0 |
T24 | 6 | 6 | 0 | 0 |
T40 | 6 | 6 | 0 | 0 |
T41 | 6 | 6 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 124830042 | 124565652 | 0 | 0 |
T1 | 13530 | 13044 | 0 | 0 |
T2 | 29094 | 28734 | 0 | 0 |
T3 | 406644 | 406338 | 0 | 0 |
T4 | 289116 | 287358 | 0 | 0 |
T5 | 778092 | 776724 | 0 | 0 |
T6 | 747114 | 746082 | 0 | 0 |
T16 | 55698 | 55170 | 0 | 0 |
T24 | 11922 | 11556 | 0 | 0 |
T40 | 30378 | 29958 | 0 | 0 |
T41 | 14334 | 13938 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 62415021 | 62276904 | 0 | 1503 |
T1 | 6765 | 6513 | 0 | 9 |
T2 | 14547 | 14358 | 0 | 9 |
T3 | 203322 | 203160 | 0 | 9 |
T4 | 144558 | 143643 | 0 | 9 |
T5 | 389046 | 388326 | 0 | 9 |
T6 | 373557 | 373014 | 0 | 9 |
T16 | 27849 | 27576 | 0 | 9 |
T24 | 5961 | 5769 | 0 | 9 |
T40 | 15189 | 14970 | 0 | 9 |
T41 | 7167 | 6960 | 0 | 9 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 62415021 | 62282826 | 0 | 0 |
T1 | 6765 | 6522 | 0 | 0 |
T2 | 14547 | 14367 | 0 | 0 |
T3 | 203322 | 203169 | 0 | 0 |
T4 | 144558 | 143679 | 0 | 0 |
T5 | 389046 | 388362 | 0 | 0 |
T6 | 373557 | 373041 | 0 | 0 |
T16 | 27849 | 27585 | 0 | 0 |
T24 | 5961 | 5778 | 0 | 0 |
T40 | 15189 | 14979 | 0 | 0 |
T41 | 7167 | 6969 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 167 | 167 | 0 | 0 |
OutputsKnown_A | 20805007 | 20760942 | 0 | 0 |
gen_flops.OutputDelay_A | 20805007 | 20758968 | 0 | 501 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 167 | 167 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T24 | 1 | 1 | 0 | 0 |
T40 | 1 | 1 | 0 | 0 |
T41 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 20805007 | 20760942 | 0 | 0 |
T1 | 2255 | 2174 | 0 | 0 |
T2 | 4849 | 4789 | 0 | 0 |
T3 | 67774 | 67723 | 0 | 0 |
T4 | 48186 | 47893 | 0 | 0 |
T5 | 129682 | 129454 | 0 | 0 |
T6 | 124519 | 124347 | 0 | 0 |
T16 | 9283 | 9195 | 0 | 0 |
T24 | 1987 | 1926 | 0 | 0 |
T40 | 5063 | 4993 | 0 | 0 |
T41 | 2389 | 2323 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 20805007 | 20758968 | 0 | 501 |
T1 | 2255 | 2171 | 0 | 3 |
T2 | 4849 | 4786 | 0 | 3 |
T3 | 67774 | 67720 | 0 | 3 |
T4 | 48186 | 47881 | 0 | 3 |
T5 | 129682 | 129442 | 0 | 3 |
T6 | 124519 | 124338 | 0 | 3 |
T16 | 9283 | 9192 | 0 | 3 |
T24 | 1987 | 1923 | 0 | 3 |
T40 | 5063 | 4990 | 0 | 3 |
T41 | 2389 | 2320 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 167 | 167 | 0 | 0 |
OutputsKnown_A | 20805007 | 20760942 | 0 | 0 |
gen_flops.OutputDelay_A | 20805007 | 20758968 | 0 | 501 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 167 | 167 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T24 | 1 | 1 | 0 | 0 |
T40 | 1 | 1 | 0 | 0 |
T41 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 20805007 | 20760942 | 0 | 0 |
T1 | 2255 | 2174 | 0 | 0 |
T2 | 4849 | 4789 | 0 | 0 |
T3 | 67774 | 67723 | 0 | 0 |
T4 | 48186 | 47893 | 0 | 0 |
T5 | 129682 | 129454 | 0 | 0 |
T6 | 124519 | 124347 | 0 | 0 |
T16 | 9283 | 9195 | 0 | 0 |
T24 | 1987 | 1926 | 0 | 0 |
T40 | 5063 | 4993 | 0 | 0 |
T41 | 2389 | 2323 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 20805007 | 20758968 | 0 | 501 |
T1 | 2255 | 2171 | 0 | 3 |
T2 | 4849 | 4786 | 0 | 3 |
T3 | 67774 | 67720 | 0 | 3 |
T4 | 48186 | 47881 | 0 | 3 |
T5 | 129682 | 129442 | 0 | 3 |
T6 | 124519 | 124338 | 0 | 3 |
T16 | 9283 | 9192 | 0 | 3 |
T24 | 1987 | 1923 | 0 | 3 |
T40 | 5063 | 4990 | 0 | 3 |
T41 | 2389 | 2320 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 6 | 6 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 5 | 5 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 167 | 167 | 0 | 0 |
OutputsKnown_A | 20805007 | 20760942 | 0 | 0 |
gen_no_flops.OutputDelay_A | 20805007 | 20760942 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 167 | 167 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T24 | 1 | 1 | 0 | 0 |
T40 | 1 | 1 | 0 | 0 |
T41 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 20805007 | 20760942 | 0 | 0 |
T1 | 2255 | 2174 | 0 | 0 |
T2 | 4849 | 4789 | 0 | 0 |
T3 | 67774 | 67723 | 0 | 0 |
T4 | 48186 | 47893 | 0 | 0 |
T5 | 129682 | 129454 | 0 | 0 |
T6 | 124519 | 124347 | 0 | 0 |
T16 | 9283 | 9195 | 0 | 0 |
T24 | 1987 | 1926 | 0 | 0 |
T40 | 5063 | 4993 | 0 | 0 |
T41 | 2389 | 2323 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 20805007 | 20760942 | 0 | 0 |
T1 | 2255 | 2174 | 0 | 0 |
T2 | 4849 | 4789 | 0 | 0 |
T3 | 67774 | 67723 | 0 | 0 |
T4 | 48186 | 47893 | 0 | 0 |
T5 | 129682 | 129454 | 0 | 0 |
T6 | 124519 | 124347 | 0 | 0 |
T16 | 9283 | 9195 | 0 | 0 |
T24 | 1987 | 1926 | 0 | 0 |
T40 | 5063 | 4993 | 0 | 0 |
T41 | 2389 | 2323 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 3 | 3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 167 | 167 | 0 | 0 |
OutputsKnown_A | 20805007 | 20760942 | 0 | 0 |
gen_flops.OutputDelay_A | 20805007 | 20758968 | 0 | 501 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 167 | 167 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T24 | 1 | 1 | 0 | 0 |
T40 | 1 | 1 | 0 | 0 |
T41 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 20805007 | 20760942 | 0 | 0 |
T1 | 2255 | 2174 | 0 | 0 |
T2 | 4849 | 4789 | 0 | 0 |
T3 | 67774 | 67723 | 0 | 0 |
T4 | 48186 | 47893 | 0 | 0 |
T5 | 129682 | 129454 | 0 | 0 |
T6 | 124519 | 124347 | 0 | 0 |
T16 | 9283 | 9195 | 0 | 0 |
T24 | 1987 | 1926 | 0 | 0 |
T40 | 5063 | 4993 | 0 | 0 |
T41 | 2389 | 2323 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 20805007 | 20758968 | 0 | 501 |
T1 | 2255 | 2171 | 0 | 3 |
T2 | 4849 | 4786 | 0 | 3 |
T3 | 67774 | 67720 | 0 | 3 |
T4 | 48186 | 47881 | 0 | 3 |
T5 | 129682 | 129442 | 0 | 3 |
T6 | 124519 | 124338 | 0 | 3 |
T16 | 9283 | 9192 | 0 | 3 |
T24 | 1987 | 1923 | 0 | 3 |
T40 | 5063 | 4990 | 0 | 3 |
T41 | 2389 | 2320 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 167 | 167 | 0 | 0 |
OutputsKnown_A | 20805007 | 20760942 | 0 | 0 |
gen_no_flops.OutputDelay_A | 20805007 | 20760942 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 167 | 167 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T24 | 1 | 1 | 0 | 0 |
T40 | 1 | 1 | 0 | 0 |
T41 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 20805007 | 20760942 | 0 | 0 |
T1 | 2255 | 2174 | 0 | 0 |
T2 | 4849 | 4789 | 0 | 0 |
T3 | 67774 | 67723 | 0 | 0 |
T4 | 48186 | 47893 | 0 | 0 |
T5 | 129682 | 129454 | 0 | 0 |
T6 | 124519 | 124347 | 0 | 0 |
T16 | 9283 | 9195 | 0 | 0 |
T24 | 1987 | 1926 | 0 | 0 |
T40 | 5063 | 4993 | 0 | 0 |
T41 | 2389 | 2323 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 20805007 | 20760942 | 0 | 0 |
T1 | 2255 | 2174 | 0 | 0 |
T2 | 4849 | 4789 | 0 | 0 |
T3 | 67774 | 67723 | 0 | 0 |
T4 | 48186 | 47893 | 0 | 0 |
T5 | 129682 | 129454 | 0 | 0 |
T6 | 124519 | 124347 | 0 | 0 |
T16 | 9283 | 9195 | 0 | 0 |
T24 | 1987 | 1926 | 0 | 0 |
T40 | 5063 | 4993 | 0 | 0 |
T41 | 2389 | 2323 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 167 | 167 | 0 | 0 |
OutputsKnown_A | 20805007 | 20760942 | 0 | 0 |
gen_no_flops.OutputDelay_A | 20805007 | 20760942 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 167 | 167 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T24 | 1 | 1 | 0 | 0 |
T40 | 1 | 1 | 0 | 0 |
T41 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 20805007 | 20760942 | 0 | 0 |
T1 | 2255 | 2174 | 0 | 0 |
T2 | 4849 | 4789 | 0 | 0 |
T3 | 67774 | 67723 | 0 | 0 |
T4 | 48186 | 47893 | 0 | 0 |
T5 | 129682 | 129454 | 0 | 0 |
T6 | 124519 | 124347 | 0 | 0 |
T16 | 9283 | 9195 | 0 | 0 |
T24 | 1987 | 1926 | 0 | 0 |
T40 | 5063 | 4993 | 0 | 0 |
T41 | 2389 | 2323 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 20805007 | 20760942 | 0 | 0 |
T1 | 2255 | 2174 | 0 | 0 |
T2 | 4849 | 4789 | 0 | 0 |
T3 | 67774 | 67723 | 0 | 0 |
T4 | 48186 | 47893 | 0 | 0 |
T5 | 129682 | 129454 | 0 | 0 |
T6 | 124519 | 124347 | 0 | 0 |
T16 | 9283 | 9195 | 0 | 0 |
T24 | 1987 | 1926 | 0 | 0 |
T40 | 5063 | 4993 | 0 | 0 |
T41 | 2389 | 2323 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |