Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	223476	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	577473	1		T1	4		T4	1		T13	80

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	514474	1		T13	80		T22	8		T15	20
values[0x0]	141257	1		T1	14		T4	2		T5	4
values[0x1]	145218	1		T1	16		T4	3		T5	1

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	170105	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	630844	1		T1	7		T4	2		T13	80

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2945	1		T48	2		T49	23		T76	6
valid_sources[0x01]	3332	1		T14	1		T48	5		T49	22
valid_sources[0x02]	4401	1		T13	1		T21	1		T14	1
valid_sources[0x03]	2058	1		T48	9		T49	29		T46	24
valid_sources[0x04]	2664	1		T48	5		T49	17		T76	8
valid_sources[0x05]	2830	1		T75	2		T48	2		T45	275
valid_sources[0x06]	3605	1		T15	1		T17	2		T14	2
valid_sources[0x07]	3118	1		T21	1		T48	2		T49	30
valid_sources[0x08]	3294	1		T15	1		T48	3		T45	11
valid_sources[0x09]	3307	1		T49	21		T76	3		T47	13
valid_sources[0x0a]	2463	1		T48	2		T49	27		T76	5
valid_sources[0x0b]	3580	1		T15	5		T48	3		T49	28
valid_sources[0x0c]	3349	1		T18	2		T49	15		T76	4
valid_sources[0x0d]	3498	1		T14	1		T48	1		T49	12
valid_sources[0x0e]	2846	1		T48	5		T49	16		T46	5
valid_sources[0x0f]	2252	1		T75	1		T14	3		T48	3
valid_sources[0x10]	2743	1		T14	1		T45	4		T49	20
valid_sources[0x11]	3271	1		T48	5		T45	1		T49	25
valid_sources[0x12]	2966	1		T75	1		T48	6		T49	50
valid_sources[0x13]	2587	1		T9	1		T48	2		T49	24
valid_sources[0x14]	3098	1		T17	1		T14	1		T48	1
valid_sources[0x15]	2757	1		T14	3		T48	4		T49	11
valid_sources[0x16]	3023	1		T9	1		T48	3		T49	29
valid_sources[0x17]	3599	1		T14	2		T48	4		T49	19
valid_sources[0x18]	2841	1		T9	1		T48	4		T49	18
valid_sources[0x19]	2957	1		T49	28		T76	3		T47	18
valid_sources[0x1a]	2690	1		T75	1		T45	7		T49	20
valid_sources[0x1b]	3134	1		T21	5		T14	1		T48	2
valid_sources[0x1c]	3944	1		T21	1		T14	1		T48	4
valid_sources[0x1d]	4422	1		T22	1		T14	1		T48	1
valid_sources[0x1e]	3317	1		T9	1		T48	3		T49	26
valid_sources[0x1f]	3784	1		T48	2		T45	5		T49	32
valid_sources[0x20]	3351	1		T13	4		T18	2		T48	6
valid_sources[0x21]	3130	1		T48	6		T49	13		T76	3
valid_sources[0x22]	3696	1		T9	1		T48	2		T45	6
valid_sources[0x23]	2249	1		T48	3		T49	20		T76	7
valid_sources[0x24]	3714	1		T48	5		T45	284		T49	23
valid_sources[0x25]	2406	1		T48	3		T49	20		T76	6
valid_sources[0x26]	3633	1		T9	1		T48	1		T49	16
valid_sources[0x27]	2888	1		T48	5		T49	33		T76	6
valid_sources[0x28]	2573	1		T22	1		T48	3		T49	31
valid_sources[0x29]	2716	1		T17	1		T48	6		T49	17
valid_sources[0x2a]	3208	1		T48	7		T49	14		T76	4
valid_sources[0x2b]	3242	1		T48	4		T49	20		T76	3
valid_sources[0x2c]	3805	1		T13	1		T48	4		T49	23
valid_sources[0x2d]	2825	1		T36	1		T48	1		T45	2
valid_sources[0x2e]	2964	1		T48	2		T49	33		T76	7
valid_sources[0x2f]	2833	1		T48	6		T49	15		T46	8
valid_sources[0x30]	3183	1		T13	1		T22	1		T10	31
valid_sources[0x31]	2842	1		T9	1		T49	13		T46	21
valid_sources[0x32]	4007	1		T14	1		T48	1		T49	26
valid_sources[0x33]	2975	1		T11	20		T14	1		T48	5
valid_sources[0x34]	3019	1		T9	1		T48	4		T49	25
valid_sources[0x35]	3345	1		T45	2		T49	23		T76	5
valid_sources[0x36]	4520	1		T9	1		T48	1		T49	30
valid_sources[0x37]	3281	1		T21	1		T14	2		T48	4
valid_sources[0x38]	3181	1		T14	1		T138	1		T48	13
valid_sources[0x39]	2349	1		T48	6		T45	3		T49	10
valid_sources[0x3a]	3598	1		T75	2		T48	5		T45	215
valid_sources[0x3b]	3261	1		T14	1		T48	11		T45	275
valid_sources[0x3c]	3230	1		T15	6		T16	1		T48	4
valid_sources[0x3d]	2989	1		T36	1		T48	8		T45	1
valid_sources[0x3e]	2810	1		T9	1		T49	20		T46	41
valid_sources[0x3f]	4022	1		T16	1		T75	1		T48	3
valid_sources[0x40]	3579	1		T48	3		T49	21		T47	11
valid_sources[0x41]	3022	1		T8	163		T75	1		T48	19
valid_sources[0x42]	3187	1		T14	1		T48	7		T49	43
valid_sources[0x43]	2631	1		T48	7		T45	7		T49	23
valid_sources[0x44]	3402	1		T48	6		T49	18		T76	4
valid_sources[0x45]	2558	1		T23	9		T48	3		T49	21
valid_sources[0x46]	2600	1		T48	3		T49	14		T76	6
valid_sources[0x47]	2995	1		T18	5		T75	1		T48	2
valid_sources[0x48]	2721	1		T14	1		T48	4		T49	33
valid_sources[0x49]	3084	1		T13	4		T17	1		T48	8
valid_sources[0x4a]	3695	1		T9	1		T75	2		T48	2
valid_sources[0x4b]	2447	1		T13	3		T18	2		T14	2
valid_sources[0x4c]	3631	1		T36	1		T49	28		T76	6
valid_sources[0x4d]	3589	1		T48	2		T49	25		T76	8
valid_sources[0x4e]	3294	1		T21	1		T48	8		T49	21
valid_sources[0x4f]	3042	1		T48	2		T49	22		T76	4
valid_sources[0x50]	3214	1		T75	1		T14	1		T48	4
valid_sources[0x51]	3139	1		T5	1		T14	1		T48	10
valid_sources[0x52]	2987	1		T48	7		T49	22		T76	5
valid_sources[0x53]	3084	1		T9	1		T17	1		T14	2
valid_sources[0x54]	3254	1		T14	1		T48	9		T45	5
valid_sources[0x55]	2533	1		T48	6		T45	31		T49	14
valid_sources[0x56]	3863	1		T14	1		T48	7		T45	18
valid_sources[0x57]	2751	1		T48	4		T49	14		T76	5
valid_sources[0x58]	3265	1		T48	13		T49	31		T76	2
valid_sources[0x59]	2937	1		T9	1		T48	1		T49	23
valid_sources[0x5a]	3042	1		T48	2		T49	18		T76	5
valid_sources[0x5b]	3343	1		T49	16		T76	2		T47	19
valid_sources[0x5c]	3086	1		T48	5		T49	20		T76	7
valid_sources[0x5d]	4059	1		T49	20		T46	1275		T76	1
valid_sources[0x5e]	2563	1		T14	2		T48	7		T49	24
valid_sources[0x5f]	3008	1		T48	7		T45	9		T49	42
valid_sources[0x60]	2555	1		T9	1		T48	4		T49	20
valid_sources[0x61]	2916	1		T48	19		T49	34		T76	4
valid_sources[0x62]	3707	1		T36	2		T48	5		T45	44
valid_sources[0x63]	3523	1		T48	9		T49	19		T46	24
valid_sources[0x64]	2987	1		T48	1		T45	22		T49	29
valid_sources[0x65]	2968	1		T21	3		T14	2		T48	6
valid_sources[0x66]	2640	1		T36	1		T48	4		T49	28
valid_sources[0x67]	2650	1		T48	5		T49	19		T76	4
valid_sources[0x68]	3901	1		T15	3		T48	5		T49	36
valid_sources[0x69]	2944	1		T36	1		T14	1		T48	2
valid_sources[0x6a]	2691	1		T75	1		T48	1		T49	16
valid_sources[0x6b]	2577	1		T48	7		T49	26		T76	8
valid_sources[0x6c]	3724	1		T48	3		T49	39		T76	3
valid_sources[0x6d]	3897	1		T48	7		T49	28		T46	21
valid_sources[0x6e]	3709	1		T9	1		T48	3		T49	8
valid_sources[0x6f]	3261	1		T75	1		T14	1		T48	7
valid_sources[0x70]	4322	1		T48	6		T45	1406		T49	28
valid_sources[0x71]	2645	1		T48	7		T49	27		T76	5
valid_sources[0x72]	3978	1		T14	1		T48	7		T49	23
valid_sources[0x73]	3290	1		T14	1		T48	4		T49	32
valid_sources[0x74]	3690	1		T75	5		T14	1		T49	29
valid_sources[0x75]	3589	1		T48	3		T49	32		T76	7
valid_sources[0x76]	2757	1		T19	10		T48	1		T49	36
valid_sources[0x77]	3574	1		T18	1		T48	1		T49	34
valid_sources[0x78]	3385	1		T48	4		T49	4		T76	4
valid_sources[0x79]	3260	1		T14	1		T48	6		T45	275
valid_sources[0x7a]	2915	1		T48	5		T49	20		T76	4
valid_sources[0x7b]	2866	1		T48	4		T45	28		T49	12
valid_sources[0x7c]	2550	1		T9	2		T48	6		T49	39
valid_sources[0x7d]	3414	1		T48	7		T49	16		T76	5
valid_sources[0x7e]	2928	1		T14	1		T48	13		T45	3
valid_sources[0x7f]	3409	1		T13	11		T75	1		T48	1
valid_sources[0x80]	4013	1		T48	6		T49	24		T76	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

299461

1

T13

80

T22

2

T15

9

values[0x0]

all_enables

biggest_size

139537

1

T1

1

T5

1

T15

8

values[0x1]

all_enables

biggest_size

138475

1

T1

3

T4

1

T15

12

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4714	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	18078	1		T2	4		T3	3		T35	1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	9117	1		T48	6		T45	33		T49	29
values[0x0]	6728	1		T2	6		T3	5		T35	2
values[0x1]	6947	1		T2	3		T3	6		T35	2

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3597	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	19195	1		T2	5		T3	4		T35	1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	91	1		T119	2		T61	2		T67	1
valid_sources[0x01]	100	1		T76	1		T47	2		T69	1
valid_sources[0x02]	92	1		T139	1		T140	1		T68	1
valid_sources[0x03]	127	1		T141	2		T47	2		T77	1
valid_sources[0x04]	54	1		T46	2		T67	2		T60	1
valid_sources[0x05]	161	1		T61	1		T76	1		T68	3
valid_sources[0x06]	64	1		T142	1		T60	1		T73	1
valid_sources[0x07]	75	1		T119	1		T76	1		T67	3
valid_sources[0x08]	88	1		T143	1		T144	3		T67	5
valid_sources[0x09]	115	1		T46	1		T69	1		T60	1
valid_sources[0x0a]	65	1		T67	2		T59	1		T60	1
valid_sources[0x0b]	98	1		T142	1		T45	2		T59	1
valid_sources[0x0c]	60	1		T44	1		T69	1		T72	1
valid_sources[0x0d]	82	1		T49	1		T69	1		T60	1
valid_sources[0x0e]	73	1		T39	2		T46	1		T68	1
valid_sources[0x0f]	80	1		T55	3		T68	1		T59	1
valid_sources[0x10]	59	1		T145	1		T68	1		T60	1
valid_sources[0x11]	52	1		T145	2		T45	1		T67	1
valid_sources[0x12]	871	1		T122	1		T47	1		T68	1
valid_sources[0x13]	64	1		T146	3		T139	1		T61	1
valid_sources[0x14]	64	1		T42	1		T147	1		T67	1
valid_sources[0x15]	95	1		T49	1		T69	1		T72	2
valid_sources[0x16]	69	1		T148	1		T140	1		T68	1
valid_sources[0x17]	94	1		T49	2		T76	2		T69	3
valid_sources[0x18]	68	1		T47	2		T68	1		T72	2
valid_sources[0x19]	59	1		T46	2		T67	3		T68	1
valid_sources[0x1a]	92	1		T149	9		T150	1		T59	2
valid_sources[0x1b]	73	1		T45	1		T59	2		T74	5
valid_sources[0x1c]	95	1		T151	3		T152	3		T76	1
valid_sources[0x1d]	99	1		T143	2		T67	4		T60	1
valid_sources[0x1e]	52	1		T148	1		T49	7		T72	3
valid_sources[0x1f]	74	1		T39	1		T47	1		T68	2
valid_sources[0x20]	90	1		T45	1		T71	3		T72	3
valid_sources[0x21]	72	1		T72	1		T121	1		T127	3
valid_sources[0x22]	108	1		T45	1		T47	3		T69	1
valid_sources[0x23]	62	1		T153	1		T151	1		T77	1
valid_sources[0x24]	83	1		T48	8		T76	1		T67	1
valid_sources[0x25]	64	1		T47	3		T59	2		T85	4
valid_sources[0x26]	59	1		T154	1		T49	5		T47	2
valid_sources[0x27]	58	1		T67	1		T59	1		T72	2
valid_sources[0x28]	109	1		T68	1		T72	2		T81	4
valid_sources[0x29]	61	1		T139	2		T69	1		T60	1
valid_sources[0x2a]	121	1		T43	2		T55	4		T61	1
valid_sources[0x2b]	64	1		T59	3		T60	1		T71	3
valid_sources[0x2c]	79	1		T47	1		T60	1		T72	1
valid_sources[0x2d]	104	1		T119	2		T46	1		T67	1
valid_sources[0x2e]	146	1		T45	1		T49	10		T68	1
valid_sources[0x2f]	108	1		T145	1		T49	3		T68	1
valid_sources[0x30]	63	1		T124	1		T46	1		T69	1
valid_sources[0x31]	82	1		T150	1		T68	1		T69	1
valid_sources[0x32]	75	1		T49	1		T68	2		T72	2
valid_sources[0x33]	52	1		T46	1		T76	1		T68	2
valid_sources[0x34]	67	1		T50	1		T139	1		T155	1
valid_sources[0x35]	55	1		T45	1		T68	2		T59	2
valid_sources[0x36]	47	1		T156	1		T48	1		T69	1
valid_sources[0x37]	56	1		T157	1		T45	2		T67	1
valid_sources[0x38]	68	1		T68	1		T69	1		T59	1
valid_sources[0x39]	176	1		T67	1		T59	2		T72	2
valid_sources[0x3a]	52	1		T60	1		T72	4		T73	1
valid_sources[0x3b]	60	1		T69	1		T59	1		T72	4
valid_sources[0x3c]	94	1		T2	9		T68	2		T72	2
valid_sources[0x3d]	71	1		T39	1		T67	3		T68	3
valid_sources[0x3e]	68	1		T148	1		T67	3		T69	2
valid_sources[0x3f]	43	1		T68	1		T69	1		T59	1
valid_sources[0x40]	61	1		T156	1		T67	2		T69	2
valid_sources[0x41]	85	1		T157	1		T68	1		T72	4
valid_sources[0x42]	72	1		T68	2		T69	1		T59	1
valid_sources[0x43]	56	1		T142	1		T76	1		T69	2
valid_sources[0x44]	101	1		T150	2		T46	1		T68	1
valid_sources[0x45]	67	1		T45	1		T47	1		T67	2
valid_sources[0x46]	89	1		T68	2		T60	1		T72	1
valid_sources[0x47]	65	1		T55	2		T68	2		T60	2
valid_sources[0x48]	82	1		T52	22		T46	1		T59	2
valid_sources[0x49]	80	1		T141	3		T68	2		T59	1
valid_sources[0x4a]	83	1		T147	1		T154	2		T148	1
valid_sources[0x4b]	161	1		T72	2		T85	7		T83	72
valid_sources[0x4c]	78	1		T120	2		T140	1		T69	1
valid_sources[0x4d]	67	1		T46	1		T69	1		T59	1
valid_sources[0x4e]	68	1		T67	1		T59	5		T71	1
valid_sources[0x4f]	71	1		T158	3		T68	1		T69	1
valid_sources[0x50]	103	1		T45	1		T47	1		T68	2
valid_sources[0x51]	58	1		T46	1		T59	1		T85	1
valid_sources[0x52]	73	1		T68	2		T69	1		T74	5
valid_sources[0x53]	88	1		T68	1		T59	2		T74	9
valid_sources[0x54]	51	1		T45	1		T68	1		T85	3
valid_sources[0x55]	106	1		T45	1		T68	1		T59	1
valid_sources[0x56]	59	1		T45	1		T59	1		T60	3
valid_sources[0x57]	85	1		T49	1		T68	2		T69	2
valid_sources[0x58]	134	1		T143	1		T48	1		T46	1
valid_sources[0x59]	73	1		T69	1		T60	1		T72	1
valid_sources[0x5a]	193	1		T45	1		T67	5		T69	2
valid_sources[0x5b]	80	1		T45	1		T68	2		T59	1
valid_sources[0x5c]	60	1		T46	1		T68	1		T59	2
valid_sources[0x5d]	58	1		T47	1		T67	1		T68	1
valid_sources[0x5e]	83	1		T153	1		T47	4		T59	1
valid_sources[0x5f]	73	1		T67	3		T68	2		T59	1
valid_sources[0x60]	63	1		T68	1		T71	3		T72	1
valid_sources[0x61]	64	1		T140	1		T60	3		T72	1
valid_sources[0x62]	99	1		T41	1		T68	1		T69	1
valid_sources[0x63]	92	1		T46	1		T47	2		T67	1
valid_sources[0x64]	60	1		T159	1		T68	2		T59	1
valid_sources[0x65]	57	1		T67	1		T68	1		T59	1
valid_sources[0x66]	64	1		T122	1		T67	1		T68	1
valid_sources[0x67]	47	1		T41	1		T143	1		T47	2
valid_sources[0x68]	67	1		T38	3		T45	2		T68	2
valid_sources[0x69]	97	1		T140	1		T68	1		T59	2
valid_sources[0x6a]	70	1		T68	1		T60	1		T118	1
valid_sources[0x6b]	135	1		T70	16		T160	1		T46	1
valid_sources[0x6c]	59	1		T47	3		T77	1		T68	1
valid_sources[0x6d]	276	1		T148	2		T68	1		T69	2
valid_sources[0x6e]	67	1		T142	2		T61	1		T46	1
valid_sources[0x6f]	64	1		T68	1		T60	1		T72	1
valid_sources[0x70]	56	1		T155	1		T47	1		T68	1
valid_sources[0x71]	85	1		T47	1		T68	3		T69	2
valid_sources[0x72]	58	1		T46	1		T67	2		T68	3
valid_sources[0x73]	215	1		T147	1		T161	15		T47	5
valid_sources[0x74]	58	1		T48	1		T49	2		T59	1
valid_sources[0x75]	70	1		T39	1		T143	1		T46	1
valid_sources[0x76]	69	1		T50	1		T157	1		T68	1
valid_sources[0x77]	79	1		T154	2		T68	2		T59	3
valid_sources[0x78]	80	1		T50	2		T119	1		T45	2
valid_sources[0x79]	85	1		T143	1		T45	2		T46	2
valid_sources[0x7a]	89	1		T145	2		T49	1		T68	1
valid_sources[0x7b]	88	1		T45	1		T67	7		T72	2
valid_sources[0x7c]	105	1		T143	1		T68	1		T60	4
valid_sources[0x7d]	121	1		T56	1		T162	15		T61	1
valid_sources[0x7e]	57	1		T45	1		T69	2		T60	1
valid_sources[0x7f]	52	1		T43	1		T72	2		T85	3
valid_sources[0x80]	65	1		T45	1		T46	1		T59	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

6260

1

T48

3

T45

17

T49

29

values[0x0]

all_enables

biggest_size

6007

1

T2

3

T3

2

T35

1

values[0x1]

all_enables

biggest_size

5811

1

T2

1

T3

1

T70

2