Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	258174	1		T1	26		T4	4		T5	4
full_word	578584	1		T1	4		T4	1		T13	80

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	836478	1		T1	30		T4	5		T13	80
auto[TlIntgErrCmd]	94	1		T45	3		T46	1		T47	4
auto[TlIntgErrData]	103	1		T45	3		T46	6		T47	3
auto[TlIntgErrBoth]	83	1		T45	4		T46	3		T47	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	515737	1		T13	80		T22	8		T15	20
auto[1]	321021	1		T1	30		T4	5		T5	5

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	216045	1		T22	6		T15	11		T8	17
auto[TlIntgErrNone]	partial	auto[1]	41877	1		T1	26		T4	4		T5	4
auto[TlIntgErrNone]	full_word	auto[0]	299568	1		T13	80		T22	2		T15	9
auto[TlIntgErrNone]	full_word	auto[1]	278988	1		T1	4		T4	1		T5	1
auto[TlIntgErrCmd]	partial	auto[0]	30	1		T47	2		T127	2		T128	1
auto[TlIntgErrCmd]	partial	auto[1]	51	1		T45	2		T47	2		T127	3
auto[TlIntgErrCmd]	full_word	auto[0]	5	1		T129	1		T131	2		T134	1
auto[TlIntgErrCmd]	full_word	auto[1]	8	1		T45	1		T46	1		T127	1
auto[TlIntgErrData]	partial	auto[0]	42	1		T45	2		T46	2		T47	1
auto[TlIntgErrData]	partial	auto[1]	53	1		T45	1		T46	4		T47	2
auto[TlIntgErrData]	full_word	auto[0]	6	1		T129	1		T133	1		T134	1
auto[TlIntgErrData]	full_word	auto[1]	2	1		T130	1		T133	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	38	1		T45	3		T46	2		T127	4
auto[TlIntgErrBoth]	partial	auto[1]	38	1		T45	1		T46	1		T47	2
auto[TlIntgErrBoth]	full_word	auto[0]	3	1		T127	1		T136	1		T137	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1		T47	1		T130	1		T131	1