Unified Coverage Report :: Module :: rv_dm_regs_csr_assert_fpv

Module : rv_dm_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_dm_csr_assert_0/rv_dm_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_dm_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_dm_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
77.03	90.91	61.70	87.88		57.14	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_dm_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	30351926	11185	0	0
late_debug_enable_rd_A	30351926	1922	0	0
late_debug_enable_regwen_rd_A	30351926	1734	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30351926	11185	0	0
T45	18312	1	0	0
T46	20359	3	0	0
T47	32186	4	0	0
T59	451175	46	0	0
T60	510517	41	0	0
T67	83691	43	0	0
T68	119522	125	0	0
T69	3815	307	0	0
T71	25483	30	0	0
T72	306013	87	0	0

late_debug_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30351926	1922	0	0
T48	10352	3	0	0
T49	47522	54	0	0
T59	451175	36	0	0
T60	510517	53	0	0
T71	25483	45	0	0
T77	5394	2	0	0
T84	7051	21	0	0
T100	49815	23	0	0
T110	731013	267	0	0
T121	404750	50	0	0

late_debug_enable_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30351926	1734	0	0
T48	10352	8	0	0
T49	47522	16	0	0
T59	451175	32	0	0
T60	510517	43	0	0
T71	25483	38	0	0
T77	5394	4	0	0
T84	7051	31	0	0
T100	49815	30	0	0
T110	731013	318	0	0
T121	404750	38	0	0