Unified Coverage Report :: Module :: prim_generic_clock_mux2

Module : prim_generic_clock_mux2

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_prim_clock_mux2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_prim_rst_n_mux2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_scan.i_dft_tck_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_generic_clock_mux2

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Module : prim_generic_clock_mux2

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T36

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T36
1	1	Covered	T8,T36

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T8,T36
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_generic_clock_mux2

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	18177506	18176672	0	0
selKnown1	16404448	16403614	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	18177506	18176672	0	0
T1	44676	44674	0	0
T2	310	308	0	0
T3	370	368	0	0
T4	9652	9650	0	0
T6	7792	7790	0	0
T8	5	3	0	0
T11	0	17	0	0
T13	330	328	0	0
T16	2	0	0	0
T20	0	9	0	0
T24	4560	4558	0	0
T27	98	96	0	0
T28	0	90	0	0
T29	0	73	0	0
T30	6	4	0	0
T31	0	5	0	0
T32	0	40	0	0
T33	0	40	0	0
T35	342	340	0	0
T36	0	7	0	0
T38	310	308	0	0
T40	2	0	0	0
T41	2	0	0	0
T44	2	0	0	0
T50	2	0	0	0
T51	336	334	0	0
T119	2	0	0	0
T122	2	0	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	16404448	16403614	0	0
T1	77019	77017	0	0
T2	3045	3043	0	0
T3	2107	2105	0	0
T4	8888	8886	0	0
T6	27940	27938	0	0
T8	6	4	0	0
T11	0	4	0	0
T13	2526	2524	0	0
T16	2	0	0	0
T20	0	8	0	0
T24	4273	4271	0	0
T27	98	96	0	0
T28	0	90	0	0
T29	0	72	0	0
T30	2	0	0	0
T32	0	40	0	0
T33	0	40	0	0
T35	3131	3129	0	0
T36	0	2	0	0
T38	1418	1416	0	0
T40	2	0	0	0
T41	2	0	0	0
T44	2	0	0	0
T50	2	0	0	0
T51	1463	1461	0	0
T88	0	16	0	0
T119	2	0	0	0
T122	2	0	0	0

Line Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T36

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T36
1	1	Covered	T8,T36

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T36
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	4382180	4382077	0	0
selKnown1	2609263	2609160	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	4382180	4382077	0	0
T1	22338	22337	0	0
T2	155	154	0	0
T3	185	184	0	0
T4	4826	4825	0	0
T6	3896	3895	0	0
T13	165	164	0	0
T24	2280	2279	0	0
T35	171	170	0	0
T38	155	154	0	0
T51	168	167	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2609263	2609160	0	0
T1	54681	54680	0	0
T2	2890	2889	0	0
T3	1922	1921	0	0
T4	4062	4061	0	0
T6	24044	24043	0	0
T13	2361	2360	0	0
T24	1993	1992	0	0
T35	2960	2959	0	0
T38	1263	1262	0	0
T51	1295	1294	0	0

Line Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T36

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T36
1	1	Covered	T8,T36

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T36
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	362	259	0	0
selKnown1	355	252	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	362	259	0	0
T8	2	1	0	0
T11	0	3	0	0
T16	1	0	0	0
T20	0	4	0	0
T27	49	48	0	0
T28	0	45	0	0
T29	0	37	0	0
T30	1	0	0	0
T32	0	20	0	0
T33	0	20	0	0
T36	0	7	0	0
T40	1	0	0	0
T41	1	0	0	0
T44	1	0	0	0
T50	1	0	0	0
T88	0	8	0	0
T119	1	0	0	0
T122	1	0	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	355	252	0	0
T8	3	2	0	0
T11	0	2	0	0
T16	1	0	0	0
T20	0	4	0	0
T27	49	48	0	0
T28	0	45	0	0
T29	0	36	0	0
T30	1	0	0	0
T32	0	20	0	0
T33	0	20	0	0
T36	0	1	0	0
T40	1	0	0	0
T41	1	0	0	0
T44	1	0	0	0
T50	1	0	0	0
T88	0	8	0	0
T119	1	0	0	0
T122	1	0	0	0

Line Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T36

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T36
1	1	Covered	T8,T36

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T8,T36
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	13793270	13792956	0	0
selKnown1	13793270	13792956	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	13793270	13792956	0	0
T1	22338	22337	0	0
T2	155	154	0	0
T3	185	184	0	0
T4	4826	4825	0	0
T6	3896	3895	0	0
T13	165	164	0	0
T24	2280	2279	0	0
T35	171	170	0	0
T38	155	154	0	0
T51	168	167	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	13793270	13792956	0	0
T1	22338	22337	0	0
T2	155	154	0	0
T3	185	184	0	0
T4	4826	4825	0	0
T6	3896	3895	0	0
T13	165	164	0	0
T24	2280	2279	0	0
T35	171	170	0	0
T38	155	154	0	0
T51	168	167	0	0

Line Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T36

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T36
1	1	Covered	T8,T36

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T8,T36
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	1694	1380	0	0
selKnown1	1560	1246	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	1694	1380	0	0
T8	3	2	0	0
T11	0	14	0	0
T16	1	0	0	0
T20	0	5	0	0
T27	49	48	0	0
T28	0	45	0	0
T29	0	36	0	0
T30	5	4	0	0
T31	0	5	0	0
T32	0	20	0	0
T33	0	20	0	0
T40	1	0	0	0
T41	1	0	0	0
T44	1	0	0	0
T50	1	0	0	0
T119	1	0	0	0
T122	1	0	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	1560	1246	0	0
T8	3	2	0	0
T11	0	2	0	0
T16	1	0	0	0
T20	0	4	0	0
T27	49	48	0	0
T28	0	45	0	0
T29	0	36	0	0
T30	1	0	0	0
T32	0	20	0	0
T33	0	20	0	0
T36	0	1	0	0
T40	1	0	0	0
T41	1	0	0	0
T44	1	0	0	0
T50	1	0	0	0
T88	0	8	0	0
T119	1	0	0	0
T122	1	0	0	0