Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	190062	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	559298	1		T2	1		T4	7		T6	7

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	463174	1		T9	8		T24	8		T17	18
values[0x0]	141283	1		T2	2		T4	22		T6	13
values[0x1]	144903	1		T2	4		T4	16		T6	16

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	145536	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	603824	1		T2	3		T4	9		T6	11

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2619	1		T2	1		T48	18		T46	49
valid_sources[0x01]	3452	1		T48	20		T46	37		T47	3
valid_sources[0x02]	2628	1		T45	50		T48	20		T46	41
valid_sources[0x03]	3022	1		T27	1		T48	37		T46	39
valid_sources[0x04]	3612	1		T45	6		T48	33		T46	47
valid_sources[0x05]	2813	1		T48	13		T46	36		T47	4
valid_sources[0x06]	3622	1		T21	1		T48	27		T46	38
valid_sources[0x07]	2556	1		T48	30		T46	37		T47	6
valid_sources[0x08]	2989	1		T48	24		T46	44		T47	4
valid_sources[0x09]	2970	1		T45	1		T48	24		T46	58
valid_sources[0x0a]	3113	1		T45	16		T48	23		T46	37
valid_sources[0x0b]	2575	1		T14	1		T45	2		T48	30
valid_sources[0x0c]	2703	1		T45	4		T48	25		T46	29
valid_sources[0x0d]	2289	1		T48	46		T46	39		T47	3
valid_sources[0x0e]	3427	1		T48	20		T46	36		T47	3
valid_sources[0x0f]	3534	1		T12	3		T48	32		T46	45
valid_sources[0x10]	2598	1		T48	23		T46	35		T47	7
valid_sources[0x11]	3887	1		T45	21		T48	32		T46	40
valid_sources[0x12]	2690	1		T48	16		T46	36		T47	7
valid_sources[0x13]	2771	1		T11	1		T133	1		T48	24
valid_sources[0x14]	3233	1		T45	32		T48	28		T46	37
valid_sources[0x15]	2798	1		T11	1		T45	20		T48	39
valid_sources[0x16]	2873	1		T13	1		T14	3		T48	36
valid_sources[0x17]	2434	1		T45	2		T48	19		T46	25
valid_sources[0x18]	3309	1		T23	36		T48	38		T46	43
valid_sources[0x19]	2618	1		T20	2		T45	29		T48	13
valid_sources[0x1a]	3094	1		T45	6		T48	21		T46	41
valid_sources[0x1b]	2537	1		T45	4		T48	13		T46	48
valid_sources[0x1c]	2606	1		T45	69		T48	22		T46	48
valid_sources[0x1d]	2917	1		T21	4		T45	5		T48	25
valid_sources[0x1e]	2668	1		T48	18		T46	41		T47	2
valid_sources[0x1f]	2652	1		T20	1		T48	14		T46	35
valid_sources[0x20]	3073	1		T11	1		T45	1		T48	20
valid_sources[0x21]	2978	1		T11	1		T48	35		T46	48
valid_sources[0x22]	3579	1		T11	1		T48	17		T46	41
valid_sources[0x23]	2395	1		T16	2		T45	27		T48	39
valid_sources[0x24]	2543	1		T48	23		T46	39		T47	3
valid_sources[0x25]	2450	1		T6	1		T13	1		T21	1
valid_sources[0x26]	2733	1		T48	28		T46	34		T47	3
valid_sources[0x27]	2473	1		T45	5		T48	31		T46	50
valid_sources[0x28]	3117	1		T45	21		T48	37		T46	51
valid_sources[0x29]	3075	1		T26	1		T14	1		T48	20
valid_sources[0x2a]	3083	1		T48	18		T46	38		T47	11
valid_sources[0x2b]	2738	1		T6	1		T11	1		T13	2
valid_sources[0x2c]	2660	1		T14	2		T45	3		T48	14
valid_sources[0x2d]	2690	1		T45	16		T48	15		T46	47
valid_sources[0x2e]	3101	1		T13	4		T45	7		T48	17
valid_sources[0x2f]	2958	1		T20	1		T45	12		T48	28
valid_sources[0x30]	2614	1		T45	9		T48	25		T46	30
valid_sources[0x31]	2742	1		T48	24		T46	41		T47	7
valid_sources[0x32]	2443	1		T14	3		T45	37		T48	35
valid_sources[0x33]	2383	1		T48	16		T46	41		T47	5
valid_sources[0x34]	3043	1		T45	7		T48	29		T46	51
valid_sources[0x35]	3099	1		T6	1		T48	16		T46	45
valid_sources[0x36]	2486	1		T11	1		T48	22		T46	40
valid_sources[0x37]	3150	1		T6	1		T27	1		T45	2
valid_sources[0x38]	2759	1		T48	29		T46	49		T47	8
valid_sources[0x39]	3055	1		T13	1		T25	1		T45	56
valid_sources[0x3a]	2649	1		T45	3		T48	29		T46	53
valid_sources[0x3b]	3021	1		T45	14		T48	26		T46	31
valid_sources[0x3c]	2254	1		T48	20		T46	23		T47	4
valid_sources[0x3d]	5887	1		T13	3		T14	1		T45	27
valid_sources[0x3e]	3038	1		T4	38		T12	5		T17	36
valid_sources[0x3f]	2362	1		T45	32		T48	18		T46	41
valid_sources[0x40]	2309	1		T11	1		T45	19		T48	19
valid_sources[0x41]	2623	1		T13	2		T45	35		T48	29
valid_sources[0x42]	2560	1		T25	1		T45	6		T48	21
valid_sources[0x43]	2899	1		T45	53		T48	38		T46	38
valid_sources[0x44]	2776	1		T11	1		T133	1		T48	32
valid_sources[0x45]	2990	1		T45	5		T48	25		T46	41
valid_sources[0x46]	2690	1		T48	28		T46	48		T47	7
valid_sources[0x47]	3443	1		T6	1		T45	2		T48	16
valid_sources[0x48]	2948	1		T26	2		T14	2		T27	1
valid_sources[0x49]	2747	1		T13	1		T21	1		T45	14
valid_sources[0x4a]	2878	1		T80	16		T45	9		T48	21
valid_sources[0x4b]	2870	1		T20	1		T45	22		T48	24
valid_sources[0x4c]	3107	1		T45	21		T48	26		T46	46
valid_sources[0x4d]	2400	1		T45	3		T48	23		T46	32
valid_sources[0x4e]	2463	1		T48	24		T46	35		T47	5
valid_sources[0x4f]	2785	1		T45	288		T48	37		T46	30
valid_sources[0x50]	3378	1		T11	2		T45	2		T48	33
valid_sources[0x51]	3243	1		T45	40		T48	26		T46	44
valid_sources[0x52]	3041	1		T21	1		T45	20		T48	41
valid_sources[0x53]	3085	1		T21	2		T48	39		T46	49
valid_sources[0x54]	2502	1		T11	1		T13	2		T45	9
valid_sources[0x55]	2423	1		T13	1		T45	6		T48	38
valid_sources[0x56]	2928	1		T13	3		T45	20		T48	22
valid_sources[0x57]	2743	1		T11	1		T45	19		T48	12
valid_sources[0x58]	3855	1		T11	1		T14	3		T48	28
valid_sources[0x59]	2720	1		T13	2		T48	23		T46	37
valid_sources[0x5a]	3738	1		T6	1		T14	4		T45	11
valid_sources[0x5b]	3396	1		T27	1		T48	18		T46	56
valid_sources[0x5c]	3067	1		T6	2		T45	31		T48	29
valid_sources[0x5d]	2908	1		T13	1		T45	1		T48	26
valid_sources[0x5e]	2682	1		T13	1		T19	1		T48	22
valid_sources[0x5f]	2728	1		T11	1		T45	20		T48	35
valid_sources[0x60]	3594	1		T48	18		T46	40		T47	9
valid_sources[0x61]	2659	1		T11	1		T14	2		T45	40
valid_sources[0x62]	2869	1		T48	21		T46	44		T47	8
valid_sources[0x63]	3043	1		T45	4		T48	27		T46	55
valid_sources[0x64]	2769	1		T13	1		T45	17		T48	18
valid_sources[0x65]	2837	1		T48	33		T46	22		T47	9
valid_sources[0x66]	2711	1		T13	4		T48	29		T46	49
valid_sources[0x67]	2426	1		T13	4		T25	1		T48	20
valid_sources[0x68]	2515	1		T48	16		T46	26		T47	5
valid_sources[0x69]	3734	1		T11	1		T14	1		T45	287
valid_sources[0x6a]	2758	1		T45	6		T48	28		T46	39
valid_sources[0x6b]	3135	1		T13	2		T26	1		T45	285
valid_sources[0x6c]	3438	1		T48	13		T46	43		T47	7
valid_sources[0x6d]	2450	1		T6	4		T13	1		T134	1
valid_sources[0x6e]	2738	1		T12	2		T14	3		T48	19
valid_sources[0x6f]	4647	1		T14	3		T45	9		T48	17
valid_sources[0x70]	2681	1		T45	9		T48	10		T46	35
valid_sources[0x71]	2856	1		T14	6		T45	3		T48	14
valid_sources[0x72]	3091	1		T12	1		T13	3		T20	1
valid_sources[0x73]	2651	1		T14	1		T48	25		T46	45
valid_sources[0x74]	2925	1		T11	1		T48	27		T46	32
valid_sources[0x75]	3161	1		T6	1		T48	23		T46	35
valid_sources[0x76]	4064	1		T48	24		T46	32		T47	3
valid_sources[0x77]	2817	1		T11	3		T19	1		T48	15
valid_sources[0x78]	2881	1		T19	1		T45	9		T48	29
valid_sources[0x79]	2700	1		T45	22		T48	20		T46	51
valid_sources[0x7a]	3088	1		T45	19		T48	44		T46	36
valid_sources[0x7b]	2708	1		T11	1		T45	275		T48	23
valid_sources[0x7c]	3098	1		T45	35		T48	27		T46	37
valid_sources[0x7d]	3816	1		T13	1		T14	3		T45	1
valid_sources[0x7e]	3047	1		T13	1		T26	1		T48	22
valid_sources[0x7f]	2713	1		T45	6		T48	39		T46	43
valid_sources[0x80]	2486	1		T45	18		T48	31		T46	45

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

280907

1

T9

3

T24

5

T17

11

values[0x0]

all_enables

biggest_size

139641

1

T2

1

T4

4

T6

4

values[0x1]

all_enables

biggest_size

138750

1

T4

3

T6

3

T9

12

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4927	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	20011	1		T3	2		T41	2		T40	1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	9860	1		T45	35		T48	34		T46	68
values[0x0]	7540	1		T3	5		T41	1		T40	1
values[0x1]	7538	1		T3	5		T41	2		T40	4

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3731	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	21207	1		T3	2		T41	2		T40	1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	65	1		T135	1		T74	1		T66	2
valid_sources[0x01]	81	1		T136	1		T137	1		T74	7
valid_sources[0x02]	75	1		T62	1		T76	10		T66	1
valid_sources[0x03]	72	1		T15	1		T76	11		T66	1
valid_sources[0x04]	64	1		T74	5		T66	2		T91	2
valid_sources[0x05]	54	1		T136	1		T138	1		T84	8
valid_sources[0x06]	86	1		T75	3		T91	1		T92	1
valid_sources[0x07]	46	1		T62	1		T46	1		T66	1
valid_sources[0x08]	108	1		T66	6		T78	31		T91	1
valid_sources[0x09]	57	1		T139	1		T84	2		T106	1
valid_sources[0x0a]	153	1		T137	1		T140	1		T75	1
valid_sources[0x0b]	58	1		T43	1		T75	2		T66	5
valid_sources[0x0c]	74	1		T57	4		T141	1		T142	2
valid_sources[0x0d]	63	1		T143	1		T75	2		T66	9
valid_sources[0x0e]	96	1		T74	19		T66	1		T84	6
valid_sources[0x0f]	70	1		T76	5		T66	2		T90	3
valid_sources[0x10]	55	1		T53	1		T66	1		T87	1
valid_sources[0x11]	87	1		T50	1		T144	1		T145	1
valid_sources[0x12]	113	1		T62	1		T57	5		T121	1
valid_sources[0x13]	103	1		T46	2		T75	1		T66	2
valid_sources[0x14]	69	1		T146	1		T137	1		T66	2
valid_sources[0x15]	99	1		T139	1		T46	1		T66	1
valid_sources[0x16]	77	1		T141	1		T74	3		T66	1
valid_sources[0x17]	105	1		T66	1		T92	1		T84	2
valid_sources[0x18]	150	1		T48	3		T78	21		T84	4
valid_sources[0x19]	89	1		T46	1		T75	1		T76	6
valid_sources[0x1a]	93	1		T50	4		T48	2		T75	3
valid_sources[0x1b]	52	1		T138	1		T74	3		T66	1
valid_sources[0x1c]	80	1		T76	20		T66	1		T91	1
valid_sources[0x1d]	87	1		T46	1		T74	2		T75	4
valid_sources[0x1e]	71	1		T74	10		T66	4		T91	1
valid_sources[0x1f]	84	1		T44	1		T76	16		T66	2
valid_sources[0x20]	91	1		T147	4		T45	2		T92	2
valid_sources[0x21]	100	1		T41	1		T148	1		T74	6
valid_sources[0x22]	86	1		T44	1		T121	1		T54	2
valid_sources[0x23]	195	1		T66	1		T91	1		T84	4
valid_sources[0x24]	104	1		T46	4		T75	2		T66	1
valid_sources[0x25]	87	1		T3	1		T50	1		T66	1
valid_sources[0x26]	85	1		T62	1		T142	1		T139	2
valid_sources[0x27]	75	1		T75	2		T66	2		T78	1
valid_sources[0x28]	128	1		T138	1		T75	1		T66	1
valid_sources[0x29]	84	1		T75	1		T66	6		T92	1
valid_sources[0x2a]	106	1		T74	2		T76	1		T66	4
valid_sources[0x2b]	102	1		T146	1		T136	1		T144	1
valid_sources[0x2c]	113	1		T74	2		T66	2		T77	9
valid_sources[0x2d]	99	1		T44	1		T46	4		T74	2
valid_sources[0x2e]	70	1		T46	1		T66	2		T84	4
valid_sources[0x2f]	54	1		T140	1		T66	1		T91	2
valid_sources[0x30]	94	1		T46	4		T75	1		T66	1
valid_sources[0x31]	51	1		T140	1		T66	6		T92	1
valid_sources[0x32]	79	1		T75	7		T92	1		T122	2
valid_sources[0x33]	155	1		T76	54		T66	2		T91	2
valid_sources[0x34]	151	1		T46	1		T66	1		T122	1
valid_sources[0x35]	83	1		T53	1		T66	1		T122	3
valid_sources[0x36]	173	1		T75	2		T66	1		T92	2
valid_sources[0x37]	860	1		T15	1		T136	1		T48	2
valid_sources[0x38]	76	1		T53	1		T149	1		T150	1
valid_sources[0x39]	111	1		T142	1		T135	1		T45	3
valid_sources[0x3a]	85	1		T3	5		T145	1		T46	2
valid_sources[0x3b]	64	1		T139	3		T91	1		T92	3
valid_sources[0x3c]	52	1		T46	1		T74	4		T75	2
valid_sources[0x3d]	75	1		T45	3		T74	3		T76	2
valid_sources[0x3e]	63	1		T135	1		T74	8		T66	3
valid_sources[0x3f]	147	1		T58	11		T151	4		T140	1
valid_sources[0x40]	91	1		T53	1		T46	1		T74	10
valid_sources[0x41]	78	1		T66	1		T78	5		T81	4
valid_sources[0x42]	83	1		T140	1		T66	2		T91	1
valid_sources[0x43]	134	1		T141	1		T66	3		T93	7
valid_sources[0x44]	30	1		T66	1		T91	1		T92	1
valid_sources[0x45]	99	1		T43	2		T46	1		T74	4
valid_sources[0x46]	161	1		T137	2		T138	1		T84	4
valid_sources[0x47]	95	1		T152	4		T66	2		T78	6
valid_sources[0x48]	77	1		T74	1		T76	6		T66	3
valid_sources[0x49]	124	1		T75	2		T66	6		T84	2
valid_sources[0x4a]	63	1		T136	2		T74	1		T66	1
valid_sources[0x4b]	106	1		T84	2		T122	5		T123	3
valid_sources[0x4c]	98	1		T141	1		T153	6		T154	1
valid_sources[0x4d]	86	1		T137	1		T140	1		T75	5
valid_sources[0x4e]	188	1		T135	1		T138	1		T46	2
valid_sources[0x4f]	76	1		T135	1		T76	3		T66	2
valid_sources[0x50]	113	1		T46	5		T75	5		T76	5
valid_sources[0x51]	55	1		T66	5		T123	4		T155	5
valid_sources[0x52]	67	1		T3	1		T151	2		T46	1
valid_sources[0x53]	111	1		T49	1		T43	1		T75	5
valid_sources[0x54]	125	1		T74	3		T99	1		T122	1
valid_sources[0x55]	86	1		T84	2		T122	1		T123	5
valid_sources[0x56]	99	1		T75	8		T66	1		T84	2
valid_sources[0x57]	92	1		T142	1		T144	1		T46	1
valid_sources[0x58]	104	1		T142	1		T75	4		T66	1
valid_sources[0x59]	94	1		T5	1		T48	2		T66	2
valid_sources[0x5a]	100	1		T48	3		T46	2		T74	5
valid_sources[0x5b]	45	1		T75	1		T91	3		T99	1
valid_sources[0x5c]	100	1		T83	1		T91	1		T122	3
valid_sources[0x5d]	80	1		T48	6		T91	1		T84	2
valid_sources[0x5e]	121	1		T148	1		T76	6		T78	13
valid_sources[0x5f]	140	1		T53	1		T150	1		T48	8
valid_sources[0x60]	75	1		T74	3		T66	4		T77	4
valid_sources[0x61]	76	1		T5	1		T76	16		T66	3
valid_sources[0x62]	72	1		T135	1		T46	1		T66	3
valid_sources[0x63]	73	1		T142	1		T75	1		T91	3
valid_sources[0x64]	154	1		T148	1		T48	1		T47	75
valid_sources[0x65]	73	1		T146	3		T138	1		T46	6
valid_sources[0x66]	110	1		T44	1		T144	1		T45	3
valid_sources[0x67]	77	1		T141	1		T75	5		T84	2
valid_sources[0x68]	87	1		T144	1		T48	1		T75	3
valid_sources[0x69]	92	1		T140	1		T45	3		T46	1
valid_sources[0x6a]	78	1		T15	1		T150	1		T74	1
valid_sources[0x6b]	298	1		T44	1		T138	1		T76	26
valid_sources[0x6c]	88	1		T121	2		T150	2		T74	5
valid_sources[0x6d]	50	1		T154	2		T92	1		T84	4
valid_sources[0x6e]	69	1		T75	3		T66	2		T91	2
valid_sources[0x6f]	71	1		T5	1		T138	1		T148	1
valid_sources[0x70]	110	1		T5	1		T66	2		T78	34
valid_sources[0x71]	55	1		T15	2		T140	1		T150	1
valid_sources[0x72]	75	1		T48	2		T74	1		T75	1
valid_sources[0x73]	57	1		T44	1		T136	1		T46	2
valid_sources[0x74]	186	1		T138	1		T48	1		T47	126
valid_sources[0x75]	72	1		T75	2		T66	3		T91	1
valid_sources[0x76]	67	1		T142	1		T46	2		T75	1
valid_sources[0x77]	121	1		T121	1		T140	1		T74	5
valid_sources[0x78]	75	1		T44	1		T46	2		T74	5
valid_sources[0x79]	68	1		T150	2		T48	1		T75	1
valid_sources[0x7a]	86	1		T41	1		T74	1		T76	3
valid_sources[0x7b]	102	1		T46	2		T75	1		T66	3
valid_sources[0x7c]	88	1		T74	1		T76	17		T66	1
valid_sources[0x7d]	90	1		T146	2		T142	1		T74	13
valid_sources[0x7e]	252	1		T48	1		T46	1		T75	1
valid_sources[0x7f]	133	1		T66	1		T77	1		T92	1
valid_sources[0x80]	65	1		T138	1		T75	2		T66	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

6862

1

T45

13

T48

34

T46

29

values[0x0]

all_enables

biggest_size

6781

1

T3

1

T41

1

T5

2

values[0x1]

all_enables

biggest_size

6368

1

T3

1

T41

1

T40

1