Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	224962	1		T2	5		T4	31		T6	22
full_word	560768	1		T2	1		T4	7		T6	7

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	785420	1		T2	6		T4	38		T6	29
auto[TlIntgErrCmd]	98	1		T45	2		T46	8		T90	5
auto[TlIntgErrData]	101	1		T45	4		T46	9		T90	4
auto[TlIntgErrBoth]	111	1		T45	4		T46	3		T90	1

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	464837	1		T9	8		T24	8		T17	18
auto[1]	320893	1		T2	6		T4	38		T6	29

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	183643	1		T9	5		T24	3		T17	7
auto[TlIntgErrNone]	partial	auto[1]	41042	1		T2	5		T4	31		T6	22
auto[TlIntgErrNone]	full_word	auto[0]	281073	1		T9	3		T24	5		T17	11
auto[TlIntgErrNone]	full_word	auto[1]	279662	1		T2	1		T4	7		T6	7
auto[TlIntgErrCmd]	partial	auto[0]	33	1		T46	3		T91	1		T125	2
auto[TlIntgErrCmd]	partial	auto[1]	54	1		T46	2		T90	5		T91	4
auto[TlIntgErrCmd]	full_word	auto[0]	4	1		T126	1		T128	1		T129	1
auto[TlIntgErrCmd]	full_word	auto[1]	7	1		T45	2		T46	3		T125	1
auto[TlIntgErrData]	partial	auto[0]	39	1		T45	1		T46	5		T90	2
auto[TlIntgErrData]	partial	auto[1]	53	1		T45	2		T46	3		T90	1
auto[TlIntgErrData]	full_word	auto[0]	3	1		T90	1		T125	1		T130	1
auto[TlIntgErrData]	full_word	auto[1]	6	1		T45	1		T46	1		T91	1
auto[TlIntgErrBoth]	partial	auto[0]	39	1		T45	3		T46	2		T90	1
auto[TlIntgErrBoth]	partial	auto[1]	59	1		T45	1		T46	1		T91	6
auto[TlIntgErrBoth]	full_word	auto[0]	3	1		T128	1		T131	1		T129	1
auto[TlIntgErrBoth]	full_word	auto[1]	10	1		T125	1		T119	1		T127	2