Unified Coverage Report :: Module :: rv_dm_regs_csr_assert_fpv

Module : rv_dm_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_dm_csr_assert_0/rv_dm_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_dm_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_dm_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.35	87.88	61.70	87.54		57.14	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_dm_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	28660836	12978	0	0
late_debug_enable_rd_A	28660836	1868	0	0
late_debug_enable_regwen_rd_A	28660836	2113	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28660836	12978	0	0
T45	50828	1	0	0
T46	163732	2	0	0
T47	12839	65	0	0
T66	523093	125	0	0
T74	38521	166	0	0
T75	14263	326	0	0
T76	202572	248	0	0
T77	11100	49	0	0
T78	3600	425	0	0
T90	53904	3	0	0

late_debug_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28660836	1868	0	0
T67	301482	19	0	0
T75	14263	52	0	0
T83	6231	2	0	0
T86	5176	2	0	0
T90	53904	24	0	0
T93	16481	101	0	0
T106	4973	5	0	0
T109	9090	8	0	0
T119	102616	31	0	0
T120	15849	186	0	0

late_debug_enable_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28660836	2113	0	0
T67	301482	26	0	0
T75	14263	45	0	0
T81	5698	9	0	0
T83	6231	6	0	0
T86	5176	6	0	0
T90	53904	22	0	0
T93	16481	154	0	0
T102	20447	34	0	0
T119	102616	53	0	0
T120	15849	134	0	0